mem: Adopt a memory namespace for memories

Encapsulate every class inheriting from Abstract or Physical
memories, and the memory controller in a memory namespace.

Change-Id: I228f7e55efc395089e3616ae0a0a6325867bd782
Issued-on: https://gem5.atlassian.net/browse/GEM5-983
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47309
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

src/arch/arm/semihosting.cc

@@ -551,7 +551,7 @@ ArmSemihosting::gatherHeapInfo(ThreadContext *tc, bool aarch64,
                                Addr &heap_base, Addr &heap_limit,
                                Addr &stack_base, Addr &stack_limit)
 {
-    const PhysicalMemory &phys = tc->getSystemPtr()->getPhysMem();
+    const memory::PhysicalMemory &phys = tc->getSystemPtr()->getPhysMem();
     const AddrRangeList memories = phys.getConfAddrRanges();
     fatal_if(memories.size() < 1, "No memories reported from System");
     warn_if(memories.size() > 1, "Multiple physical memory ranges available. "

src/cpu/kvm/vm.cc

@@ -50,6 +50,7 @@
 
 #include "cpu/kvm/base.hh"
 #include "debug/Kvm.hh"
+#include "mem/physical.hh"
 #include "params/KvmVM.hh"
 #include "sim/system.hh"
 
@@ -355,7 +356,7 @@ void
 KvmVM::delayedStartup()
 {
     assert(system); // set by the system during its construction
-    const std::vector<BackingStoreEntry> &memories(
+    const std::vector<memory::BackingStoreEntry> &memories(
         system->getPhysMem().getBackingStore());
 
     DPRINTF(Kvm, "Mapping %i memory region(s)\n", memories.size());

src/cpu/o3/inst_queue.hh

@@ -65,7 +65,11 @@ namespace gem5
 {
 
 struct O3CPUParams;
+
+namespace memory
+{
 class MemInterface;
+} // namespace memory
 
 namespace o3
 {
@@ -284,7 +288,7 @@ class InstructionQueue
     CPU *cpu;
 
     /** Cache interface. */
-    MemInterface *dcacheInterface;
+    memory::MemInterface *dcacheInterface;
 
     /** Pointer to IEW stage. */
     IEW *iewStage;

src/mem/AbstractMemory.py

@@ -43,7 +43,7 @@ class AbstractMemory(ClockedObject):
     type = 'AbstractMemory'
     abstract = True
     cxx_header = "mem/abstract_mem.hh"
-    cxx_class = 'gem5::AbstractMemory'
+    cxx_class = 'gem5::memory::AbstractMemory'
 
     # A default memory size of 128 MiB (starting at 0) is used to
     # simplify the regressions

src/mem/CfiMemory.py

@@ -43,7 +43,7 @@ from m5.util.fdthelper import FdtNode, FdtPropertyWords
 class CfiMemory(AbstractMemory):
     type = 'CfiMemory'
     cxx_header = "mem/cfi_mem.hh"
-    cxx_class = 'gem5::CfiMemory'
+    cxx_class = 'gem5::memory::CfiMemory'
 
     port = ResponsePort("Response port")
 

src/mem/DRAMInterface.py

@@ -49,7 +49,7 @@ class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
 class DRAMInterface(MemInterface):
     type = 'DRAMInterface'
     cxx_header = "mem/mem_interface.hh"
-    cxx_class = 'gem5::DRAMInterface'
+    cxx_class = 'gem5::memory::DRAMInterface'
 
     # scheduler page policy
     page_policy = Param.PageManage('open_adaptive', "Page management policy")

src/mem/DRAMSim2.py

@@ -40,7 +40,7 @@ from m5.objects.AbstractMemory import *
 class DRAMSim2(AbstractMemory):
     type = 'DRAMSim2'
     cxx_header = "mem/dramsim2.hh"
-    cxx_class = 'gem5::DRAMSim2'
+    cxx_class = 'gem5::memory::DRAMSim2'
 
     # A single port for now
     port = ResponsePort("This port sends responses and receives requests")

src/mem/DRAMsim3.py

@@ -40,7 +40,7 @@ from m5.objects.AbstractMemory import *
 class DRAMsim3(AbstractMemory):
     type = 'DRAMsim3'
     cxx_header = "mem/dramsim3.hh"
-    cxx_class = 'gem5::DRAMsim3'
+    cxx_class = 'gem5::memory::DRAMsim3'
 
     # A single port for now
     port = ResponsePort("port for receiving requests from"

src/mem/MemCtrl.py

@@ -53,7 +53,7 @@ class MemSched(Enum): vals = ['fcfs', 'frfcfs']
 class MemCtrl(QoSMemCtrl):
     type = 'MemCtrl'
     cxx_header = "mem/mem_ctrl.hh"
-    cxx_class = 'gem5::MemCtrl'
+    cxx_class = 'gem5::memory::MemCtrl'
 
     # single-ported on the system interface side, instantiate with a
     # bus in front of the controller for multiple ports

src/mem/MemInterface.py

@@ -55,7 +55,7 @@ class MemInterface(AbstractMemory):
     type = 'MemInterface'
     abstract = True
     cxx_header = "mem/mem_interface.hh"
-    cxx_class = 'gem5::MemInterface'
+    cxx_class = 'gem5::memory::MemInterface'
 
     # Allow the interface to set required controller buffer sizes
     # each entry corresponds to a burst for the specific memory channel

src/mem/NVMInterface.py

@@ -44,7 +44,7 @@ from m5.objects.DRAMInterface import AddrMap
 class NVMInterface(MemInterface):
     type = 'NVMInterface'
     cxx_header = "mem/mem_interface.hh"
-    cxx_class = 'gem5::NVMInterface'
+    cxx_class = 'gem5::memory::NVMInterface'
 
     # NVM DIMM could have write buffer to offload writes
     # define buffer depth, which will limit the number of pending writes

src/mem/SimpleMemory.py

@@ -42,7 +42,7 @@ from m5.objects.AbstractMemory import *
 class SimpleMemory(AbstractMemory):
     type = 'SimpleMemory'
     cxx_header = "mem/simple_mem.hh"
-    cxx_class = 'gem5::SimpleMemory'
+    cxx_class = 'gem5::memory::SimpleMemory'
 
     port = ResponsePort("This port sends responses and receives requests")
     latency = Param.Latency('30ns', "Request to response latency")

src/mem/abstract_mem.cc

@@ -54,6 +54,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 AbstractMemory::AbstractMemory(const Params &p) :
     ClockedObject(p), range(p.range), pmemAddr(NULL),
     backdoor(params().range, nullptr,
@@ -509,4 +512,5 @@ AbstractMemory::functionalAccess(PacketPtr pkt)
     }
 }
 
+} // namespace memory
 } // namespace gem5

src/mem/abstract_mem.hh

@@ -57,6 +57,9 @@ namespace gem5
 
 class System;
 
+namespace memory
+{
+
 /**
  * Locked address class that represents a physical address and a
  * context id.
@@ -348,6 +351,7 @@ class AbstractMemory : public ClockedObject
     void functionalAccess(PacketPtr pkt);
 };
 
+} // namespace memory
 } // namespace gem5
 
 #endif //__MEM_ABSTRACT_MEMORY_HH__

src/mem/cfi_mem.cc

@@ -51,6 +51,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 bool
 CfiMemory::BlockData::isLocked(Addr block_address) const
 {
@@ -732,4 +735,5 @@ CfiMemory::BlockData::erase(PacketPtr pkt)
     std::memset(host_address, 0xff, blockSize);
 }
 
+} // namespace memory
 } // namespace gem5

src/mem/cfi_mem.hh

@@ -47,6 +47,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 /**
  * CfiMemory: This is modelling a flash memory adhering to the
  * Common Flash Interface (CFI):
@@ -395,6 +398,7 @@ class CfiMemory : public AbstractMemory
     uint64_t cfiQuery(Addr addr);
 };
 
+} // namespace memory
 } // namespace gem5
 
 #endif

src/mem/dramsim2.cc

@@ -47,6 +47,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 DRAMSim2::DRAMSim2(const Params &p) :
     AbstractMemory(p),
     port(name() + ".port", *this),
@@ -392,4 +395,5 @@ DRAMSim2::MemoryPort::recvRespRetry()
     mem.recvRespRetry();
 }
 
+} // namespace memory
 } // namespace gem5

src/mem/dramsim2.hh

@@ -53,6 +53,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 class DRAMSim2 : public AbstractMemory
 {
   private:
@@ -207,6 +210,7 @@ class DRAMSim2 : public AbstractMemory
 
 };
 
+} // namespace memory
 } // namespace gem5
 
 #endif // __MEM_DRAMSIM2_HH__

src/mem/dramsim2_wrapper.cc

@@ -57,6 +57,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 /**
  * DRAMSim2 requires SHOW_SIM_OUTPUT to be defined (declared extern in
  * the DRAMSim2 print macros), otherwise we get linking errors due to
@@ -200,4 +203,5 @@ DRAMSim2Wrapper::tick()
     dramsim->update();
 }
 
+} // namespace memory
 } // namespace gem5

src/mem/dramsim2_wrapper.hh

@@ -59,6 +59,9 @@ class MultiChannelMemorySystem;
 namespace gem5
 {
 
+namespace memory
+{
+
 /**
  * Wrapper class to avoid having DRAMSim2 names like ClockDomain etc
  * clashing with the normal gem5 world. Many of the DRAMSim2 headers
@@ -161,6 +164,7 @@ class DRAMSim2Wrapper
     void tick();
 };
 
+} // namespace memory
 } // namespace gem5
 
 #endif //__MEM_DRAMSIM2_WRAPPER_HH__

src/mem/dramsim3.cc

@@ -46,6 +46,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 DRAMsim3::DRAMsim3(const Params &p) :
     AbstractMemory(p),
     port(name() + ".port", *this),
@@ -390,4 +393,5 @@ DRAMsim3::MemoryPort::recvRespRetry()
     mem.recvRespRetry();
 }
 
+} // namespace memory
 } // namespace gem5

src/mem/dramsim3.hh

@@ -55,6 +55,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 class DRAMsim3 : public AbstractMemory
 {
   private:
@@ -218,6 +221,7 @@ class DRAMsim3 : public AbstractMemory
 
 };
 
+} // namespace memory
 } // namespace gem5
 
 #endif // __MEM_DRAMSIM3_HH__

src/mem/dramsim3_wrapper.cc

@@ -58,6 +58,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 DRAMsim3Wrapper::DRAMsim3Wrapper(const std::string& config_file,
                                  const std::string& working_dir,
                                  std::function<void(uint64_t)> read_cb,
@@ -154,4 +157,5 @@ DRAMsim3Wrapper::tick()
     dramsim->ClockTick();
 }
 
+} // namespace memory
 } // namespace gem5

src/mem/dramsim3_wrapper.hh

@@ -59,6 +59,9 @@ class MemorySystem;
 namespace gem5
 {
 
+namespace memory
+{
+
 /**
  * Wrapper class to avoid having DRAMsim3 names like ClockDomain etc
  * clashing with the normal gem5 world. Many of the DRAMsim3 headers
@@ -160,6 +163,7 @@ class DRAMsim3Wrapper
     void tick();
 };
 
+} // namespace memory
 } // namespace gem5
 
 #endif //__MEM_DRAMSIM3_WRAPPER_HH__

src/mem/mem_ctrl.cc

@@ -52,8 +52,11 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 MemCtrl::MemCtrl(const MemCtrlParams &p) :
-    memory::qos::MemCtrl(p),
+    qos::MemCtrl(p),
     port(name() + ".port", *this), isTimingMode(false),
     retryRdReq(false), retryWrReq(false),
     nextReqEvent([this]{ processNextReqEvent(); }, name()),
@@ -1396,7 +1399,7 @@ Port &
 MemCtrl::getPort(const std::string &if_name, PortID idx)
 {
     if (if_name != "port") {
-        return memory::qos::MemCtrl::getPort(if_name, idx);
+        return qos::MemCtrl::getPort(if_name, idx);
     } else {
         return port;
     }
@@ -1514,4 +1517,5 @@ MemCtrl::MemoryPort::recvTimingReq(PacketPtr pkt)
     return ctrl.recvTimingReq(pkt);
 }
 
+} // namespace memory
 } // namespace gem5

src/mem/mem_ctrl.hh

@@ -63,6 +63,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 class DRAMInterface;
 class NVMInterface;
 
@@ -236,7 +239,7 @@ typedef std::deque<MemPacket*> MemPacketQueue;
  * please cite the paper.
  *
  */
-class MemCtrl : public memory::qos::MemCtrl
+class MemCtrl : public qos::MemCtrl
 {
   private:
 
@@ -712,6 +715,7 @@ class MemCtrl : public memory::qos::MemCtrl
 
 };
 
+} // namespace memory
 } // namespace gem5
 
 #endif //__MEM_CTRL_HH__

src/mem/mem_interface.cc

@@ -54,6 +54,9 @@ namespace gem5
 
 using namespace Data;
 
+namespace memory
+{
+
 MemInterface::MemInterface(const MemInterfaceParams &_p)
     : AbstractMemory(_p),
       addrMapping(_p.addr_mapping),
@@ -2624,4 +2627,5 @@ NVMInterface::NVMStats::regStats()
     busUtilWrite = avgWrBW / peakBW * 100;
 }
 
+} // namespace memory
 } // namespace gem5

src/mem/mem_interface.hh

@@ -67,6 +67,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 /**
  * General interface to memory device
  * Includes functions and parameters shared across media types
@@ -1263,6 +1266,7 @@ class NVMInterface : public MemInterface
     NVMInterface(const NVMInterfaceParams &_p);
 };
 
+} // namespace memory
 } // namespace gem5
 
 #endif //__MEM_INTERFACE_HH__

src/mem/physical.cc

@@ -71,6 +71,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 PhysicalMemory::PhysicalMemory(const std::string& _name,
                                const std::vector<AbstractMemory*>& _memories,
                                bool mmap_using_noreserve,
@@ -471,4 +474,5 @@ PhysicalMemory::unserializeStore(CheckpointIn &cp)
               filename);
 }
 
+} // namespace memory
 } // namespace gem5

src/mem/physical.hh

@@ -50,6 +50,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 /**
  * Forward declaration to avoid header dependencies.
  */
@@ -277,6 +280,7 @@ class PhysicalMemory : public Serializable
 
 };
 
+} // namespace memory
 } // namespace gem5
 
 #endif //__MEM_PHYSICAL_HH__

src/mem/ruby/system/RubySystem.hh

@@ -49,6 +49,11 @@
 namespace gem5
 {
 
+namespace memory
+{
+class SimpleMemory;
+} // namespace memory
+
 namespace ruby
 {
 
@@ -70,7 +75,7 @@ class RubySystem : public ClockedObject
     static bool getWarmupEnabled() { return m_warmup_enabled; }
     static bool getCooldownEnabled() { return m_cooldown_enabled; }
 
-    SimpleMemory *getPhysMem() { return m_phys_mem; }
+    memory::SimpleMemory *getPhysMem() { return m_phys_mem; }
     Cycles getStartCycle() { return m_start_cycle; }
     bool getAccessBackingStore() { return m_access_backing_store; }
 
@@ -137,7 +142,7 @@ class RubySystem : public ClockedObject
     static bool m_warmup_enabled;
     static unsigned m_systems_to_warmup;
     static bool m_cooldown_enabled;
-    SimpleMemory *m_phys_mem;
+    memory::SimpleMemory *m_phys_mem;
     const bool m_access_backing_store;
 
     //std::vector<Network *> m_networks;

src/mem/simple_mem.cc

@@ -47,6 +47,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 SimpleMemory::SimpleMemory(const SimpleMemoryParams &p) :
     AbstractMemory(p),
     port(name() + ".port", *this), latency(p.latency),
@@ -303,4 +306,5 @@ SimpleMemory::MemoryPort::recvRespRetry()
     mem.recvRespRetry();
 }
 
+} // namespace memory
 } // namespace gem5

src/mem/simple_mem.hh

@@ -55,6 +55,9 @@
 namespace gem5
 {
 
+namespace memory
+{
+
 /**
  * The simple memory is a basic single-ported memory controller with
  * a configurable throughput and latency.
@@ -192,6 +195,7 @@ class SimpleMemory : public AbstractMemory
     void recvRespRetry();
 };
 
+} // namespace memory
 } // namespace gem5
 
 #endif //__MEM_SIMPLE_MEMORY_HH__

src/sim/system.cc

@@ -379,7 +379,8 @@ System::isMemAddr(Addr addr) const
 }
 
 void
-System::addDeviceMemory(RequestorID requestor_id, AbstractMemory *deviceMemory)
+System::addDeviceMemory(RequestorID requestor_id,
+    memory::AbstractMemory *deviceMemory)
 {
     deviceMemMap[requestor_id].push_back(deviceMemory);
 }
@@ -394,7 +395,7 @@ System::isDeviceMemAddr(const PacketPtr& pkt) const
     return (getDeviceMemory(pkt) != nullptr);
 }
 
-AbstractMemory *
+memory::AbstractMemory *
 System::getDeviceMemory(const PacketPtr& pkt) const
 {
     const RequestorID& rid = pkt->requestorId();

src/sim/system.hh

@@ -111,7 +111,7 @@ class System : public SimObject, public PCEventScope
     SystemPort _systemPort;
 
     // Map of memory address ranges for devices with their own backing stores
-    std::unordered_map<RequestorID, std::vector<AbstractMemory *>>
+    std::unordered_map<RequestorID, std::vector<memory::AbstractMemory *>>
         deviceMemMap;
 
   public:
@@ -345,7 +345,7 @@ class System : public SimObject, public PCEventScope
     bool validKvmEnvironment() const;
 
     /** Get a pointer to access the physical memory of the system */
-    PhysicalMemory& getPhysMem() { return physmem; }
+    memory::PhysicalMemory& getPhysMem() { return physmem; }
 
     /** Amount of physical memory that is still free */
     Addr freeMemSize(int poolID = 0) const;
@@ -368,7 +368,7 @@ class System : public SimObject, public PCEventScope
      * and range match something in the device memory map.
      */
     void addDeviceMemory(RequestorID requestorId,
-                      AbstractMemory *deviceMemory);
+        memory::AbstractMemory *deviceMemory);
 
     /**
      * Similar to isMemAddr but for devices. Checks if a physical address
@@ -380,7 +380,7 @@ class System : public SimObject, public PCEventScope
     /**
      * Return a pointer to the device memory.
      */
-    AbstractMemory *getDeviceMemory(const PacketPtr& pkt) const;
+    memory::AbstractMemory *getDeviceMemory(const PacketPtr& pkt) const;
 
     /*
      * Return the list of address ranges backed by a shadowed ROM.
@@ -422,7 +422,7 @@ class System : public SimObject, public PCEventScope
 
     KvmVM *const kvmVM = nullptr;
 
-    PhysicalMemory physmem;
+    memory::PhysicalMemory physmem;
 
     AddrRangeList ShadowRomRanges;