mem: Rename "memory" variables as "mem"

Pave the way to a "memory" namespace by renaming all
the variables that have a naming conflict.

Change-Id: I8327256ed88f1791225fe158f023132850303472
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45438
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/semihosting.cc

@@ -553,9 +553,9 @@ ArmSemihosting::gatherHeapInfo(ThreadContext *tc, bool aarch64,
     fatal_if(memories.size() < 1, "No memories reported from System");
     warn_if(memories.size() > 1, "Multiple physical memory ranges available. "
             "Using first range heap/stack.");
-    const AddrRange memory = *memories.begin();
-    const Addr mem_start = memory.start() + memReserve;
-    Addr mem_end = memory.end();
+    const AddrRange mem = *memories.begin();
+    const Addr mem_start = mem.start() + memReserve;
+    Addr mem_end = mem.end();
 
     // Make sure that 32-bit guests can access their memory.
     if (!aarch64) {

src/mem/cfi_mem.cc

@@ -447,46 +447,46 @@ CfiMemory::unserialize(CheckpointIn &cp)
 
 CfiMemory::MemoryPort::MemoryPort(const std::string& _name,
                                      CfiMemory& _memory)
-    : ResponsePort(_name, &_memory), memory(_memory)
+    : ResponsePort(_name, &_memory), mem(_memory)
 { }
 
 AddrRangeList
 CfiMemory::MemoryPort::getAddrRanges() const
 {
     AddrRangeList ranges;
-    ranges.push_back(memory.getAddrRange());
+    ranges.push_back(mem.getAddrRange());
     return ranges;
 }
 
 Tick
 CfiMemory::MemoryPort::recvAtomic(PacketPtr pkt)
 {
-    return memory.recvAtomic(pkt);
+    return mem.recvAtomic(pkt);
 }
 
 Tick
 CfiMemory::MemoryPort::recvAtomicBackdoor(
         PacketPtr pkt, MemBackdoorPtr &_backdoor)
 {
-    return memory.recvAtomicBackdoor(pkt, _backdoor);
+    return mem.recvAtomicBackdoor(pkt, _backdoor);
 }
 
 void
 CfiMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 {
-    memory.recvFunctional(pkt);
+    mem.recvFunctional(pkt);
 }
 
 bool
 CfiMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
 {
-    return memory.recvTimingReq(pkt);
+    return mem.recvTimingReq(pkt);
 }
 
 void
 CfiMemory::MemoryPort::recvRespRetry()
 {
-    memory.recvRespRetry();
+    mem.recvRespRetry();
 }
 
 void

src/mem/cfi_mem.hh

@@ -232,7 +232,7 @@ class CfiMemory : public AbstractMemory
     class MemoryPort : public ResponsePort
     {
       private:
-        CfiMemory& memory;
+        CfiMemory& mem;
 
       public:
         MemoryPort(const std::string& _name, CfiMemory& _memory);

src/mem/dramsim2.cc

@@ -353,38 +353,38 @@ DRAMSim2::drain()
 
 DRAMSim2::MemoryPort::MemoryPort(const std::string& _name,
                                  DRAMSim2& _memory)
-    : ResponsePort(_name, &_memory), memory(_memory)
+    : ResponsePort(_name, &_memory), mem(_memory)
 { }
 
 AddrRangeList
 DRAMSim2::MemoryPort::getAddrRanges() const
 {
     AddrRangeList ranges;
-    ranges.push_back(memory.getAddrRange());
+    ranges.push_back(mem.getAddrRange());
     return ranges;
 }
 
 Tick
 DRAMSim2::MemoryPort::recvAtomic(PacketPtr pkt)
 {
-    return memory.recvAtomic(pkt);
+    return mem.recvAtomic(pkt);
 }
 
 void
 DRAMSim2::MemoryPort::recvFunctional(PacketPtr pkt)
 {
-    memory.recvFunctional(pkt);
+    mem.recvFunctional(pkt);
 }
 
 bool
 DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt)
 {
     // pass it to the memory controller
-    return memory.recvTimingReq(pkt);
+    return mem.recvTimingReq(pkt);
 }
 
 void
 DRAMSim2::MemoryPort::recvRespRetry()
 {
-    memory.recvRespRetry();
+    mem.recvRespRetry();
 }

src/mem/dramsim2.hh

@@ -64,7 +64,7 @@ class DRAMSim2 : public AbstractMemory
 
       private:
 
-        DRAMSim2& memory;
+        DRAMSim2& mem;
 
       public:
 

src/mem/dramsim3.cc

@@ -351,38 +351,38 @@ DRAMsim3::drain()
 
 DRAMsim3::MemoryPort::MemoryPort(const std::string& _name,
                                  DRAMsim3& _memory)
-    : ResponsePort(_name, &_memory), memory(_memory)
+    : ResponsePort(_name, &_memory), mem(_memory)
 { }
 
 AddrRangeList
 DRAMsim3::MemoryPort::getAddrRanges() const
 {
     AddrRangeList ranges;
-    ranges.push_back(memory.getAddrRange());
+    ranges.push_back(mem.getAddrRange());
     return ranges;
 }
 
 Tick
 DRAMsim3::MemoryPort::recvAtomic(PacketPtr pkt)
 {
-    return memory.recvAtomic(pkt);
+    return mem.recvAtomic(pkt);
 }
 
 void
 DRAMsim3::MemoryPort::recvFunctional(PacketPtr pkt)
 {
-    memory.recvFunctional(pkt);
+    mem.recvFunctional(pkt);
 }
 
 bool
 DRAMsim3::MemoryPort::recvTimingReq(PacketPtr pkt)
 {
     // pass it to the memory controller
-    return memory.recvTimingReq(pkt);
+    return mem.recvTimingReq(pkt);
 }
 
 void
 DRAMsim3::MemoryPort::recvRespRetry()
 {
-    memory.recvRespRetry();
+    mem.recvRespRetry();
 }

src/mem/dramsim3.hh

@@ -66,7 +66,7 @@ class DRAMsim3 : public AbstractMemory
 
       private:
 
-        DRAMsim3& memory;
+        DRAMsim3& mem;
 
       public:
 

src/mem/qos/mem_sink.cc

@@ -348,33 +348,33 @@ MemSinkCtrl::MemSinkCtrlStats::MemSinkCtrlStats(statistics::Group *parent)
 MemSinkCtrl::MemoryPort::MemoryPort(const std::string& n,
                                     MemSinkCtrl& m)
   : QueuedResponsePort(n, &m, queue, true),
-   memory(m), queue(memory, *this, true)
+   mem(m), queue(mem, *this, true)
 {}
 
 AddrRangeList
 MemSinkCtrl::MemoryPort::getAddrRanges() const
 {
     AddrRangeList ranges;
-    ranges.push_back(memory.interface->getAddrRange());
+    ranges.push_back(mem.interface->getAddrRange());
     return ranges;
 }
 
 Tick
 MemSinkCtrl::MemoryPort::recvAtomic(PacketPtr pkt)
 {
-    return memory.recvAtomic(pkt);
+    return mem.recvAtomic(pkt);
 }
 
 void
 MemSinkCtrl::MemoryPort::recvFunctional(PacketPtr pkt)
 {
-    pkt->pushLabel(memory.name());
+    pkt->pushLabel(mem.name());
 
     if (!queue.trySatisfyFunctional(pkt)) {
         // Default implementation of SimpleTimingPort::recvFunctional()
         // calls recvAtomic() and throws away the latency; we can save a
         // little here by just not calculating the latency.
-        memory.recvFunctional(pkt);
+        mem.recvFunctional(pkt);
     }
 
     pkt->popLabel();
@@ -383,7 +383,7 @@ MemSinkCtrl::MemoryPort::recvFunctional(PacketPtr pkt)
 bool
 MemSinkCtrl::MemoryPort::recvTimingReq(PacketPtr pkt)
 {
-    return memory.recvTimingReq(pkt);
+    return mem.recvTimingReq(pkt);
 }
 
 } // namespace qos

src/mem/qos/mem_sink.hh

@@ -79,7 +79,7 @@ class MemSinkCtrl : public MemCtrl
     {
       private:
         /** reference to parent memory object */
-        MemSinkCtrl& memory;
+        MemSinkCtrl& mem;
 
         /** Outgoing packet responses queue */
         RespPacketQueue queue;

src/mem/simple_mem.cc

@@ -258,44 +258,44 @@ SimpleMemory::drain()
 
 SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
                                      SimpleMemory& _memory)
-    : ResponsePort(_name, &_memory), memory(_memory)
+    : ResponsePort(_name, &_memory), mem(_memory)
 { }
 
 AddrRangeList
 SimpleMemory::MemoryPort::getAddrRanges() const
 {
     AddrRangeList ranges;
-    ranges.push_back(memory.getAddrRange());
+    ranges.push_back(mem.getAddrRange());
     return ranges;
 }
 
 Tick
 SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt)
 {
-    return memory.recvAtomic(pkt);
+    return mem.recvAtomic(pkt);
 }
 
 Tick
 SimpleMemory::MemoryPort::recvAtomicBackdoor(
         PacketPtr pkt, MemBackdoorPtr &_backdoor)
 {
-    return memory.recvAtomicBackdoor(pkt, _backdoor);
+    return mem.recvAtomicBackdoor(pkt, _backdoor);
 }
 
 void
 SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt)
 {
-    memory.recvFunctional(pkt);
+    mem.recvFunctional(pkt);
 }
 
 bool
 SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
 {
-    return memory.recvTimingReq(pkt);
+    return mem.recvTimingReq(pkt);
 }
 
 void
 SimpleMemory::MemoryPort::recvRespRetry()
 {
-    memory.recvRespRetry();
+    mem.recvRespRetry();
 }

src/mem/simple_mem.hh

@@ -82,7 +82,7 @@ class SimpleMemory : public AbstractMemory
     class MemoryPort : public ResponsePort
     {
       private:
-        SimpleMemory& memory;
+        SimpleMemory& mem;
 
       public:
         MemoryPort(const std::string& _name, SimpleMemory& _memory);

src/sim/system.cc

@@ -226,9 +226,9 @@ System::System(const Params &p)
     if (!FullSystem) {
         AddrRangeList memories = physmem.getConfAddrRanges();
         assert(!memories.empty());
-        for (const auto &memory : memories) {
-            assert(!memory.interleaved());
-            memPools.emplace_back(this, memory.start(), memory.end());
+        for (const auto &mem : memories) {
+            assert(!mem.interleaved());
+            memPools.emplace_back(this, mem.start(), mem.end());
         }
 
         /*