mem-cache: Queue,QueueEntry, NSHR::TargetList inherit from Named
With this change, when using a DPRINTF statment on a class inheriting
from the Queue or QueueEntry class, the name at the start of the log
line will be meaningful.
Currently affected classes:
MSHRqueue
MSHR
MSHR::TargetList
WriteQueue
WriteQueueEntry
Change-Id: I4e5ac080fec572961f9f1d9f88429ed6e72d8994
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47040
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
4
src/mem/cache/base.cc
vendored
4
src/mem/cache/base.cc
vendored
@@ -76,8 +76,8 @@ BaseCache::BaseCache(const BaseCacheParams &p, unsigned blk_size)
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: ClockedObject(p),
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cpuSidePort (p.name + ".cpu_side_port", this, "CpuSidePort"),
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memSidePort(p.name + ".mem_side_port", this, "MemSidePort"),
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mshrQueue("MSHRs", p.mshrs, 0, p.demand_mshr_reserve), // see below
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writeBuffer("write buffer", p.write_buffers, p.mshrs), // see below
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mshrQueue("MSHRs", p.mshrs, 0, p.demand_mshr_reserve, p.name),
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writeBuffer("write buffer", p.write_buffers, p.mshrs, p.name),
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tags(p.tags),
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compressor(p.compressor),
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prefetcher(p.prefetcher),
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19
src/mem/cache/mshr.cc
vendored
19
src/mem/cache/mshr.cc
vendored
@@ -57,16 +57,21 @@
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#include "mem/request.hh"
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#include "sim/core.hh"
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MSHR::MSHR() : downstreamPending(false),
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pendingModified(false),
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postInvalidate(false), postDowngrade(false),
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wasWholeLineWrite(false), isForward(false)
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MSHR::MSHR(const std::string &name)
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: QueueEntry(name),
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downstreamPending(false),
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pendingModified(false),
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postInvalidate(false), postDowngrade(false),
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wasWholeLineWrite(false), isForward(false),
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targets(name + ".targets"),
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deferredTargets(name + ".deferredTargets")
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{
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}
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MSHR::TargetList::TargetList()
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: needsWritable(false), hasUpgrade(false), allocOnFill(false),
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hasFromCache(false)
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MSHR::TargetList::TargetList(const std::string &name)
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: Named(name),
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needsWritable(false), hasUpgrade(false),
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allocOnFill(false), hasFromCache(false)
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{}
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6
src/mem/cache/mshr.hh
vendored
6
src/mem/cache/mshr.hh
vendored
@@ -161,7 +161,7 @@ class MSHR : public QueueEntry, public Printable
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{}
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};
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class TargetList : public std::list<Target>
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class TargetList : public std::list<Target>, public Named
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{
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public:
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@@ -175,7 +175,7 @@ class MSHR : public QueueEntry, public Printable
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*/
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bool hasFromCache;
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TargetList();
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TargetList(const std::string &name = ".unnamedTargetList");
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/**
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* Use the provided packet and the source to update the
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@@ -416,7 +416,7 @@ class MSHR : public QueueEntry, public Printable
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bool handleSnoop(PacketPtr target, Counter order);
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/** A simple constructor. */
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MSHR();
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MSHR(const std::string &name);
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/**
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* Returns the current number of allocated targets.
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5
src/mem/cache/mshr_queue.cc
vendored
5
src/mem/cache/mshr_queue.cc
vendored
@@ -49,8 +49,9 @@
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#include "mem/cache/mshr.hh"
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MSHRQueue::MSHRQueue(const std::string &_label,
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int num_entries, int reserve, int demand_reserve)
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: Queue<MSHR>(_label, num_entries, reserve),
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int num_entries, int reserve,
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int demand_reserve, std::string cache_name = "")
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: Queue<MSHR>(_label, num_entries, reserve, cache_name + ".mshr_queue"),
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demandReserve(demand_reserve)
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{}
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2
src/mem/cache/mshr_queue.hh
vendored
2
src/mem/cache/mshr_queue.hh
vendored
@@ -76,7 +76,7 @@ class MSHRQueue : public Queue<MSHR>
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* demand accesses.
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*/
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MSHRQueue(const std::string &_label, int num_entries, int reserve,
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int demand_reserve);
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int demand_reserve, std::string cache_name);
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/**
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* Allocates a new MSHR for the request and size. This places the request
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11
src/mem/cache/queue.hh
vendored
11
src/mem/cache/queue.hh
vendored
@@ -50,6 +50,7 @@
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#include <type_traits>
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#include "base/logging.hh"
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#include "base/named.hh"
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#include "base/trace.hh"
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#include "base/types.hh"
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#include "debug/Drain.hh"
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@@ -63,7 +64,7 @@
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* the write buffer.
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*/
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template<class Entry>
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class Queue : public Drainable
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class Queue : public Drainable, public Named
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{
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static_assert(std::is_base_of<QueueEntry, Entry>::value,
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"Entry must be derived from QueueEntry");
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@@ -126,10 +127,12 @@ class Queue : public Drainable
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* @param num_entries The number of entries in this queue.
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* @param reserve The extra overflow entries needed.
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*/
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Queue(const std::string &_label, int num_entries, int reserve) :
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Queue(const std::string &_label, int num_entries, int reserve,
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const std::string &name) :
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Named(name),
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label(_label), numEntries(num_entries + reserve),
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numReserve(reserve), entries(numEntries), _numInService(0),
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allocated(0)
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numReserve(reserve), entries(numEntries, name + ".entry"),
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_numInService(0), allocated(0)
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{
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for (int i = 0; i < numEntries; ++i) {
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freeList.push_back(&entries[i]);
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8
src/mem/cache/queue_entry.hh
vendored
8
src/mem/cache/queue_entry.hh
vendored
@@ -46,6 +46,7 @@
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#ifndef __MEM_CACHE_QUEUE_ENTRY_HH__
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#define __MEM_CACHE_QUEUE_ENTRY_HH__
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#include "base/named.hh"
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#include "base/types.hh"
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#include "mem/packet.hh"
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@@ -55,7 +56,7 @@ class BaseCache;
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* A queue entry base class, to be used by both the MSHRs and
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* write-queue entries.
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*/
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class QueueEntry : public Packet::SenderState
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class QueueEntry : public Packet::SenderState, public Named
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{
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/**
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@@ -117,8 +118,9 @@ class QueueEntry : public Packet::SenderState
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/** True if the entry targets the secure memory space. */
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bool isSecure;
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QueueEntry()
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: readyTime(0), _isUncacheable(false),
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QueueEntry(const std::string &name)
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: Named(name),
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readyTime(0), _isUncacheable(false),
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inService(false), order(0), blkAddr(0), blkSize(0), isSecure(false)
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{}
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5
src/mem/cache/write_queue.cc
vendored
5
src/mem/cache/write_queue.cc
vendored
@@ -49,8 +49,9 @@
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#include "mem/cache/write_queue_entry.hh"
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WriteQueue::WriteQueue(const std::string &_label,
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int num_entries, int reserve)
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: Queue<WriteQueueEntry>(_label, num_entries, reserve)
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int num_entries, int reserve, const std::string &name)
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: Queue<WriteQueueEntry>(_label, num_entries, reserve,
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name + ".write_queue")
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{}
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WriteQueueEntry *
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3
src/mem/cache/write_queue.hh
vendored
3
src/mem/cache/write_queue.hh
vendored
@@ -65,7 +65,8 @@ class WriteQueue : public Queue<WriteQueueEntry>
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* @param reserve The maximum number of entries needed to satisfy
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* any access.
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*/
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WriteQueue(const std::string &_label, int num_entries, int reserve);
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WriteQueue(const std::string &_label, int num_entries, int reserve,
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const std::string &name);
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/**
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* Allocates a new WriteQueueEntry for the request and size. This
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4
src/mem/cache/write_queue_entry.hh
vendored
4
src/mem/cache/write_queue_entry.hh
vendored
@@ -112,7 +112,9 @@ class WriteQueueEntry : public QueueEntry, public Printable
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public:
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/** A simple constructor. */
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WriteQueueEntry() {}
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WriteQueueEntry(const std::string &name)
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: QueueEntry(name)
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{}
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/**
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* Allocate a miss to this entry.
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