diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 928c30b2b1..48731cf7e8 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -76,8 +76,8 @@ BaseCache::BaseCache(const BaseCacheParams &p, unsigned blk_size)
     : ClockedObject(p),
       cpuSidePort (p.name + ".cpu_side_port", this, "CpuSidePort"),
       memSidePort(p.name + ".mem_side_port", this, "MemSidePort"),
-      mshrQueue("MSHRs", p.mshrs, 0, p.demand_mshr_reserve), // see below
-      writeBuffer("write buffer", p.write_buffers, p.mshrs), // see below
+      mshrQueue("MSHRs", p.mshrs, 0, p.demand_mshr_reserve, p.name),
+      writeBuffer("write buffer", p.write_buffers, p.mshrs, p.name),
       tags(p.tags),
       compressor(p.compressor),
       prefetcher(p.prefetcher),
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index bb4e8dfdba..2927d053f9 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -57,16 +57,21 @@
 #include "mem/request.hh"
 #include "sim/core.hh"
 
-MSHR::MSHR() : downstreamPending(false),
-               pendingModified(false),
-               postInvalidate(false), postDowngrade(false),
-               wasWholeLineWrite(false), isForward(false)
+MSHR::MSHR(const std::string &name)
+    :   QueueEntry(name),
+        downstreamPending(false),
+        pendingModified(false),
+        postInvalidate(false), postDowngrade(false),
+        wasWholeLineWrite(false), isForward(false),
+        targets(name + ".targets"),
+        deferredTargets(name + ".deferredTargets")
 {
 }
 
-MSHR::TargetList::TargetList()
-    : needsWritable(false), hasUpgrade(false), allocOnFill(false),
-      hasFromCache(false)
+MSHR::TargetList::TargetList(const std::string &name)
+    :   Named(name),
+        needsWritable(false), hasUpgrade(false),
+        allocOnFill(false), hasFromCache(false)
 {}
 
 
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index 306b5ac1d9..b23ed28056 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -161,7 +161,7 @@ class MSHR : public QueueEntry, public Printable
         {}
     };
 
-    class TargetList : public std::list<Target>
+    class TargetList : public std::list<Target>, public Named
     {
 
       public:
@@ -175,7 +175,7 @@ class MSHR : public QueueEntry, public Printable
          */
         bool hasFromCache;
 
-        TargetList();
+        TargetList(const std::string &name = ".unnamedTargetList");
 
         /**
          * Use the provided packet and the source to update the
@@ -416,7 +416,7 @@ class MSHR : public QueueEntry, public Printable
     bool handleSnoop(PacketPtr target, Counter order);
 
     /** A simple constructor. */
-    MSHR();
+    MSHR(const std::string &name);
 
     /**
      * Returns the current number of allocated targets.
diff --git a/src/mem/cache/mshr_queue.cc b/src/mem/cache/mshr_queue.cc
index 016c3f4db3..cea32fdf4c 100644
--- a/src/mem/cache/mshr_queue.cc
+++ b/src/mem/cache/mshr_queue.cc
@@ -49,8 +49,9 @@
 #include "mem/cache/mshr.hh"
 
 MSHRQueue::MSHRQueue(const std::string &_label,
-                     int num_entries, int reserve, int demand_reserve)
-    : Queue<MSHR>(_label, num_entries, reserve),
+                     int num_entries, int reserve,
+                     int demand_reserve, std::string cache_name = "")
+    : Queue<MSHR>(_label, num_entries, reserve, cache_name + ".mshr_queue"),
       demandReserve(demand_reserve)
 {}
 
diff --git a/src/mem/cache/mshr_queue.hh b/src/mem/cache/mshr_queue.hh
index 7a34db1d51..98147fab7a 100644
--- a/src/mem/cache/mshr_queue.hh
+++ b/src/mem/cache/mshr_queue.hh
@@ -76,7 +76,7 @@ class MSHRQueue : public Queue<MSHR>
      * demand accesses.
      */
     MSHRQueue(const std::string &_label, int num_entries, int reserve,
-              int demand_reserve);
+              int demand_reserve, std::string cache_name);
 
     /**
      * Allocates a new MSHR for the request and size. This places the request
diff --git a/src/mem/cache/queue.hh b/src/mem/cache/queue.hh
index 8ab0cbb094..81999a7384 100644
--- a/src/mem/cache/queue.hh
+++ b/src/mem/cache/queue.hh
@@ -50,6 +50,7 @@
 #include <type_traits>
 
 #include "base/logging.hh"
+#include "base/named.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "debug/Drain.hh"
@@ -63,7 +64,7 @@
  * the write buffer.
  */
 template<class Entry>
-class Queue : public Drainable
+class Queue : public Drainable, public Named
 {
     static_assert(std::is_base_of<QueueEntry, Entry>::value,
         "Entry must be derived from QueueEntry");
@@ -126,10 +127,12 @@ class Queue : public Drainable
      * @param num_entries The number of entries in this queue.
      * @param reserve The extra overflow entries needed.
      */
-    Queue(const std::string &_label, int num_entries, int reserve) :
+    Queue(const std::string &_label, int num_entries, int reserve,
+            const std::string &name) :
+        Named(name),
         label(_label), numEntries(num_entries + reserve),
-        numReserve(reserve), entries(numEntries), _numInService(0),
-        allocated(0)
+        numReserve(reserve), entries(numEntries, name + ".entry"),
+        _numInService(0), allocated(0)
     {
         for (int i = 0; i < numEntries; ++i) {
             freeList.push_back(&entries[i]);
diff --git a/src/mem/cache/queue_entry.hh b/src/mem/cache/queue_entry.hh
index 48d17c7b8b..9e528da2f7 100644
--- a/src/mem/cache/queue_entry.hh
+++ b/src/mem/cache/queue_entry.hh
@@ -46,6 +46,7 @@
 #ifndef __MEM_CACHE_QUEUE_ENTRY_HH__
 #define __MEM_CACHE_QUEUE_ENTRY_HH__
 
+#include "base/named.hh"
 #include "base/types.hh"
 #include "mem/packet.hh"
 
@@ -55,7 +56,7 @@ class BaseCache;
  * A queue entry base class, to be used by both the MSHRs and
  * write-queue entries.
  */
-class QueueEntry : public Packet::SenderState
+class QueueEntry : public Packet::SenderState, public Named
 {
 
     /**
@@ -117,8 +118,9 @@ class QueueEntry : public Packet::SenderState
     /** True if the entry targets the secure memory space. */
     bool isSecure;
 
-    QueueEntry()
-        : readyTime(0), _isUncacheable(false),
+    QueueEntry(const std::string &name)
+        : Named(name),
+          readyTime(0), _isUncacheable(false),
           inService(false), order(0), blkAddr(0), blkSize(0), isSecure(false)
     {}
 
diff --git a/src/mem/cache/write_queue.cc b/src/mem/cache/write_queue.cc
index 2e3cc93406..fd5525715b 100644
--- a/src/mem/cache/write_queue.cc
+++ b/src/mem/cache/write_queue.cc
@@ -49,8 +49,9 @@
 #include "mem/cache/write_queue_entry.hh"
 
 WriteQueue::WriteQueue(const std::string &_label,
-                       int num_entries, int reserve)
-    : Queue<WriteQueueEntry>(_label, num_entries, reserve)
+                       int num_entries, int reserve, const std::string &name)
+    : Queue<WriteQueueEntry>(_label, num_entries, reserve,
+            name + ".write_queue")
 {}
 
 WriteQueueEntry *
diff --git a/src/mem/cache/write_queue.hh b/src/mem/cache/write_queue.hh
index a072468df2..2705232993 100644
--- a/src/mem/cache/write_queue.hh
+++ b/src/mem/cache/write_queue.hh
@@ -65,7 +65,8 @@ class WriteQueue : public Queue<WriteQueueEntry>
      * @param reserve The maximum number of entries needed to satisfy
      *        any access.
      */
-    WriteQueue(const std::string &_label, int num_entries, int reserve);
+    WriteQueue(const std::string &_label, int num_entries, int reserve,
+            const std::string &name);
 
     /**
      * Allocates a new WriteQueueEntry for the request and size. This
diff --git a/src/mem/cache/write_queue_entry.hh b/src/mem/cache/write_queue_entry.hh
index d50de353e8..cfb4a11bc7 100644
--- a/src/mem/cache/write_queue_entry.hh
+++ b/src/mem/cache/write_queue_entry.hh
@@ -112,7 +112,9 @@ class WriteQueueEntry : public QueueEntry, public Printable
   public:
 
     /** A simple constructor. */
-    WriteQueueEntry() {}
+    WriteQueueEntry(const std::string &name)
+        :   QueueEntry(name)
+    {}
 
     /**
      * Allocate a miss to this entry.