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base: Rename Loader namespace as loader

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As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Loader became ::loader.

Change-Id: Ifddf11ab4d5d7358032fbc523bc923c0a9feedbd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45424
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Daniel R. Carvalho
2021-05-06 20:19:18 -03:00
committed by Daniel Carvalho
parent a658ea043f
commit 9f55bb8478
176 changed files with 804 additions and 774 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/arm/freebsd/fs_workload.cc
View File

@@ -81,7 +81,7 @@ FsFreebsd::initState()
if (params().early_kernel_symbols) {
auto phys_globals = kernelObj->symtab().globals()->mask(_loadAddrMask);
kernelSymtab.insert(*phys_globals);
Loader::debugSymbolTable.insert(*phys_globals);
loader::debugSymbolTable.insert(*phys_globals);
}
// Check if the kernel image has a symbol that tells us it supports
@@ -95,7 +95,7 @@ FsFreebsd::initState()
inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
params().dtb_addr);
auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);
auto *dtb_file = new loader::DtbFile(params().dtb_filename);
warn_if(!dtb_file->addBootCmdLine(commandLine.c_str(), commandLine.size()),
"Couldn't append bootargs to DTB file: %s",

10
src/arch/arm/freebsd/se_workload.cc
View File

@@ -51,20 +51,20 @@ class FreebsdLoader : public Process::Loader
{
public:
Process *
load(const ProcessParams &params, ::Loader::ObjectFile *obj) override
load(const ProcessParams &params, loader::ObjectFile *obj) override
{
auto arch = obj->getArch();
auto opsys = obj->getOpSys();
if (arch != ::Loader::Arm && arch != ::Loader::Thumb &&
arch != ::Loader::Arm64) {
if (arch != loader::Arm && arch != loader::Thumb &&
arch != loader::Arm64) {
return nullptr;
}
if (opsys != ::Loader::FreeBSD)
if (opsys != loader::FreeBSD)
return nullptr;
if (arch == ::Loader::Arm64)
if (arch == loader::Arm64)
return new ArmProcess64(params, obj, arch);
else
return new ArmProcess32(params, obj, arch);

12
src/arch/arm/fs_workload.cc
View File

@@ -78,8 +78,8 @@ FsWorkload::FsWorkload(const Params &p) : KernelWorkload(p)
bootLoaders.reserve(p.boot_loader.size());
for (const auto &bl : p.boot_loader) {
std::unique_ptr<Loader::ObjectFile> bl_obj;
bl_obj.reset(Loader::createObjectFile(bl));
std::unique_ptr<loader::ObjectFile> bl_obj;
bl_obj.reset(loader::createObjectFile(bl));
fatal_if(!bl_obj, "Could not read bootloader: %s", bl);
bootLoaders.emplace_back(std::move(bl_obj));
@@ -91,7 +91,7 @@ FsWorkload::FsWorkload(const Params &p) : KernelWorkload(p)
"Can't find a matching boot loader / kernel combination!");
if (bootldr)
Loader::debugSymbolTable.insert(*bootldr->symtab().globals());
loader::debugSymbolTable.insert(*bootldr->symtab().globals());
}
void
@@ -130,7 +130,7 @@ FsWorkload::initState()
tc->setIntReg(3, kernelEntry);
if (is_gic_v2)
tc->setIntReg(4, arm_sys->params().gic_cpu_addr);
if (getArch() == Loader::Arm)
if (getArch() == loader::Arm)
tc->setIntReg(5, params().cpu_release_addr);
}
inform("Using kernel entry physical address at %#x\n", kernelEntry);
@@ -141,8 +141,8 @@ FsWorkload::initState()
}
}
Loader::ObjectFile *
FsWorkload::getBootLoader(Loader::ObjectFile *const obj)
loader::ObjectFile *
FsWorkload::getBootLoader(loader::ObjectFile *const obj)
{
if (obj) {
for (auto &bl : bootLoaders) {

14
src/arch/arm/fs_workload.hh
View File

@@ -66,12 +66,12 @@ class FsWorkload : public KernelWorkload
{
protected:
/** Bootloaders */
std::vector<std::unique_ptr<Loader::ObjectFile>> bootLoaders;
std::vector<std::unique_ptr<loader::ObjectFile>> bootLoaders;
/**
* Pointer to the bootloader object
*/
Loader::ObjectFile *bootldr = nullptr;
loader::ObjectFile *bootldr = nullptr;
/**
* This differs from entry since it takes into account where
@@ -87,14 +87,14 @@ class FsWorkload : public KernelWorkload
* @return Pointer to boot loader ObjectFile or nullptr if there
* is no matching boot loader.
*/
Loader::ObjectFile *getBootLoader(Loader::ObjectFile *const obj);
loader::ObjectFile *getBootLoader(loader::ObjectFile *const obj);
template <template <class ABI, class Base> class FuncEvent,
typename... Args>
PCEvent *
addSkipFunc(Args... args)
{
if (getArch() == Loader::Arm64) {
if (getArch() == loader::Arm64) {
return addKernelFuncEvent<FuncEvent<Aapcs64, SkipFunc>>(
std::forward<Args>(args)...);
} else {
@@ -108,7 +108,7 @@ class FsWorkload : public KernelWorkload
PCEvent *
addSkipFuncOrPanic(Args... args)
{
if (getArch() == Loader::Arm64) {
if (getArch() == loader::Arm64) {
return addKernelFuncEventOrPanic<FuncEvent<Aapcs64, SkipFunc>>(
std::forward<Args>(args)...);
} else {
@@ -129,7 +129,7 @@ class FsWorkload : public KernelWorkload
return kernelEntry;
}
Loader::Arch
loader::Arch
getArch() const override
{
if (bootldr)
@@ -137,7 +137,7 @@ class FsWorkload : public KernelWorkload
else if (kernelObj)
return kernelObj->getArch();
else
return Loader::Arm64;
return loader::Arm64;
}
FsWorkload(const Params &p);

6
src/arch/arm/insts/branch.cc
View File

@@ -43,7 +43,7 @@ namespace ArmISA {
std::string
BranchReg::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -53,7 +53,7 @@ BranchReg::generateDisassembly(
std::string
BranchImm::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -63,7 +63,7 @@ BranchImm::generateDisassembly(
std::string
BranchRegReg::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);

6
src/arch/arm/insts/branch.hh
View File

@@ -58,7 +58,7 @@ class BranchImm : public PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// Conditionally Branch to a target computed with an immediate
@@ -88,7 +88,7 @@ class BranchReg : public PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// Conditionally Branch to a target computed with a register
@@ -119,7 +119,7 @@ class BranchRegReg : public PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// Branch to a target computed with an immediate and a register

20
src/arch/arm/insts/branch64.cc
View File

@@ -69,7 +69,7 @@ BranchImmImmReg64::branchTarget(const ArmISA::PCState &branchPC) const
std::string
BranchImmCond64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false, true, condCode);
@@ -79,7 +79,7 @@ BranchImmCond64::generateDisassembly(
std::string
BranchImm64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -89,7 +89,7 @@ BranchImm64::generateDisassembly(
std::string
BranchReg64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -99,7 +99,7 @@ BranchReg64::generateDisassembly(
std::string
BranchRegReg64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -111,7 +111,7 @@ BranchRegReg64::generateDisassembly(
std::string
BranchRet64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -122,7 +122,7 @@ BranchRet64::generateDisassembly(
std::string
BranchRetA64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -133,7 +133,7 @@ BranchRetA64::generateDisassembly(
std::string
BranchEret64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -142,7 +142,7 @@ BranchEret64::generateDisassembly(
std::string
BranchEretA64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -151,7 +151,7 @@ BranchEretA64::generateDisassembly(
std::string
BranchImmReg64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -163,7 +163,7 @@ BranchImmReg64::generateDisassembly(
std::string
BranchImmImmReg64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);

20
src/arch/arm/insts/branch64.hh
View File

@@ -61,7 +61,7 @@ class BranchImm64 : public ArmStaticInst
using StaticInst::branchTarget;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// Conditionally Branch to a target computed with an immediate
@@ -77,7 +77,7 @@ class BranchImmCond64 : public BranchImm64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// Branch to a target computed with two registers
@@ -94,7 +94,7 @@ class BranchRegReg64 : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// Branch to a target computed with a register
@@ -110,7 +110,7 @@ class BranchReg64 : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// Ret instruction
@@ -123,7 +123,7 @@ class BranchRet64 : public BranchReg64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// RetAA/RetAB instruction
@@ -136,7 +136,7 @@ class BranchRetA64 : public BranchRegReg64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// Eret instruction
@@ -148,7 +148,7 @@ class BranchEret64 : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// EretA/B instruction
@@ -163,7 +163,7 @@ class BranchEretA64 : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// Branch to a target computed with an immediate and a register
class BranchImmReg64 : public ArmStaticInst
@@ -185,7 +185,7 @@ class BranchImmReg64 : public ArmStaticInst
using StaticInst::branchTarget;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// Branch to a target computed with two immediates
@@ -211,7 +211,7 @@ class BranchImmImmReg64 : public ArmStaticInst
using StaticInst::branchTarget;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}

26
src/arch/arm/insts/data64.cc
View File

@@ -42,7 +42,7 @@ namespace ArmISA
std::string
DataXImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
@@ -52,7 +52,7 @@ DataXImmOp::generateDisassembly(
std::string
DataXImmOnlyOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -63,7 +63,7 @@ DataXImmOnlyOp::generateDisassembly(
std::string
DataXSRegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
@@ -73,7 +73,7 @@ DataXSRegOp::generateDisassembly(
std::string
DataXERegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
@@ -83,7 +83,7 @@ DataXERegOp::generateDisassembly(
std::string
DataX1RegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -95,7 +95,7 @@ DataX1RegOp::generateDisassembly(
std::string
DataX1RegImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -108,7 +108,7 @@ DataX1RegImmOp::generateDisassembly(
std::string
DataX1Reg2ImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -121,7 +121,7 @@ DataX1Reg2ImmOp::generateDisassembly(
std::string
DataX2RegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -135,7 +135,7 @@ DataX2RegOp::generateDisassembly(
std::string
DataX2RegImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -150,7 +150,7 @@ DataX2RegImmOp::generateDisassembly(
std::string
DataX3RegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -166,7 +166,7 @@ DataX3RegOp::generateDisassembly(
std::string
DataXCondCompImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -179,7 +179,7 @@ DataXCondCompImmOp::generateDisassembly(
std::string
DataXCondCompRegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -194,7 +194,7 @@ DataXCondCompRegOp::generateDisassembly(
std::string
DataXCondSelOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);

26
src/arch/arm/insts/data64.hh
View File

@@ -57,7 +57,7 @@ class DataXImmOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataXImmOnlyOp : public ArmStaticInst
@@ -73,7 +73,7 @@ class DataXImmOnlyOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataXSRegOp : public ArmStaticInst
@@ -92,7 +92,7 @@ class DataXSRegOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataXERegOp : public ArmStaticInst
@@ -111,7 +111,7 @@ class DataXERegOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataX1RegOp : public ArmStaticInst
@@ -125,7 +125,7 @@ class DataX1RegOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataX1RegImmOp : public ArmStaticInst
@@ -141,7 +141,7 @@ class DataX1RegImmOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataX1Reg2ImmOp : public ArmStaticInst
@@ -158,7 +158,7 @@ class DataX1Reg2ImmOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataX2RegOp : public ArmStaticInst
@@ -173,7 +173,7 @@ class DataX2RegOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataX2RegImmOp : public ArmStaticInst
@@ -190,7 +190,7 @@ class DataX2RegImmOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataX3RegOp : public ArmStaticInst
@@ -206,7 +206,7 @@ class DataX3RegOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataXCondCompImmOp : public ArmStaticInst
@@ -225,7 +225,7 @@ class DataXCondCompImmOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataXCondCompRegOp : public ArmStaticInst
@@ -243,7 +243,7 @@ class DataXCondCompRegOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataXCondSelOp : public ArmStaticInst
@@ -260,7 +260,7 @@ class DataXCondSelOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}

16
src/arch/arm/insts/macromem.cc
View File

@@ -1512,7 +1512,7 @@ MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst,
std::string
MicroIntImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -1526,7 +1526,7 @@ MicroIntImmOp::generateDisassembly(
std::string
MicroIntImmXOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -1540,7 +1540,7 @@ MicroIntImmXOp::generateDisassembly(
std::string
MicroSetPCCPSR::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -1550,7 +1550,7 @@ MicroSetPCCPSR::generateDisassembly(
std::string
MicroIntRegXOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -1563,7 +1563,7 @@ MicroIntRegXOp::generateDisassembly(
std::string
MicroIntMov::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -1575,7 +1575,7 @@ MicroIntMov::generateDisassembly(
std::string
MicroIntOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -1589,7 +1589,7 @@ MicroIntOp::generateDisassembly(
std::string
MicroMemOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -1607,7 +1607,7 @@ MicroMemOp::generateDisassembly(
std::string
MicroMemPairOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);

16
src/arch/arm/insts/macromem.hh
View File

@@ -262,7 +262,7 @@ class MicroSetPCCPSR : public MicroOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -281,7 +281,7 @@ class MicroIntMov : public MicroOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -301,7 +301,7 @@ class MicroIntImmOp : public MicroOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MicroIntImmXOp : public MicroOpX
@@ -318,7 +318,7 @@ class MicroIntImmXOp : public MicroOpX
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -337,7 +337,7 @@ class MicroIntOp : public MicroOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MicroIntRegXOp : public MicroOp
@@ -357,7 +357,7 @@ class MicroIntRegXOp : public MicroOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -397,7 +397,7 @@ class MicroMemOp : public MicroIntImmOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MicroMemPairOp : public MicroOp
@@ -418,7 +418,7 @@ class MicroMemPairOp : public MicroOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**

4
src/arch/arm/insts/mem.cc
View File

@@ -74,7 +74,7 @@ MemoryReg::printOffset(std::ostream &os) const
}
std::string
RfeOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
RfeOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
switch (mode) {
@@ -99,7 +99,7 @@ RfeOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
}
std::string
SrsOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
SrsOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
switch (mode) {

10
src/arch/arm/insts/mem.hh
View File

@@ -109,7 +109,7 @@ class RfeOp : public MightBeMicro
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// The address is a base register plus an immediate.
@@ -151,7 +151,7 @@ class SrsOp : public MightBeMicro
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class Memory : public MightBeMicro
@@ -376,7 +376,7 @@ class MemoryOffset : public Base
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
this->printInst(ss, Memory::AddrMd_Offset);
@@ -427,7 +427,7 @@ class MemoryPreIndex : public Base
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
this->printInst(ss, Memory::AddrMd_PreIndex);
@@ -478,7 +478,7 @@ class MemoryPostIndex : public Base
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
this->printInst(ss, Memory::AddrMd_PostIndex);

22
src/arch/arm/insts/mem64.cc
View File

@@ -45,7 +45,7 @@ namespace ArmISA
{
std::string
SysDC64::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
SysDC64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -84,7 +84,7 @@ Memory64::setExcAcRel(bool exclusive, bool acrel)
std::string
MemoryImm64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
startDisassembly(ss);
@@ -96,7 +96,7 @@ MemoryImm64::generateDisassembly(
std::string
MemoryDImm64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -113,7 +113,7 @@ MemoryDImm64::generateDisassembly(
std::string
MemoryDImmEx64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -132,7 +132,7 @@ MemoryDImmEx64::generateDisassembly(
std::string
MemoryPreIndex64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
startDisassembly(ss);
@@ -142,7 +142,7 @@ MemoryPreIndex64::generateDisassembly(
std::string
MemoryPostIndex64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
startDisassembly(ss);
@@ -154,7 +154,7 @@ MemoryPostIndex64::generateDisassembly(
std::string
MemoryReg64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
startDisassembly(ss);
@@ -165,7 +165,7 @@ MemoryReg64::generateDisassembly(
std::string
MemoryRaw64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
startDisassembly(ss);
@@ -175,7 +175,7 @@ MemoryRaw64::generateDisassembly(
std::string
MemoryEx64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -190,7 +190,7 @@ MemoryEx64::generateDisassembly(
std::string
MemoryLiteral64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -201,7 +201,7 @@ MemoryLiteral64::generateDisassembly(
std::string
MemoryAtomicPair64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);

22
src/arch/arm/insts/mem64.hh
View File

@@ -61,7 +61,7 @@ class SysDC64 : public MiscRegOp64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MightBeMicro64 : public ArmStaticInst
@@ -143,7 +143,7 @@ class MemoryImm64 : public Memory64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MemoryDImm64 : public MemoryImm64
@@ -159,7 +159,7 @@ class MemoryDImm64 : public MemoryImm64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MemoryDImmEx64 : public MemoryDImm64
@@ -175,7 +175,7 @@ class MemoryDImmEx64 : public MemoryDImm64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MemoryPreIndex64 : public MemoryImm64
@@ -188,7 +188,7 @@ class MemoryPreIndex64 : public MemoryImm64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MemoryPostIndex64 : public MemoryImm64
@@ -201,7 +201,7 @@ class MemoryPostIndex64 : public MemoryImm64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MemoryReg64 : public Memory64
@@ -220,7 +220,7 @@ class MemoryReg64 : public Memory64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MemoryRaw64 : public Memory64
@@ -232,7 +232,7 @@ class MemoryRaw64 : public Memory64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MemoryEx64 : public Memory64
@@ -247,7 +247,7 @@ class MemoryEx64 : public Memory64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MemoryLiteral64 : public Memory64
@@ -261,7 +261,7 @@ class MemoryLiteral64 : public Memory64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MemoryAtomicPair64 : public Memory64
@@ -281,7 +281,7 @@ class MemoryAtomicPair64 : public Memory64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}

44
src/arch/arm/insts/misc.cc
View File

@@ -43,7 +43,7 @@
using namespace ArmISA;
std::string
MrsOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
MrsOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -126,7 +126,7 @@ MsrBase::printMsrBase(std::ostream &os) const
}
std::string
MsrImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
MsrImmOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMsrBase(ss);
@@ -135,7 +135,7 @@ MsrImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
}
std::string
MsrRegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
MsrRegOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMsrBase(ss);
@@ -145,7 +145,7 @@ MsrRegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
}
std::string
MrrcOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
MrrcOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -158,7 +158,7 @@ MrrcOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
}
std::string
McrrOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
McrrOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -171,7 +171,7 @@ McrrOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
}
std::string
ImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
ImmOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -180,7 +180,7 @@ ImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
}
std::string
RegImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
RegImmOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -190,7 +190,7 @@ RegImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
}
std::string
RegRegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
RegRegOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -201,7 +201,7 @@ RegRegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
}
std::string
RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
RegOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -211,7 +211,7 @@ RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
std::string
RegRegRegImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -226,7 +226,7 @@ RegRegRegImmOp::generateDisassembly(
std::string
RegRegRegRegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -242,7 +242,7 @@ RegRegRegRegOp::generateDisassembly(
std::string
RegRegRegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -256,7 +256,7 @@ RegRegRegOp::generateDisassembly(
std::string
RegRegImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -269,7 +269,7 @@ RegRegImmOp::generateDisassembly(
std::string
MiscRegRegImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -281,7 +281,7 @@ MiscRegRegImmOp::generateDisassembly(
std::string
RegMiscRegImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -293,7 +293,7 @@ RegMiscRegImmOp::generateDisassembly(
std::string
RegImmImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -304,7 +304,7 @@ RegImmImmOp::generateDisassembly(
std::string
RegRegImmImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -317,7 +317,7 @@ RegRegImmImmOp::generateDisassembly(
std::string
RegImmRegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -329,7 +329,7 @@ RegImmRegOp::generateDisassembly(
std::string
RegImmRegShiftOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -342,7 +342,7 @@ RegImmRegShiftOp::generateDisassembly(
std::string
UnknownOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (inst %#08x)", "unknown", encoding());
}
@@ -371,7 +371,7 @@ McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
std::string
McrMrcMiscInst::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (pipe flush)", mnemonic);
}
@@ -398,7 +398,7 @@ McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const
std::string
McrMrcImplDefined::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (implementation defined)", mnemonic);
}

44
src/arch/arm/insts/misc.hh
View File

@@ -51,7 +51,7 @@ class MrsOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MsrBase : public ArmISA::PredOp
@@ -78,7 +78,7 @@ class MsrImmOp : public MsrBase
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MsrRegOp : public MsrBase
@@ -92,7 +92,7 @@ class MsrRegOp : public MsrBase
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MrrcOp : public ArmISA::PredOp
@@ -111,7 +111,7 @@ class MrrcOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class McrrOp : public ArmISA::PredOp
@@ -130,7 +130,7 @@ class McrrOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class ImmOp : public ArmISA::PredOp
@@ -144,7 +144,7 @@ class ImmOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegImmOp : public ArmISA::PredOp
@@ -159,7 +159,7 @@ class RegImmOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegRegOp : public ArmISA::PredOp
@@ -175,7 +175,7 @@ class RegRegOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegOp : public ArmISA::PredOp
@@ -189,7 +189,7 @@ class RegOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegImmRegOp : public ArmISA::PredOp
@@ -207,7 +207,7 @@ class RegImmRegOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegRegRegImmOp : public ArmISA::PredOp
@@ -227,7 +227,7 @@ class RegRegRegImmOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegRegRegRegOp : public ArmISA::PredOp
@@ -247,7 +247,7 @@ class RegRegRegRegOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegRegRegOp : public ArmISA::PredOp
@@ -265,7 +265,7 @@ class RegRegRegOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegRegImmOp : public ArmISA::PredOp
@@ -283,7 +283,7 @@ class RegRegImmOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MiscRegRegImmOp : public ArmISA::PredOp
@@ -301,7 +301,7 @@ class MiscRegRegImmOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegMiscRegImmOp : public ArmISA::PredOp
@@ -319,7 +319,7 @@ class RegMiscRegImmOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegImmImmOp : public ArmISA::PredOp
@@ -337,7 +337,7 @@ class RegImmImmOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegRegImmImmOp : public ArmISA::PredOp
@@ -356,7 +356,7 @@ class RegRegImmImmOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegImmRegShiftOp : public ArmISA::PredOp
@@ -378,7 +378,7 @@ class RegImmRegShiftOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class UnknownOp : public ArmISA::PredOp
@@ -391,7 +391,7 @@ class UnknownOp : public ArmISA::PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -414,7 +414,7 @@ class McrMrcMiscInst : public ArmISA::ArmStaticInst
Trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
@@ -432,7 +432,7 @@ class McrMrcImplDefined : public McrMrcMiscInst
Trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};

18
src/arch/arm/insts/misc64.cc
View File

@@ -41,7 +41,7 @@
using namespace ArmISA;
std::string
ImmOp64::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
ImmOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -51,7 +51,7 @@ ImmOp64::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
std::string
RegRegImmImmOp64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -64,7 +64,7 @@ RegRegImmImmOp64::generateDisassembly(
std::string
RegRegRegImmOp64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -79,7 +79,7 @@ RegRegRegImmOp64::generateDisassembly(
std::string
UnknownOp64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (inst %#08x)", "unknown", encoding());
}
@@ -808,7 +808,7 @@ MiscRegImmOp64::miscRegImm() const
std::string
MiscRegImmOp64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -820,7 +820,7 @@ MiscRegImmOp64::generateDisassembly(
std::string
MiscRegRegImmOp64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -832,7 +832,7 @@ MiscRegRegImmOp64::generateDisassembly(
std::string
RegMiscRegImmOp64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -867,14 +867,14 @@ MiscRegImplDefined64::execute(ExecContext *xc,
std::string
MiscRegImplDefined64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (implementation defined)", fullMnemonic.c_str());
}
std::string
RegNone::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);

18
src/arch/arm/insts/misc64.hh
View File

@@ -51,7 +51,7 @@ class ImmOp64 : public ArmISA::ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegRegImmImmOp64 : public ArmISA::ArmStaticInst
@@ -71,7 +71,7 @@ class RegRegImmImmOp64 : public ArmISA::ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegRegRegImmOp64 : public ArmISA::ArmStaticInst
@@ -91,7 +91,7 @@ class RegRegRegImmOp64 : public ArmISA::ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class UnknownOp64 : public ArmISA::ArmStaticInst
@@ -104,7 +104,7 @@ class UnknownOp64 : public ArmISA::ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -167,7 +167,7 @@ class MiscRegImmOp64 : public MiscRegOp64
RegVal miscRegImm() const;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MiscRegRegImmOp64 : public MiscRegOp64
@@ -185,7 +185,7 @@ class MiscRegRegImmOp64 : public MiscRegOp64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegMiscRegImmOp64 : public MiscRegOp64
@@ -203,7 +203,7 @@ class RegMiscRegImmOp64 : public MiscRegOp64
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class MiscRegImplDefined64 : public MiscRegOp64
@@ -231,7 +231,7 @@ class MiscRegImplDefined64 : public MiscRegOp64
Trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class RegNone : public ArmISA::ArmStaticInst
@@ -246,7 +246,7 @@ class RegNone : public ArmISA::ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const;
Addr pc, const loader::SymbolTable *symtab) const;
};
#endif

12
src/arch/arm/insts/pred_inst.cc
View File

@@ -44,7 +44,7 @@ namespace ArmISA
{
std::string
PredIntOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
unsigned rotate = machInst.rotate * 2;
@@ -62,7 +62,7 @@ PredIntOp::generateDisassembly(
std::string
PredImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printDataInst(ss, true, machInst.opcode4 == 0, machInst.sField,
@@ -77,7 +77,7 @@ PredImmOp::generateDisassembly(
std::string
DataImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
@@ -87,7 +87,7 @@ DataImmOp::generateDisassembly(
std::string
DataRegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
@@ -97,7 +97,7 @@ DataRegOp::generateDisassembly(
std::string
DataRegRegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printDataInst(ss, false, false, /*XXX not really s*/ false, dest, op1,
@@ -107,7 +107,7 @@ DataRegRegOp::generateDisassembly(
std::string
PredMacroOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;

12
src/arch/arm/insts/pred_inst.hh
View File

@@ -251,7 +251,7 @@ class PredImmOp : public PredOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -272,7 +272,7 @@ class PredIntOp : public PredOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataImmOp : public PredOp
@@ -291,7 +291,7 @@ class DataImmOp : public PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataRegOp : public PredOp
@@ -310,7 +310,7 @@ class DataRegOp : public PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class DataRegRegOp : public PredOp
@@ -328,7 +328,7 @@ class DataRegRegOp : public PredOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -372,7 +372,7 @@ class PredMacroOp : public PredOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**

6
src/arch/arm/insts/pseudo.cc
View File

@@ -100,7 +100,7 @@ DecoderFaultInst::faultName() const
std::string
DecoderFaultInst::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("gem5fault %s", faultName());
}
@@ -135,7 +135,7 @@ FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
std::string
FailUnimplemented::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)",
fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
@@ -177,7 +177,7 @@ WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
std::string
WarnUnimplemented::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)",
fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);

6
src/arch/arm/insts/pseudo.hh
View File

@@ -57,7 +57,7 @@ class DecoderFaultInst : public ArmISA::ArmStaticInst
Trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -83,7 +83,7 @@ class FailUnimplemented : public ArmISA::ArmStaticInst
Trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -113,7 +113,7 @@ class WarnUnimplemented : public ArmISA::ArmStaticInst
Trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**

6
src/arch/arm/insts/static_inst.cc
View File

@@ -393,7 +393,7 @@ ArmStaticInst::printMnemonic(std::ostream &os,
void
ArmStaticInst::printTarget(std::ostream &os, Addr target,
const Loader::SymbolTable *symtab) const
const loader::SymbolTable *symtab) const
{
if (symtab) {
auto it = symtab->findNearest(target);
@@ -475,7 +475,7 @@ ArmStaticInst::printCondition(std::ostream &os,
void
ArmStaticInst::printMemSymbol(std::ostream &os,
const Loader::SymbolTable *symtab,
const loader::SymbolTable *symtab,
const std::string &prefix,
const Addr addr,
const std::string &suffix) const
@@ -621,7 +621,7 @@ ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
std::string
ArmStaticInst::generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const
const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);

6
src/arch/arm/insts/static_inst.hh
View File

@@ -173,10 +173,10 @@ class ArmStaticInst : public StaticInst
bool withCond64 = false,
ConditionCode cond64 = COND_UC) const;
void printTarget(std::ostream &os, Addr target,
const Loader::SymbolTable *symtab) const;
const loader::SymbolTable *symtab) const;
void printCondition(std::ostream &os, unsigned code,
bool noImplicit=false) const;
void printMemSymbol(std::ostream &os, const Loader::SymbolTable *symtab,
void printMemSymbol(std::ostream &os, const loader::SymbolTable *symtab,
const std::string &prefix, const Addr addr,
const std::string &suffix) const;
void printShiftOperand(std::ostream &os, IntRegIndex rm,
@@ -210,7 +210,7 @@ class ArmStaticInst : public StaticInst
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
static void
activateBreakpoint(ThreadContext *tc)

100
src/arch/arm/insts/sve.cc
View File

@@ -56,7 +56,7 @@ svePredTypeToStr(SvePredType pt)
std::string
SvePredCountPredOp::generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const
const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -70,7 +70,7 @@ SvePredCountPredOp::generateDisassembly(Addr pc,
std::string
SvePredCountOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -91,7 +91,7 @@ SvePredCountOp::generateDisassembly(
std::string
SveIndexIIOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -102,7 +102,7 @@ SveIndexIIOp::generateDisassembly(
std::string
SveIndexIROp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -114,7 +114,7 @@ SveIndexIROp::generateDisassembly(
std::string
SveIndexRIOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -127,7 +127,7 @@ SveIndexRIOp::generateDisassembly(
std::string
SveIndexRROp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -141,7 +141,7 @@ SveIndexRROp::generateDisassembly(
std::string
SveWhileOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -160,7 +160,7 @@ SveWhileOp::generateDisassembly(
std::string
SveCompTermOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -172,7 +172,7 @@ SveCompTermOp::generateDisassembly(
std::string
SveUnaryPredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -186,7 +186,7 @@ SveUnaryPredOp::generateDisassembly(
std::string
SveUnaryUnpredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -198,7 +198,7 @@ SveUnaryUnpredOp::generateDisassembly(
std::string
SveUnaryWideImmUnpredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -210,7 +210,7 @@ SveUnaryWideImmUnpredOp::generateDisassembly(
std::string
SveUnaryWideImmPredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -225,7 +225,7 @@ SveUnaryWideImmPredOp::generateDisassembly(
std::string
SveBinImmUnpredConstrOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -239,7 +239,7 @@ SveBinImmUnpredConstrOp::generateDisassembly(
std::string
SveBinImmPredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -255,7 +255,7 @@ SveBinImmPredOp::generateDisassembly(
std::string
SveBinWideImmUnpredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -269,7 +269,7 @@ SveBinWideImmUnpredOp::generateDisassembly(
std::string
SveBinDestrPredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -285,7 +285,7 @@ SveBinDestrPredOp::generateDisassembly(
std::string
SveBinConstrPredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -304,7 +304,7 @@ SveBinConstrPredOp::generateDisassembly(
std::string
SveBinUnpredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -318,7 +318,7 @@ SveBinUnpredOp::generateDisassembly(
std::string
SveBinIdxUnpredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -335,7 +335,7 @@ SveBinIdxUnpredOp::generateDisassembly(
std::string
SvePredLogicalOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -355,7 +355,7 @@ SvePredLogicalOp::generateDisassembly(
std::string
SvePredBinPermOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -368,7 +368,7 @@ SvePredBinPermOp::generateDisassembly(
}
std::string
SveCmpOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
SveCmpOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -384,7 +384,7 @@ SveCmpOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
std::string
SveCmpImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -400,7 +400,7 @@ SveCmpImmOp::generateDisassembly(
std::string
SveTerPredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -416,7 +416,7 @@ SveTerPredOp::generateDisassembly(
std::string
SveTerImmUnpredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -432,7 +432,7 @@ SveTerImmUnpredOp::generateDisassembly(
std::string
SveReducOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -446,7 +446,7 @@ SveReducOp::generateDisassembly(
std::string
SveOrdReducOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -462,7 +462,7 @@ SveOrdReducOp::generateDisassembly(
std::string
SvePtrueOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -476,7 +476,7 @@ SvePtrueOp::generateDisassembly(
std::string
SveIntCmpOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -496,7 +496,7 @@ SveIntCmpOp::generateDisassembly(
std::string
SveIntCmpImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -511,7 +511,7 @@ SveIntCmpImmOp::generateDisassembly(
}
std::string
SveAdrOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
SveAdrOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -536,7 +536,7 @@ SveAdrOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
std::string
SveElemCountOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
static const char suffix[9] =
{'\0', 'b', 'h', '\0', 'w', '\0', '\0', '\0', 'd'};
@@ -564,7 +564,7 @@ SveElemCountOp::generateDisassembly(
std::string
SvePartBrkOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -578,7 +578,7 @@ SvePartBrkOp::generateDisassembly(
std::string
SvePartBrkPropOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -594,7 +594,7 @@ SvePartBrkPropOp::generateDisassembly(
std::string
SveSelectOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -620,7 +620,7 @@ SveSelectOp::generateDisassembly(
std::string
SveUnaryPredPredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -633,7 +633,7 @@ SveUnaryPredPredOp::generateDisassembly(
}
std::string
SveTblOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
SveTblOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -647,7 +647,7 @@ SveTblOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
std::string
SveUnpackOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -659,7 +659,7 @@ SveUnpackOp::generateDisassembly(
std::string
SvePredTestOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -671,7 +671,7 @@ SvePredTestOp::generateDisassembly(
std::string
SvePredUnaryWImplicitSrcOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -681,7 +681,7 @@ SvePredUnaryWImplicitSrcOp::generateDisassembly(
std::string
SvePredUnaryWImplicitSrcPredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -694,7 +694,7 @@ SvePredUnaryWImplicitSrcPredOp::generateDisassembly(
std::string
SvePredUnaryWImplicitDstOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -704,7 +704,7 @@ SvePredUnaryWImplicitDstOp::generateDisassembly(
std::string
SveWImplicitSrcDstOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -713,7 +713,7 @@ SveWImplicitSrcDstOp::generateDisassembly(
std::string
SveBinImmUnpredDestrOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -729,7 +729,7 @@ SveBinImmUnpredDestrOp::generateDisassembly(
std::string
SveBinImmIdxUnpredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -744,7 +744,7 @@ SveBinImmIdxUnpredOp::generateDisassembly(
std::string
SveUnarySca2VecUnpredOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -760,7 +760,7 @@ SveUnarySca2VecUnpredOp::generateDisassembly(
std::string
SveDotProdIdxOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -777,7 +777,7 @@ SveDotProdIdxOp::generateDisassembly(
std::string
SveDotProdOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -791,7 +791,7 @@ SveDotProdOp::generateDisassembly(
std::string
SveComplexOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -811,7 +811,7 @@ SveComplexOp::generateDisassembly(
std::string
SveComplexIdxOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);

100
src/arch/arm/insts/sve.hh
View File

@@ -68,7 +68,7 @@ class SveIndexIIOp : public ArmStaticInst
dest(_dest), imm1(_imm1), imm2(_imm2)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class SveIndexIROp : public ArmStaticInst
@@ -85,7 +85,7 @@ class SveIndexIROp : public ArmStaticInst
dest(_dest), imm1(_imm1), op2(_op2)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class SveIndexRIOp : public ArmStaticInst
@@ -102,7 +102,7 @@ class SveIndexRIOp : public ArmStaticInst
dest(_dest), op1(_op1), imm2(_imm2)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class SveIndexRROp : public ArmStaticInst
@@ -119,7 +119,7 @@ class SveIndexRROp : public ArmStaticInst
dest(_dest), op1(_op1), op2(_op2)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// Predicate count SVE instruction.
@@ -139,7 +139,7 @@ class SvePredCountOp : public ArmStaticInst
srcIs32b(_srcIs32b), destIsVec(_destIsVec)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// Predicate count SVE instruction (predicated).
@@ -157,7 +157,7 @@ class SvePredCountPredOp : public ArmStaticInst
dest(_dest), op1(_op1), gp(_gp)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// While predicate generation SVE instruction.
@@ -174,7 +174,7 @@ class SveWhileOp : public ArmStaticInst
dest(_dest), op1(_op1), op2(_op2), srcIs32b(_srcIs32b)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Compare and terminate loop SVE instruction.
@@ -189,7 +189,7 @@ class SveCompTermOp : public ArmStaticInst
op1(_op1), op2(_op2)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Unary, constructive, predicated (merging) SVE instruction.
@@ -205,7 +205,7 @@ class SveUnaryPredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Unary, constructive, unpredicated SVE instruction.
@@ -221,7 +221,7 @@ class SveUnaryUnpredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Unary with wide immediate, constructive, unpredicated SVE instruction.
@@ -239,7 +239,7 @@ class SveUnaryWideImmUnpredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Unary with wide immediate, constructive, predicated SVE instruction.
@@ -260,7 +260,7 @@ class SveUnaryWideImmPredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Binary with immediate, destructive, unpredicated SVE instruction.
@@ -278,7 +278,7 @@ class SveBinImmUnpredConstrOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Binary with immediate, destructive, predicated (merging) SVE instruction.
@@ -295,7 +295,7 @@ class SveBinImmPredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Binary with wide immediate, destructive, unpredicated SVE instruction.
@@ -313,7 +313,7 @@ class SveBinWideImmUnpredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Binary, destructive, predicated (merging) SVE instruction.
@@ -330,7 +330,7 @@ class SveBinDestrPredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Binary, constructive, predicated SVE instruction.
@@ -349,7 +349,7 @@ class SveBinConstrPredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Binary, unpredicated SVE instruction with indexed operand
@@ -365,7 +365,7 @@ class SveBinUnpredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Binary, unpredicated SVE instruction
@@ -383,7 +383,7 @@ class SveBinIdxUnpredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Predicate logical instruction.
@@ -401,7 +401,7 @@ class SvePredLogicalOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Predicate binary permute instruction.
@@ -418,7 +418,7 @@ class SvePredBinPermOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE compare instructions, predicated (zeroing).
@@ -435,7 +435,7 @@ class SveCmpOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE compare-with-immediate instructions, predicated (zeroing).
@@ -453,7 +453,7 @@ class SveCmpImmOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Ternary, destructive, predicated (merging) SVE instruction.
@@ -470,7 +470,7 @@ class SveTerPredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Ternary with immediate, destructive, unpredicated SVE instruction.
@@ -488,7 +488,7 @@ class SveTerImmUnpredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE reductions.
@@ -504,7 +504,7 @@ class SveReducOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE ordered reductions.
@@ -520,7 +520,7 @@ class SveOrdReducOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// PTRUE, PTRUES.
@@ -537,7 +537,7 @@ class SvePtrueOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Integer compare SVE instruction.
@@ -556,7 +556,7 @@ class SveIntCmpOp : public ArmStaticInst
dest(_dest), op1(_op1), op2(_op2), gp(_gp), op2IsWide(_op2IsWide)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Integer compare with immediate SVE instruction.
@@ -575,7 +575,7 @@ class SveIntCmpImmOp : public ArmStaticInst
dest(_dest), op1(_op1), imm(_imm), gp(_gp)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// ADR.
@@ -603,7 +603,7 @@ class SveAdrOp : public ArmStaticInst
offsetFormat(_offsetFormat)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Element count SVE instruction.
@@ -625,7 +625,7 @@ class SveElemCountOp : public ArmStaticInst
dstIs32b(_dstIs32b)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Partition break SVE instruction.
@@ -644,7 +644,7 @@ class SvePartBrkOp : public ArmStaticInst
dest(_dest), gp(_gp), op1(_op1), isMerging(_isMerging)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Partition break with propagation SVE instruction.
@@ -663,7 +663,7 @@ class SvePartBrkPropOp : public ArmStaticInst
dest(_dest), op1(_op1), op2(_op2), gp(_gp)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Scalar element select SVE instruction.
@@ -688,7 +688,7 @@ class SveSelectOp : public ArmStaticInst
scalar(_scalar), simdFp(_simdFp)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE unary operation on predicate (predicated)
@@ -706,7 +706,7 @@ class SveUnaryPredPredOp : public ArmStaticInst
dest(_dest), op1(_op1), gp(_gp)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE table lookup/permute using vector of element indices (TBL)
@@ -723,7 +723,7 @@ class SveTblOp : public ArmStaticInst
dest(_dest), op1(_op1), op2(_op2)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE unpack and widen predicate
@@ -739,7 +739,7 @@ class SveUnpackOp : public ArmStaticInst
dest(_dest), op1(_op1)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE predicate test
@@ -755,7 +755,7 @@ class SvePredTestOp : public ArmStaticInst
op1(_op1), gp(_gp)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE unary predicate instructions with implicit source operand
@@ -770,7 +770,7 @@ class SvePredUnaryWImplicitSrcOp : public ArmStaticInst
dest(_dest)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE unary predicate instructions, predicated, with implicit source operand
@@ -787,7 +787,7 @@ class SvePredUnaryWImplicitSrcPredOp : public ArmStaticInst
dest(_dest), gp(_gp)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE unary predicate instructions with implicit destination operand
@@ -802,7 +802,7 @@ class SvePredUnaryWImplicitDstOp : public ArmStaticInst
op1(_op1)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE unary predicate instructions with implicit destination operand
@@ -814,7 +814,7 @@ class SveWImplicitSrcDstOp : public ArmStaticInst
ArmStaticInst(mnem, _machInst, __opClass)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE vector - immediate binary operation
@@ -832,7 +832,7 @@ class SveBinImmUnpredDestrOp : public ArmStaticInst
dest(_dest), op1(_op1), imm(_imm)
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Binary with immediate index, destructive, unpredicated SVE instruction.
@@ -850,7 +850,7 @@ class SveBinImmIdxUnpredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// Unary unpredicated scalar to vector instruction
@@ -868,7 +868,7 @@ class SveUnarySca2VecUnpredOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE dot product instruction (indexed)
@@ -888,7 +888,7 @@ class SveDotProdIdxOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE dot product instruction (vectors)
@@ -907,7 +907,7 @@ class SveDotProdOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE Complex Instructions (vectors)
@@ -926,7 +926,7 @@ class SveComplexOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/// SVE Complex Instructions (indexed)
@@ -945,7 +945,7 @@ class SveComplexIdxOp : public ArmStaticInst
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};

12
src/arch/arm/insts/sve_macromem.hh
View File

@@ -94,7 +94,7 @@ class SveLdStructSS : public PredMacroOp
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -167,7 +167,7 @@ class SveStStructSS : public PredMacroOp
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -240,7 +240,7 @@ class SveLdStructSI : public PredMacroOp
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -314,7 +314,7 @@ class SveStStructSI : public PredMacroOp
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -414,7 +414,7 @@ class SveIndexedMemVI : public PredMacroOp
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
// TODO: add suffix to transfer and base registers
std::stringstream ss;
@@ -519,7 +519,7 @@ class SveIndexedMemSV : public PredMacroOp
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
// TODO: add suffix to transfer and base registers
std::stringstream ss;

8
src/arch/arm/insts/sve_mem.cc
View File

@@ -42,7 +42,7 @@ namespace ArmISA
std::string
SveMemVecFillSpill::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -58,7 +58,7 @@ SveMemVecFillSpill::generateDisassembly(
std::string
SveMemPredFillSpill::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -74,7 +74,7 @@ SveMemPredFillSpill::generateDisassembly(
std::string
SveContigMemSS::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
// TODO: add suffix to transfer register and scaling factor (LSL #<x>)
std::stringstream ss;
@@ -94,7 +94,7 @@ SveContigMemSS::generateDisassembly(
std::string
SveContigMemSI::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
// TODO: add suffix to transfer register
std::stringstream ss;

8
src/arch/arm/insts/sve_mem.hh
View File

@@ -67,7 +67,7 @@ class SveMemVecFillSpill : public ArmStaticInst
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class SveMemPredFillSpill : public ArmStaticInst
@@ -93,7 +93,7 @@ class SveMemPredFillSpill : public ArmStaticInst
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class SveContigMemSS : public ArmStaticInst
@@ -120,7 +120,7 @@ class SveContigMemSS : public ArmStaticInst
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class SveContigMemSI : public ArmStaticInst
@@ -147,7 +147,7 @@ class SveContigMemSI : public ArmStaticInst
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
} // namespace ArmISA

6
src/arch/arm/insts/tme64.cc
View File

@@ -46,7 +46,7 @@ namespace ArmISAInst {
std::string
TmeImmOp64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -56,7 +56,7 @@ TmeImmOp64::generateDisassembly(
std::string
TmeRegNone64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -66,7 +66,7 @@ TmeRegNone64::generateDisassembly(
std::string
MicroTmeBasic64::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);

6
src/arch/arm/insts/tme64.hh
View File

@@ -62,7 +62,7 @@ class MicroTmeBasic64 : public MicroTmeOp
{}
std::string generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const;
const loader::SymbolTable *symtab) const;
};
class TmeImmOp64 : public ArmISA::ArmStaticInst
@@ -77,7 +77,7 @@ class TmeImmOp64 : public ArmISA::ArmStaticInst
{}
std::string generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const;
const loader::SymbolTable *symtab) const;
};
class TmeRegNone64 : public ArmISA::ArmStaticInst
@@ -92,7 +92,7 @@ class TmeRegNone64 : public ArmISA::ArmStaticInst
{}
std::string generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const;
const loader::SymbolTable *symtab) const;
};
class Tstart64 : public TmeRegNone64

18
src/arch/arm/insts/vfp.cc
View File

@@ -47,7 +47,7 @@ using namespace ArmISA;
std::string
FpCondCompRegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -62,7 +62,7 @@ FpCondCompRegOp::generateDisassembly(
std::string
FpCondSelOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -78,7 +78,7 @@ FpCondSelOp::generateDisassembly(
std::string
FpRegRegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -90,7 +90,7 @@ FpRegRegOp::generateDisassembly(
std::string
FpRegImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -101,7 +101,7 @@ FpRegImmOp::generateDisassembly(
std::string
FpRegRegImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -114,7 +114,7 @@ FpRegRegImmOp::generateDisassembly(
std::string
FpRegRegRegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -128,7 +128,7 @@ FpRegRegRegOp::generateDisassembly(
std::string
FpRegRegRegCondOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab)
Addr pc, const loader::SymbolTable *symtab)
const
{
std::stringstream ss;
@@ -144,7 +144,7 @@ FpRegRegRegCondOp::generateDisassembly(
std::string
FpRegRegRegRegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
@@ -160,7 +160,7 @@ FpRegRegRegRegOp::generateDisassembly(
std::string
FpRegRegRegImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);

18
src/arch/arm/insts/vfp.hh
View File

@@ -893,7 +893,7 @@ class FpCondCompRegOp : public FpOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class FpCondSelOp : public FpOp
@@ -910,7 +910,7 @@ class FpCondSelOp : public FpOp
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class FpRegRegOp : public FpOp
@@ -928,7 +928,7 @@ class FpRegRegOp : public FpOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class FpRegImmOp : public FpOp
@@ -946,7 +946,7 @@ class FpRegImmOp : public FpOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class FpRegRegImmOp : public FpOp
@@ -965,7 +965,7 @@ class FpRegRegImmOp : public FpOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class FpRegRegRegOp : public FpOp
@@ -984,7 +984,7 @@ class FpRegRegRegOp : public FpOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class FpRegRegRegCondOp : public FpOp
@@ -1006,7 +1006,7 @@ class FpRegRegRegCondOp : public FpOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class FpRegRegRegRegOp : public FpOp
@@ -1027,7 +1027,7 @@ class FpRegRegRegRegOp : public FpOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class FpRegRegRegImmOp : public FpOp
@@ -1049,7 +1049,7 @@ class FpRegRegRegImmOp : public FpOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}

16
src/arch/arm/isa/templates/sve_mem.isa
View File

@@ -467,7 +467,7 @@ def template SveIndexedMemVIMicroopDeclare {{
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
// TODO: add suffix to transfer register
std::stringstream ss;
@@ -555,7 +555,7 @@ def template SveIndexedMemSVMicroopDeclare {{
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
// TODO: add suffix to transfer and base registers
std::stringstream ss;
@@ -790,7 +790,7 @@ def template SveFirstFaultWritebackMicroopDeclare {{
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
@@ -851,7 +851,7 @@ def template SveGatherLoadCpySrcVecMicroopDeclare {{
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
@@ -929,7 +929,7 @@ def template SveStructMemSIMicroopDeclare {{
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -1206,7 +1206,7 @@ def template SveStructMemSSMicroopDeclare {{
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
printMnemonic(ss, "", false);
@@ -1275,7 +1275,7 @@ def template SveIntrlvMicroopDeclare {{
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
@@ -1316,7 +1316,7 @@ def template SveDeIntrlvMicroopDeclare {{
std::string
generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override
const loader::SymbolTable *symtab) const override
{
std::stringstream ss;
ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));

8
src/arch/arm/linux/fs_workload.cc
View File

@@ -77,7 +77,7 @@ FsLinux::initState()
if (params().early_kernel_symbols) {
auto phys_globals = kernelObj->symtab().globals()->mask(_loadAddrMask);
kernelSymtab.insert(*phys_globals);
Loader::debugSymbolTable.insert(*phys_globals);
loader::debugSymbolTable.insert(*phys_globals);
}
// Setup boot data structure
@@ -93,7 +93,7 @@ FsLinux::initState()
inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
params().dtb_addr);
auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);
auto *dtb_file = new loader::DtbFile(params().dtb_filename);
if (!dtb_file->addBootCmdLine(
commandLine.c_str(), commandLine.size())) {
@@ -156,7 +156,7 @@ FsLinux::initState()
delete[] boot_data;
}
if (getArch() == Loader::Arm64) {
if (getArch() == loader::Arm64) {
// We inform the bootloader of the kernel entry point. This was added
// originally done because the entry offset changed in kernel v5.8.
// Previously the bootloader just used a hardcoded address.
@@ -191,7 +191,7 @@ FsLinux::startup()
FsWorkload::startup();
if (enableContextSwitchStatsDump) {
if (getArch() == Loader::Arm64)
if (getArch() == loader::Arm64)
dumpStats = addKernelFuncEvent<DumpStats64>("__switch_to");
else
dumpStats = addKernelFuncEvent<DumpStats>("__switch_to");

4
src/arch/arm/linux/process.hh
View File

@@ -50,7 +50,7 @@ class ArmLinuxProcess32 : public ArmProcess32
{
public:
ArmLinuxProcess32(const ProcessParams &params,
::Loader::ObjectFile *objFile, ::Loader::Arch _arch) :
loader::ObjectFile *objFile, loader::Arch _arch) :
ArmProcess32(params, objFile, _arch)
{}
@@ -65,7 +65,7 @@ class ArmLinuxProcess64 : public ArmProcess64
{
public:
ArmLinuxProcess64(const ProcessParams &params,
::Loader::ObjectFile *objFile, ::Loader::Arch _arch) :
loader::ObjectFile *objFile, loader::Arch _arch) :
ArmProcess64(params, objFile, _arch)
{}

16
src/arch/arm/linux/se_workload.cc
View File

@@ -55,30 +55,30 @@ class LinuxLoader : public Process::Loader
{
public:
Process *
load(const ProcessParams &params, ::Loader::ObjectFile *obj) override
load(const ProcessParams &params, loader::ObjectFile *obj) override
{
auto arch = obj->getArch();
auto opsys = obj->getOpSys();
if (arch != ::Loader::Arm && arch != ::Loader::Thumb &&
arch != ::Loader::Arm64) {
if (arch != loader::Arm && arch != loader::Thumb &&
arch != loader::Arm64) {
return nullptr;
}
if (opsys == ::Loader::UnknownOpSys) {
if (opsys == loader::UnknownOpSys) {
warn("Unknown operating system; assuming Linux.");
opsys = ::Loader::Linux;
opsys = loader::Linux;
}
if (opsys == ::Loader::LinuxArmOABI) {
if (opsys == loader::LinuxArmOABI) {
fatal("gem5 does not support ARM OABI binaries. Please recompile "
"with an EABI compiler.");
}
if (opsys != ::Loader::Linux)
if (opsys != loader::Linux)
return nullptr;
if (arch == ::Loader::Arm64)
if (arch == loader::Arm64)
return new ArmLinuxProcess64(params, obj, arch);
else
return new ArmLinuxProcess32(params, obj, arch);

16
src/arch/arm/process.cc
View File

@@ -60,7 +60,7 @@
using namespace ArmISA;
ArmProcess::ArmProcess(const ProcessParams &params,
::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
loader::ObjectFile *objFile, loader::Arch _arch)
: Process(params,
new EmulationPageTable(params.name, params.pid, PageBytes),
objFile),
@@ -70,7 +70,7 @@ ArmProcess::ArmProcess(const ProcessParams &params,
}
ArmProcess32::ArmProcess32(const ProcessParams &params,
::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
loader::ObjectFile *objFile, loader::Arch _arch)
: ArmProcess(params, objFile, _arch)
{
Addr brk_point = roundUp(image.maxAddr(), PageBytes);
@@ -85,8 +85,8 @@ ArmProcess32::ArmProcess32(const ProcessParams &params,
}
ArmProcess64::ArmProcess64(
const ProcessParams &params, ::Loader::ObjectFile *objFile,
::Loader::Arch _arch)
const ProcessParams &params, loader::ObjectFile *objFile,
loader::Arch _arch)
: ArmProcess(params, objFile, _arch)
{
Addr brk_point = roundUp(image.maxAddr(), PageBytes);
@@ -271,10 +271,10 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
//Setup the auxilliary vectors. These will already have endian conversion.
//Auxilliary vectors are loaded only for elf formatted executables.
auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile);
auto *elfObject = dynamic_cast<loader::ElfObject *>(objFile);
if (elfObject) {
if (objFile->getOpSys() == ::Loader::Linux) {
if (objFile->getOpSys() == loader::Linux) {
IntType features = armHwcap<IntType>();
//Bits which describe the system hardware capabilities
@@ -465,9 +465,9 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
}
PCState pc;
pc.thumb(arch == ::Loader::Thumb);
pc.thumb(arch == loader::Thumb);
pc.nextThumb(pc.thumb());
pc.aarch64(arch == ::Loader::Arm64);
pc.aarch64(arch == loader::Arm64);
pc.nextAArch64(pc.aarch64());
pc.set(getStartPC() & ~mask(1));
tc->pcState(pc);

14
src/arch/arm/process.hh
View File

@@ -53,9 +53,9 @@
class ArmProcess : public Process
{
protected:
::Loader::Arch arch;
ArmProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile,
::Loader::Arch _arch);
loader::Arch arch;
ArmProcess(const ProcessParams &params, loader::ObjectFile *objFile,
loader::Arch _arch);
template<class IntType>
void argsInit(int pageSize, ArmISA::IntRegIndex spIndex);
@@ -75,8 +75,8 @@ class ArmProcess : public Process
class ArmProcess32 : public ArmProcess
{
public:
ArmProcess32(const ProcessParams &params, ::Loader::ObjectFile *objFile,
::Loader::Arch _arch);
ArmProcess32(const ProcessParams &params, loader::ObjectFile *objFile,
loader::Arch _arch);
protected:
void initState() override;
@@ -88,8 +88,8 @@ class ArmProcess32 : public ArmProcess
class ArmProcess64 : public ArmProcess
{
public:
ArmProcess64(const ProcessParams &params, ::Loader::ObjectFile *objFile,
::Loader::Arch _arch);
ArmProcess64(const ProcessParams &params, loader::ObjectFile *objFile,
loader::Arch _arch);
protected:
void initState() override;

2
src/arch/arm/se_workload.hh
View File

@@ -50,7 +50,7 @@ class SEWorkload : public ::SEWorkload
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
::Loader::Arch getArch() const override { return ::Loader::Arm64; }
::loader::Arch getArch() const override { return ::loader::Arm64; }
using SyscallABI32 = RegABI32;
using SyscallABI64 = RegABI64;

2
src/arch/arm/system.cc
View File

@@ -85,7 +85,7 @@ ArmSystem::ArmSystem(const Params &p)
workload->getEntry(), _resetAddr);
}
bool wl_is_64 = (workload->getArch() == Loader::Arm64);
bool wl_is_64 = (workload->getArch() == loader::Arm64);
if (wl_is_64 != _highestELIs64) {
warn("Highest ARM exception-level set to AArch%d but the workload "
"is for AArch%d. Assuming you wanted these to match.",

4
src/arch/mips/isa/base.isa
View File

@@ -53,7 +53,7 @@ output header {{
void printReg(std::ostream &os, RegId reg) const;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
public:
ExtMachInst machInst;
@@ -97,7 +97,7 @@ output decoder {{
std::string
MipsStaticInst::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;

18
src/arch/mips/isa/formats/branch.isa
View File

@@ -51,7 +51,7 @@ output header {{
mutable Addr cachedPC;
/// Cached symbol table pointer from last disassembly
mutable const Loader::SymbolTable *cachedSymtab;
mutable const loader::SymbolTable *cachedSymtab;
/// Constructor
PCDependentDisassembly(const char *mnem, MachInst _machInst,
@@ -62,7 +62,7 @@ output header {{
}
const std::string &
disassemble(Addr pc, const Loader::SymbolTable *symtab) const;
disassemble(Addr pc, const loader::SymbolTable *symtab) const;
};
/**
@@ -93,7 +93,7 @@ output header {{
using StaticInst::branchTarget;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -123,7 +123,7 @@ output header {{
using StaticInst::branchTarget;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}};
@@ -151,7 +151,7 @@ output decoder {{
const std::string &
PCDependentDisassembly::disassemble(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
if (!cachedDisassembly || pc != cachedPC || symtab != cachedSymtab) {
if (!cachedDisassembly)
@@ -167,7 +167,7 @@ output decoder {{
std::string
Branch::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
@@ -189,7 +189,7 @@ output decoder {{
Addr target = pc + 4 + disp;
Loader::SymbolTable::const_iterator it;
loader::SymbolTable::const_iterator it;
if (symtab && (it = symtab->find(target)) != symtab->end())
ss << it->name;
else
@@ -199,7 +199,7 @@ output decoder {{
}
std::string
Jump::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
Jump::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
@@ -209,7 +209,7 @@ output decoder {{
Addr npc = pc + 4;
ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
} else if (_numSrcRegs == 0) {
Loader::SymbolTable::const_iterator it;
loader::SymbolTable::const_iterator it;
if (symtab && (it = symtab->find(disp)) != symtab->end())
ss << it->name;
else

12
src/arch/mips/isa/formats/control.isa
View File

@@ -39,7 +39,7 @@ output header {{
using MipsStaticInst::MipsStaticInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class CP0TLB : public MipsStaticInst
{
@@ -47,7 +47,7 @@ output header {{
using MipsStaticInst::MipsStaticInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
@@ -57,7 +57,7 @@ output header {{
using MipsStaticInst::MipsStaticInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}};
@@ -139,7 +139,7 @@ def template ControlTLBExecute {{
output decoder {{
std::string
CP0Control::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
@@ -147,7 +147,7 @@ output decoder {{
}
std::string
CP0TLB::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
@@ -155,7 +155,7 @@ output decoder {{
}
std::string
CP1Control::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);

4
src/arch/mips/isa/formats/fp.isa
View File

@@ -49,14 +49,14 @@ output header {{
using FPOp::FPOp;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}};
output decoder {{
std::string
FPCompareOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;

24
src/arch/mips/isa/formats/int.isa
View File

@@ -41,7 +41,7 @@ output header {{
using MipsStaticInst::MipsStaticInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
@@ -51,7 +51,7 @@ output header {{
using IntOp::IntOp;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class HiLoRsSelOp: public HiLoOp
@@ -60,7 +60,7 @@ output header {{
using HiLoOp::HiLoOp;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class HiLoRdSelOp: public HiLoOp
@@ -69,7 +69,7 @@ output header {{
using HiLoOp::HiLoOp;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class HiLoRdSelValOp: public HiLoOp
@@ -78,7 +78,7 @@ output header {{
using HiLoOp::HiLoOp;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class IntImmOp : public MipsStaticInst
@@ -100,7 +100,7 @@ output header {{
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}};
@@ -177,7 +177,7 @@ def template HiLoRdSelExecute {{
output decoder {{
std::string
IntOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
@@ -207,7 +207,7 @@ output decoder {{
std::string
HiLoOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
@@ -228,7 +228,7 @@ output decoder {{
std::string
HiLoRsSelOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
@@ -245,7 +245,7 @@ output decoder {{
std::string
HiLoRdSelOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
@@ -262,7 +262,7 @@ output decoder {{
std::string
HiLoRdSelValOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
@@ -279,7 +279,7 @@ output decoder {{
std::string
IntImmOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;

8
src/arch/mips/isa/formats/mem.isa
View File

@@ -51,7 +51,7 @@ output header {{
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -64,7 +64,7 @@ output header {{
using Memory::Memory;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}};
@@ -72,7 +72,7 @@ output header {{
output decoder {{
std::string
Memory::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
@@ -80,7 +80,7 @@ output decoder {{
std::string
MemoryNoDisp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
flags[IsFloating] ? 'f' : 'r',

4
src/arch/mips/isa/formats/mt.isa
View File

@@ -41,7 +41,7 @@ output header {{
using MipsStaticInst::MipsStaticInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
bool user_mode = false;
};
@@ -59,7 +59,7 @@ output header {{
output decoder {{
std::string
MTOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
MTOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;

4
src/arch/mips/isa/formats/noop.isa
View File

@@ -52,7 +52,7 @@ output header {{
~Nop() { }
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
@@ -60,7 +60,7 @@ output header {{
output decoder {{
std::string
Nop::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
Nop::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s %s", "nop", originalDisassembly);
}

4
src/arch/mips/isa/formats/tlbop.isa
View File

@@ -41,14 +41,14 @@ output header {{
using MipsStaticInst::MipsStaticInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}};
output decoder {{
std::string
TlbOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return "Disassembly of integer instruction\n";
}

8
src/arch/mips/isa/formats/trap.isa
View File

@@ -41,7 +41,7 @@ output header {{
using MipsStaticInst::MipsStaticInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class TrapImm : public MipsStaticInst
{
@@ -53,20 +53,20 @@ output header {{
{}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}};
output decoder {{
std::string
Trap::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return "Disassembly of trap instruction\n";
}
std::string
TrapImm::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return "Disassembly of trap instruction\n";
}

20
src/arch/mips/isa/formats/unimp.isa
View File

@@ -54,7 +54,7 @@ output header {{
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class CP0Unimplemented : public MipsStaticInst
{
@@ -71,7 +71,7 @@ output header {{
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class CP1Unimplemented : public MipsStaticInst
{
@@ -88,7 +88,7 @@ output header {{
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class CP2Unimplemented : public MipsStaticInst
{
@@ -105,7 +105,7 @@ output header {{
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -136,41 +136,41 @@ output header {{
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}};
output decoder {{
std::string
FailUnimplemented::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)", mnemonic);
}
std::string
CP0Unimplemented::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)", mnemonic);
}
std::string
CP1Unimplemented::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)", mnemonic);
}
std::string
CP2Unimplemented::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)", mnemonic);
}
std::string
WarnUnimplemented::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)", mnemonic);
}

4
src/arch/mips/isa/formats/unknown.isa
View File

@@ -52,14 +52,14 @@ output header {{
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}};
output decoder {{
std::string
Unknown::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
"unknown", machInst, OPCODE, inst2string(machInst));

10
src/arch/mips/linux/se_workload.cc
View File

@@ -45,19 +45,19 @@ class LinuxLoader : public Process::Loader
{
public:
Process *
load(const ProcessParams &params, ::Loader::ObjectFile *obj) override
load(const ProcessParams &params, loader::ObjectFile *obj) override
{
if (obj->getArch() != ::Loader::Mips)
if (obj->getArch() != loader::Mips)
return nullptr;
auto opsys = obj->getOpSys();
if (opsys == ::Loader::UnknownOpSys) {
if (opsys == loader::UnknownOpSys) {
warn("Unknown operating system; assuming Linux.");
opsys = ::Loader::Linux;
opsys = loader::Linux;
}
if (opsys != ::Loader::Linux)
if (opsys != loader::Linux)
return nullptr;
return new MipsProcess(params, obj);

4
src/arch/mips/process.cc
View File

@@ -47,7 +47,7 @@
using namespace MipsISA;
MipsProcess::MipsProcess(const ProcessParams &params,
::Loader::ObjectFile *objFile)
loader::ObjectFile *objFile)
: Process(params,
new EmulationPageTable(params.name, params.pid, PageBytes),
objFile)
@@ -90,7 +90,7 @@ MipsProcess::argsInit(int pageSize)
std::vector<gem5::auxv::AuxVector<IntType>> auxv;
auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile);
auto *elfObject = dynamic_cast<loader::ElfObject *>(objFile);
if (elfObject)
{
// Set the system page size

7
src/arch/mips/process.hh
View File

@@ -31,15 +31,16 @@
#include "sim/process.hh"
namespace Loader
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
class ObjectFile;
} // namespace Loader
} // namespace loader
class MipsProcess : public Process
{
public:
MipsProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile);
MipsProcess(const ProcessParams &params, loader::ObjectFile *objFile);
protected:
void initState();

2
src/arch/mips/se_workload.hh
View File

@@ -52,7 +52,7 @@ class SEWorkload : public ::SEWorkload
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
::Loader::Arch getArch() const override { return ::Loader::Mips; }
::loader::Arch getArch() const override { return ::loader::Mips; }
struct SyscallABI : public GenericSyscallABI64
{

12
src/arch/power/insts/branch.cc
View File

@@ -35,7 +35,7 @@ using namespace PowerISA;
const std::string &
PCDependentDisassembly::disassemble(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
if (!cachedDisassembly || pc != cachedPC || symtab != cachedSymtab) {
if (!cachedDisassembly)
@@ -62,7 +62,7 @@ BranchOp::branchTarget(const PowerISA::PCState &pc) const
std::string
BranchOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
Addr target;
@@ -83,7 +83,7 @@ BranchOp::generateDisassembly(
else
target = pc + li;
Loader::SymbolTable::const_iterator it;
loader::SymbolTable::const_iterator it;
if (symtab && (it = symtab->find(target)) != symtab->end())
ss << it->name;
else
@@ -106,7 +106,7 @@ BranchDispCondOp::branchTarget(const PowerISA::PCState &pc) const
std::string
BranchDispCondOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
Addr target;
@@ -130,7 +130,7 @@ BranchDispCondOp::generateDisassembly(
else
target = pc + bd;
Loader::SymbolTable::const_iterator it;
loader::SymbolTable::const_iterator it;
if (symtab && (it = symtab->find(target)) != symtab->end())
ss << it->name;
else
@@ -150,7 +150,7 @@ BranchRegCondOp::branchTarget(ThreadContext *tc) const
std::string
BranchRegCondOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;

10
src/arch/power/insts/branch.hh
View File

@@ -49,7 +49,7 @@ class PCDependentDisassembly : public PowerStaticInst
/// Cached program counter from last disassembly
mutable Addr cachedPC;
/// Cached symbol table pointer from last disassembly
mutable const Loader::SymbolTable *cachedSymtab;
mutable const loader::SymbolTable *cachedSymtab;
/// Constructor
PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
@@ -60,7 +60,7 @@ class PCDependentDisassembly : public PowerStaticInst
}
const std::string &
disassemble(Addr pc, const Loader::SymbolTable *symtab) const;
disassemble(Addr pc, const loader::SymbolTable *symtab) const;
};
@@ -90,7 +90,7 @@ class BranchOp : public PCDependentDisassembly
using StaticInst::branchTarget;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
@@ -161,7 +161,7 @@ class BranchDispCondOp : public BranchCondOp
using StaticInst::branchTarget;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
@@ -188,7 +188,7 @@ class BranchRegCondOp : public BranchCondOp
using StaticInst::branchTarget;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
} // namespace PowerISA

4
src/arch/power/insts/condition.cc
View File

@@ -32,7 +32,7 @@ using namespace PowerISA;
std::string
CondLogicOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
@@ -46,7 +46,7 @@ CondLogicOp::generateDisassembly(
std::string
CondMoveOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;

4
src/arch/power/insts/condition.hh
View File

@@ -56,7 +56,7 @@ class CondLogicOp : public PowerStaticInst
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -78,7 +78,7 @@ class CondMoveOp : public PowerStaticInst
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
} // namespace PowerISA

2
src/arch/power/insts/floating.cc
View File

@@ -31,7 +31,7 @@
using namespace PowerISA;
std::string
FloatOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
FloatOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;

2
src/arch/power/insts/floating.hh
View File

@@ -143,7 +143,7 @@ class FloatOp : public PowerStaticInst
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
} // namespace PowerISA

8
src/arch/power/insts/integer.cc
View File

@@ -31,7 +31,7 @@
using namespace PowerISA;
std::string
IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
IntOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
bool printDest = true;
@@ -87,7 +87,7 @@ IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
std::string
IntImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
IntImmOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
@@ -124,7 +124,7 @@ IntImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
std::string
IntShiftOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
@@ -152,7 +152,7 @@ IntShiftOp::generateDisassembly(
std::string
IntRotateOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;

8
src/arch/power/insts/integer.hh
View File

@@ -93,7 +93,7 @@ class IntOp : public PowerStaticInst
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
@@ -116,7 +116,7 @@ class IntImmOp : public IntOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
@@ -137,7 +137,7 @@ class IntShiftOp : public IntOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
@@ -173,7 +173,7 @@ class IntRotateOp : public IntShiftOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
} // namespace PowerISA

4
src/arch/power/insts/mem.cc
View File

@@ -33,14 +33,14 @@
using namespace PowerISA;
std::string
MemOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
MemOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s", mnemonic);
}
std::string
MemDispOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;

4
src/arch/power/insts/mem.hh
View File

@@ -52,7 +52,7 @@ class MemOp : public PowerStaticInst
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
@@ -73,7 +73,7 @@ class MemDispOp : public MemOp
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**

2
src/arch/power/insts/misc.cc
View File

@@ -31,7 +31,7 @@
using namespace PowerISA;
std::string
MiscOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
MiscOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;

2
src/arch/power/insts/misc.hh
View File

@@ -43,7 +43,7 @@ class MiscOp : public PowerStaticInst
using PowerStaticInst::PowerStaticInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
} // namespace PowerISA

2
src/arch/power/insts/static_inst.cc
View File

@@ -60,7 +60,7 @@ PowerStaticInst::printReg(std::ostream &os, RegId reg) const
std::string
PowerStaticInst::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;

2
src/arch/power/insts/static_inst.hh
View File

@@ -62,7 +62,7 @@ class PowerStaticInst : public StaticInst
printReg(std::ostream &os, RegId reg) const;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
void
advancePC(PowerISA::PCState &pcState) const override

8
src/arch/power/isa/formats/unimp.isa
View File

@@ -55,7 +55,7 @@ output header {{
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -86,21 +86,21 @@ output header {{
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}};
output decoder {{
std::string
FailUnimplemented::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)", mnemonic);
}
std::string
WarnUnimplemented::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (unimplemented)", mnemonic);
}

4
src/arch/power/isa/formats/unknown.isa
View File

@@ -53,14 +53,14 @@ output header {{
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}};
output decoder {{
std::string
Unknown::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
"unknown", machInst, PO, inst2string(machInst));

10
src/arch/power/linux/se_workload.cc
View File

@@ -45,19 +45,19 @@ class LinuxLoader : public Process::Loader
{
public:
Process *
load(const ProcessParams &params, ::Loader::ObjectFile *obj) override
load(const ProcessParams &params, loader::ObjectFile *obj) override
{
if (obj->getArch() != ::Loader::Power)
if (obj->getArch() != loader::Power)
return nullptr;
auto opsys = obj->getOpSys();
if (opsys == ::Loader::UnknownOpSys) {
if (opsys == loader::UnknownOpSys) {
warn("Unknown operating system; assuming Linux.");
opsys = ::Loader::Linux;
opsys = loader::Linux;
}
if (opsys != ::Loader::Linux)
if (opsys != loader::Linux)
return nullptr;
return new PowerProcess(params, obj);

4
src/arch/power/process.cc
View File

@@ -48,7 +48,7 @@
using namespace PowerISA;
PowerProcess::PowerProcess(
const ProcessParams &params, ::Loader::ObjectFile *objFile)
const ProcessParams &params, loader::ObjectFile *objFile)
: Process(params,
new EmulationPageTable(params.name, params.pid, PageBytes),
objFile)
@@ -101,7 +101,7 @@ PowerProcess::argsInit(int intSize, int pageSize)
//Setup the auxilliary vectors. These will already have endian conversion.
//Auxilliary vectors are loaded only for elf formatted executables.
auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile);
auto *elfObject = dynamic_cast<loader::ElfObject *>(objFile);
if (elfObject) {
uint32_t features = 0;

7
src/arch/power/process.hh
View File

@@ -32,10 +32,11 @@
#include "sim/process.hh"
namespace Loader
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
class ObjectFile;
} // namespace Loader;
} // namespace loader
class PowerProcess : public Process
{
@@ -43,7 +44,7 @@ class PowerProcess : public Process
void initState() override;
public:
PowerProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile);
PowerProcess(const ProcessParams &params, loader::ObjectFile *objFile);
void argsInit(int intSize, int pageSize);
};

2
src/arch/power/se_workload.hh
View File

@@ -52,7 +52,7 @@ class SEWorkload : public ::SEWorkload
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
::Loader::Arch getArch() const override { return ::Loader::Power; }
::loader::Arch getArch() const override { return ::loader::Power; }
struct SyscallABI : public GenericSyscallABI64
{

2
src/arch/riscv/bare_metal/fs_workload.cc
View File

@@ -39,7 +39,7 @@ namespace RiscvISA
BareMetal::BareMetal(const Params &p) : Workload(p),
_isBareMetal(p.bare_metal), _resetVect(p.reset_vect),
bootloader(Loader::createObjectFile(p.bootloader))
bootloader(loader::createObjectFile(p.bootloader))
{
fatal_if(!bootloader, "Could not load bootloader file %s.", p.bootloader);
_resetVect = bootloader->entryPoint();

11
src/arch/riscv/bare_metal/fs_workload.hh
View File

@@ -43,8 +43,8 @@ class BareMetal : public Workload
bool _isBareMetal;
// entry point for simulation
Addr _resetVect;
Loader::ObjectFile *bootloader;
Loader::SymbolTable bootloaderSymtab;
loader::ObjectFile *bootloader;
loader::SymbolTable bootloaderSymtab;
public:
PARAMS(RiscvBareMetal);
@@ -60,15 +60,16 @@ class BareMetal : public Workload
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
Loader::Arch getArch() const override { return bootloader->getArch(); }
const Loader::SymbolTable &
loader::Arch getArch() const override { return bootloader->getArch(); }
const loader::SymbolTable &
symtab(ThreadContext *tc) override
{
return bootloaderSymtab;
}
bool
insertSymbol(const Loader::Symbol &symbol) override
insertSymbol(const loader::Symbol &symbol) override
{
return bootloaderSymtab.insert(symbol);
}

14
src/arch/riscv/insts/amo.cc
View File

@@ -43,7 +43,7 @@ namespace RiscvISA
// memfence micro instruction
std::string
MemFenceMicro::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
@@ -59,7 +59,7 @@ Fault MemFenceMicro::execute(ExecContext *xc,
// load-reserved
std::string
LoadReserved::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic;
@@ -76,7 +76,7 @@ LoadReserved::generateDisassembly(
std::string
LoadReservedMicro::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ("
@@ -87,7 +87,7 @@ LoadReservedMicro::generateDisassembly(
// store-conditional
std::string
StoreCond::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic;
@@ -105,7 +105,7 @@ StoreCond::generateDisassembly(
std::string
StoreCondMicro::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
@@ -117,7 +117,7 @@ StoreCondMicro::generateDisassembly(
// AMOs
std::string
AtomicMemOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic;
@@ -135,7 +135,7 @@ AtomicMemOp::generateDisassembly(
std::string
AtomicMemOpMicro::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "

14
src/arch/riscv/insts/amo.hh
View File

@@ -51,7 +51,7 @@ class MemFenceMicro : public RiscvMicroInst
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// load-reserved
@@ -61,7 +61,7 @@ class LoadReserved : public RiscvMacroInst
using RiscvMacroInst::RiscvMacroInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class LoadReservedMicro : public RiscvMicroInst
@@ -71,7 +71,7 @@ class LoadReservedMicro : public RiscvMicroInst
using RiscvMicroInst::RiscvMicroInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// store-cond
@@ -81,7 +81,7 @@ class StoreCond : public RiscvMacroInst
using RiscvMacroInst::RiscvMacroInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class StoreCondMicro : public RiscvMicroInst
@@ -91,7 +91,7 @@ class StoreCondMicro : public RiscvMicroInst
using RiscvMicroInst::RiscvMicroInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
// AMOs
@@ -101,7 +101,7 @@ class AtomicMemOp : public RiscvMacroInst
using RiscvMacroInst::RiscvMacroInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class AtomicMemOpMicro : public RiscvMicroInst
@@ -111,7 +111,7 @@ class AtomicMemOpMicro : public RiscvMicroInst
using RiscvMicroInst::RiscvMicroInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**

2
src/arch/riscv/insts/compressed.cc
View File

@@ -40,7 +40,7 @@ namespace RiscvISA
std::string
CompRegOp::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<

2
src/arch/riscv/insts/compressed.hh
View File

@@ -47,7 +47,7 @@ class CompRegOp : public RiscvStaticInst
using RiscvStaticInst::RiscvStaticInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}

4
src/arch/riscv/insts/mem.cc
View File

@@ -41,7 +41,7 @@ namespace RiscvISA
{
std::string
Load::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
Load::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
@@ -50,7 +50,7 @@ Load::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
}
std::string
Store::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
Store::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(srcRegIdx(1)) << ", " <<

4
src/arch/riscv/insts/mem.hh
View File

@@ -56,7 +56,7 @@ class Load : public MemInst
using MemInst::MemInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
class Store : public MemInst
@@ -65,7 +65,7 @@ class Store : public MemInst
using MemInst::MemInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}

2
src/arch/riscv/insts/pseudo.hh
View File

@@ -42,7 +42,7 @@ class PseudoOp : public RiscvStaticInst
using RiscvStaticInst::RiscvStaticInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override
Addr pc, const loader::SymbolTable *symtab) const override
{
return mnemonic;
}

6
src/arch/riscv/insts/standard.cc
View File

@@ -42,7 +42,7 @@ namespace RiscvISA
{
std::string
RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
RegOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
@@ -55,7 +55,7 @@ RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
}
std::string
CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
CSROp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ";
@@ -72,7 +72,7 @@ CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
}
std::string
SystemOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
SystemOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
{
if (strcmp(mnemonic, "fence_vma") == 0) {
std::stringstream ss;

6
src/arch/riscv/insts/standard.hh
View File

@@ -51,7 +51,7 @@ class RegOp : public RiscvStaticInst
using RiscvStaticInst::RiscvStaticInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -77,7 +77,7 @@ class SystemOp : public RiscvStaticInst
using RiscvStaticInst::RiscvStaticInst;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
/**
@@ -119,7 +119,7 @@ class CSROp : public RiscvStaticInst
}
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}

2
src/arch/riscv/insts/unknown.hh
View File

@@ -62,7 +62,7 @@ class Unknown : public RiscvStaticInst
std::string
generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override
Addr pc, const loader::SymbolTable *symtab) const override
{
return csprintf("unknown opcode %#02x", OPCODE);
}

4
src/arch/riscv/isa/formats/compressed.isa
View File

@@ -128,7 +128,7 @@ def template CBasicDeclare {{
%(class_name)s(MachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
};
}};
@@ -147,7 +147,7 @@ def template CBasicExecute {{
std::string
%(class_name)s::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::vector<RegId> indices = {%(regs)s};
std::stringstream ss;

16
src/arch/riscv/isa/formats/standard.isa
View File

@@ -47,7 +47,7 @@ def template ImmDeclare {{
%(class_name)s(MachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::string generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const override;
const loader::SymbolTable *symtab) const override;
};
}};
@@ -75,7 +75,7 @@ def template ImmExecute {{
std::string
%(class_name)s::generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const
const loader::SymbolTable *symtab) const
{
std::vector<RegId> indices = {%(regs)s};
std::stringstream ss;
@@ -101,7 +101,7 @@ def template CILuiExecute {{
std::string
%(class_name)s::generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const
const loader::SymbolTable *symtab) const
{
std::vector<RegId> indices = {%(regs)s};
std::stringstream ss;
@@ -129,7 +129,7 @@ def template FenceExecute {{
std::string
%(class_name)s::generateDisassembly(Addr pc,
const Loader::SymbolTable *symtab) const
const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic;
@@ -173,7 +173,7 @@ def template BranchDeclare {{
std::string
generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
RiscvISA::PCState
branchTarget(const RiscvISA::PCState &branchPC) const override;
@@ -202,7 +202,7 @@ def template BranchExecute {{
std::string
%(class_name)s::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::vector<RegId> indices = {%(regs)s};
std::stringstream ss;
@@ -230,7 +230,7 @@ def template JumpDeclare {{
std::string
generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const override;
Addr pc, const loader::SymbolTable *symtab) const override;
RiscvISA::PCState
branchTarget(ThreadContext *tc) const override;
@@ -261,7 +261,7 @@ def template JumpExecute {{
std::string
%(class_name)s::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream ss;
ss << mnemonic << ' ';

2
src/arch/riscv/linux/fs_workload.cc
View File

@@ -47,7 +47,7 @@ FsLinux::initState()
inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
params().dtb_addr);
auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);
auto *dtb_file = new loader::DtbFile(params().dtb_filename);
if (!dtb_file->addBootCmdLine(
commandLine.c_str(), commandLine.size())) {

12
src/arch/riscv/linux/se_workload.cc
View File

@@ -45,23 +45,23 @@ class LinuxLoader : public Process::Loader
{
public:
Process *
load(const ProcessParams &params, ::Loader::ObjectFile *obj) override
load(const ProcessParams &params, loader::ObjectFile *obj) override
{
auto arch = obj->getArch();
auto opsys = obj->getOpSys();
if (arch != ::Loader::Riscv64 && arch != ::Loader::Riscv32)
if (arch != loader::Riscv64 && arch != loader::Riscv32)
return nullptr;
if (opsys == ::Loader::UnknownOpSys) {
if (opsys == loader::UnknownOpSys) {
warn("Unknown operating system; assuming Linux.");
opsys = ::Loader::Linux;
opsys = loader::Linux;
}
if (opsys != ::Loader::Linux)
if (opsys != loader::Linux)
return nullptr;
if (arch == ::Loader::Riscv64)
if (arch == loader::Riscv64)
return new RiscvProcess64(params, obj);
else
return new RiscvProcess32(params, obj);

8
src/arch/riscv/process.cc
View File

@@ -58,7 +58,7 @@
using namespace RiscvISA;
RiscvProcess::RiscvProcess(const ProcessParams &params,
::Loader::ObjectFile *objFile) :
loader::ObjectFile *objFile) :
Process(params,
new EmulationPageTable(params.name, params.pid, PageBytes),
objFile)
@@ -67,7 +67,7 @@ RiscvProcess::RiscvProcess(const ProcessParams &params,
}
RiscvProcess64::RiscvProcess64(const ProcessParams &params,
::Loader::ObjectFile *objFile) :
loader::ObjectFile *objFile) :
RiscvProcess(params, objFile)
{
const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
@@ -80,7 +80,7 @@ RiscvProcess64::RiscvProcess64(const ProcessParams &params,
}
RiscvProcess32::RiscvProcess32(const ProcessParams &params,
::Loader::ObjectFile *objFile) :
loader::ObjectFile *objFile) :
RiscvProcess(params, objFile)
{
const Addr stack_base = 0x7FFFFFFF;
@@ -123,7 +123,7 @@ RiscvProcess::argsInit(int pageSize)
const int RandomBytes = 16;
const int addrSize = sizeof(IntType);
auto *elfObject = dynamic_cast<::Loader::ElfObject*>(objFile);
auto *elfObject = dynamic_cast<loader::ElfObject*>(objFile);
memState->setStackMin(memState->getStackBase());
// Determine stack size and populate auxv

11
src/arch/riscv/process.hh
View File

@@ -37,17 +37,18 @@
#include "sim/process.hh"
#include "sim/syscall_abi.hh"
namespace Loader
GEM5_DEPRECATED_NAMESPACE(Loader, loader);
namespace loader
{
class ObjectFile;
} // namespace Loader
} // namespace loader
class System;
class RiscvProcess : public Process
{
protected:
RiscvProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile);
RiscvProcess(const ProcessParams &params, loader::ObjectFile *objFile);
template<class IntType>
void argsInit(int pageSize);
@@ -58,7 +59,7 @@ class RiscvProcess : public Process
class RiscvProcess64 : public RiscvProcess
{
public:
RiscvProcess64(const ProcessParams &params, ::Loader::ObjectFile *objFile);
RiscvProcess64(const ProcessParams &params, loader::ObjectFile *objFile);
protected:
void initState() override;
@@ -67,7 +68,7 @@ class RiscvProcess64 : public RiscvProcess
class RiscvProcess32 : public RiscvProcess
{
public:
RiscvProcess32(const ProcessParams &params, ::Loader::ObjectFile *objFile);
RiscvProcess32(const ProcessParams &params, loader::ObjectFile *objFile);
protected:
void initState() override;

2
src/arch/riscv/se_workload.hh
View File

@@ -52,7 +52,7 @@ class SEWorkload : public ::SEWorkload
gdb = BaseRemoteGDB::build<RemoteGDB>(system);
}
::Loader::Arch getArch() const override { return ::Loader::Riscv64; }
::loader::Arch getArch() const override { return ::loader::Riscv64; }
//FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
using SyscallABI = RegABI64;

8
src/arch/sparc/fs_workload.hh
View File

@@ -40,7 +40,7 @@ namespace SparcISA
class FsWorkload : public Workload
{
protected:
Loader::SymbolTable defaultSymtab;
loader::SymbolTable defaultSymtab;
public:
FsWorkload(const SparcFsWorkloadParams &params) : Workload(params) {}
@@ -60,16 +60,16 @@ class FsWorkload : public Workload
getREDVector(0x001, pc, npc);
return pc;
}
Loader::Arch getArch() const override { return Loader::SPARC64; }
loader::Arch getArch() const override { return loader::SPARC64; }
const Loader::SymbolTable &
const loader::SymbolTable &
symtab(ThreadContext *tc) override
{
return defaultSymtab;
}
bool
insertSymbol(const Loader::Symbol &symbol) override
insertSymbol(const loader::Symbol &symbol) override
{
return defaultSymtab.insert(symbol);
}

4
src/arch/sparc/insts/blockmem.cc
View File

@@ -33,7 +33,7 @@ namespace SparcISA
std::string
BlockMemMicro::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream response;
bool load = flags[IsLoad];
@@ -59,7 +59,7 @@ BlockMemMicro::generateDisassembly(
std::string
BlockMemImmMicro::generateDisassembly(
Addr pc, const Loader::SymbolTable *symtab) const
Addr pc, const loader::SymbolTable *symtab) const
{
std::stringstream response;
bool load = flags[IsLoad];

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