diff --git a/src/arch/arm/freebsd/fs_workload.cc b/src/arch/arm/freebsd/fs_workload.cc
index d6e9533811..d2cc750ebf 100644
--- a/src/arch/arm/freebsd/fs_workload.cc
+++ b/src/arch/arm/freebsd/fs_workload.cc
@@ -81,7 +81,7 @@ FsFreebsd::initState()
     if (params().early_kernel_symbols) {
         auto phys_globals = kernelObj->symtab().globals()->mask(_loadAddrMask);
         kernelSymtab.insert(*phys_globals);
-        Loader::debugSymbolTable.insert(*phys_globals);
+        loader::debugSymbolTable.insert(*phys_globals);
     }
 
     // Check if the kernel image has a symbol that tells us it supports
@@ -95,7 +95,7 @@ FsFreebsd::initState()
     inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
             params().dtb_addr);
 
-    auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);
+    auto *dtb_file = new loader::DtbFile(params().dtb_filename);
 
     warn_if(!dtb_file->addBootCmdLine(commandLine.c_str(), commandLine.size()),
             "Couldn't append bootargs to DTB file: %s",
diff --git a/src/arch/arm/freebsd/se_workload.cc b/src/arch/arm/freebsd/se_workload.cc
index 5e52485eee..70eab8ab80 100644
--- a/src/arch/arm/freebsd/se_workload.cc
+++ b/src/arch/arm/freebsd/se_workload.cc
@@ -51,20 +51,20 @@ class FreebsdLoader : public Process::Loader
 {
   public:
     Process *
-    load(const ProcessParams &params, ::Loader::ObjectFile *obj) override
+    load(const ProcessParams &params, loader::ObjectFile *obj) override
     {
         auto arch = obj->getArch();
         auto opsys = obj->getOpSys();
 
-        if (arch != ::Loader::Arm && arch != ::Loader::Thumb &&
-                arch != ::Loader::Arm64) {
+        if (arch != loader::Arm && arch != loader::Thumb &&
+                arch != loader::Arm64) {
             return nullptr;
         }
 
-        if (opsys != ::Loader::FreeBSD)
+        if (opsys != loader::FreeBSD)
             return nullptr;
 
-        if (arch == ::Loader::Arm64)
+        if (arch == loader::Arm64)
             return new ArmProcess64(params, obj, arch);
         else
             return new ArmProcess32(params, obj, arch);
diff --git a/src/arch/arm/fs_workload.cc b/src/arch/arm/fs_workload.cc
index a731a8100d..21ca993ac3 100644
--- a/src/arch/arm/fs_workload.cc
+++ b/src/arch/arm/fs_workload.cc
@@ -78,8 +78,8 @@ FsWorkload::FsWorkload(const Params &p) : KernelWorkload(p)
 
     bootLoaders.reserve(p.boot_loader.size());
     for (const auto &bl : p.boot_loader) {
-        std::unique_ptr<Loader::ObjectFile> bl_obj;
-        bl_obj.reset(Loader::createObjectFile(bl));
+        std::unique_ptr<loader::ObjectFile> bl_obj;
+        bl_obj.reset(loader::createObjectFile(bl));
 
         fatal_if(!bl_obj, "Could not read bootloader: %s", bl);
         bootLoaders.emplace_back(std::move(bl_obj));
@@ -91,7 +91,7 @@ FsWorkload::FsWorkload(const Params &p) : KernelWorkload(p)
              "Can't find a matching boot loader / kernel combination!");
 
     if (bootldr)
-        Loader::debugSymbolTable.insert(*bootldr->symtab().globals());
+        loader::debugSymbolTable.insert(*bootldr->symtab().globals());
 }
 
 void
@@ -130,7 +130,7 @@ FsWorkload::initState()
             tc->setIntReg(3, kernelEntry);
             if (is_gic_v2)
                 tc->setIntReg(4, arm_sys->params().gic_cpu_addr);
-            if (getArch() == Loader::Arm)
+            if (getArch() == loader::Arm)
                 tc->setIntReg(5, params().cpu_release_addr);
         }
         inform("Using kernel entry physical address at %#x\n", kernelEntry);
@@ -141,8 +141,8 @@ FsWorkload::initState()
     }
 }
 
-    Loader::ObjectFile *
-FsWorkload::getBootLoader(Loader::ObjectFile *const obj)
+    loader::ObjectFile *
+FsWorkload::getBootLoader(loader::ObjectFile *const obj)
 {
     if (obj) {
         for (auto &bl : bootLoaders) {
diff --git a/src/arch/arm/fs_workload.hh b/src/arch/arm/fs_workload.hh
index c85f867be8..b3d7f48758 100644
--- a/src/arch/arm/fs_workload.hh
+++ b/src/arch/arm/fs_workload.hh
@@ -66,12 +66,12 @@ class FsWorkload : public KernelWorkload
 {
   protected:
     /** Bootloaders */
-    std::vector<std::unique_ptr<Loader::ObjectFile>> bootLoaders;
+    std::vector<std::unique_ptr<loader::ObjectFile>> bootLoaders;
 
     /**
      * Pointer to the bootloader object
      */
-    Loader::ObjectFile *bootldr = nullptr;
+    loader::ObjectFile *bootldr = nullptr;
 
     /**
      * This differs from entry since it takes into account where
@@ -87,14 +87,14 @@ class FsWorkload : public KernelWorkload
      * @return Pointer to boot loader ObjectFile or nullptr if there
      *         is no matching boot loader.
      */
-    Loader::ObjectFile *getBootLoader(Loader::ObjectFile *const obj);
+    loader::ObjectFile *getBootLoader(loader::ObjectFile *const obj);
 
     template <template <class ABI, class Base> class FuncEvent,
              typename... Args>
     PCEvent *
     addSkipFunc(Args... args)
     {
-        if (getArch() == Loader::Arm64) {
+        if (getArch() == loader::Arm64) {
             return addKernelFuncEvent<FuncEvent<Aapcs64, SkipFunc>>(
                     std::forward<Args>(args)...);
         } else {
@@ -108,7 +108,7 @@ class FsWorkload : public KernelWorkload
     PCEvent *
     addSkipFuncOrPanic(Args... args)
     {
-        if (getArch() == Loader::Arm64) {
+        if (getArch() == loader::Arm64) {
             return addKernelFuncEventOrPanic<FuncEvent<Aapcs64, SkipFunc>>(
                     std::forward<Args>(args)...);
         } else {
@@ -129,7 +129,7 @@ class FsWorkload : public KernelWorkload
             return kernelEntry;
     }
 
-    Loader::Arch
+    loader::Arch
     getArch() const override
     {
         if (bootldr)
@@ -137,7 +137,7 @@ class FsWorkload : public KernelWorkload
         else if (kernelObj)
             return kernelObj->getArch();
         else
-            return Loader::Arm64;
+            return loader::Arm64;
     }
 
     FsWorkload(const Params &p);
diff --git a/src/arch/arm/insts/branch.cc b/src/arch/arm/insts/branch.cc
index 053ad2ece8..91a9d516c4 100644
--- a/src/arch/arm/insts/branch.cc
+++ b/src/arch/arm/insts/branch.cc
@@ -43,7 +43,7 @@ namespace ArmISA {
 
 std::string
 BranchReg::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -53,7 +53,7 @@ BranchReg::generateDisassembly(
 
 std::string
 BranchImm::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -63,7 +63,7 @@ BranchImm::generateDisassembly(
 
 std::string
 BranchRegReg::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
diff --git a/src/arch/arm/insts/branch.hh b/src/arch/arm/insts/branch.hh
index bbb1cc8c66..52836f6cb9 100644
--- a/src/arch/arm/insts/branch.hh
+++ b/src/arch/arm/insts/branch.hh
@@ -58,7 +58,7 @@ class BranchImm : public PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // Conditionally Branch to a target computed with an immediate
@@ -88,7 +88,7 @@ class BranchReg : public PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // Conditionally Branch to a target computed with a register
@@ -119,7 +119,7 @@ class BranchRegReg : public PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // Branch to a target computed with an immediate and a register
diff --git a/src/arch/arm/insts/branch64.cc b/src/arch/arm/insts/branch64.cc
index 2338f60d7b..1fe1919c09 100644
--- a/src/arch/arm/insts/branch64.cc
+++ b/src/arch/arm/insts/branch64.cc
@@ -69,7 +69,7 @@ BranchImmImmReg64::branchTarget(const ArmISA::PCState &branchPC) const
 
 std::string
 BranchImmCond64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false, true, condCode);
@@ -79,7 +79,7 @@ BranchImmCond64::generateDisassembly(
 
 std::string
 BranchImm64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -89,7 +89,7 @@ BranchImm64::generateDisassembly(
 
 std::string
 BranchReg64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -99,7 +99,7 @@ BranchReg64::generateDisassembly(
 
 std::string
 BranchRegReg64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -111,7 +111,7 @@ BranchRegReg64::generateDisassembly(
 
 std::string
 BranchRet64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -122,7 +122,7 @@ BranchRet64::generateDisassembly(
 
 std::string
 BranchRetA64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -133,7 +133,7 @@ BranchRetA64::generateDisassembly(
 
 std::string
 BranchEret64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -142,7 +142,7 @@ BranchEret64::generateDisassembly(
 
 std::string
 BranchEretA64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -151,7 +151,7 @@ BranchEretA64::generateDisassembly(
 
 std::string
 BranchImmReg64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -163,7 +163,7 @@ BranchImmReg64::generateDisassembly(
 
 std::string
 BranchImmImmReg64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
diff --git a/src/arch/arm/insts/branch64.hh b/src/arch/arm/insts/branch64.hh
index 179326a1d0..407866bcc0 100644
--- a/src/arch/arm/insts/branch64.hh
+++ b/src/arch/arm/insts/branch64.hh
@@ -61,7 +61,7 @@ class BranchImm64 : public ArmStaticInst
     using StaticInst::branchTarget;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // Conditionally Branch to a target computed with an immediate
@@ -77,7 +77,7 @@ class BranchImmCond64 : public BranchImm64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // Branch to a target computed with two registers
@@ -94,7 +94,7 @@ class BranchRegReg64 : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // Branch to a target computed with a register
@@ -110,7 +110,7 @@ class BranchReg64 : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // Ret instruction
@@ -123,7 +123,7 @@ class BranchRet64 : public BranchReg64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // RetAA/RetAB instruction
@@ -136,7 +136,7 @@ class BranchRetA64 : public BranchRegReg64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // Eret instruction
@@ -148,7 +148,7 @@ class BranchEret64 : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // EretA/B instruction
@@ -163,7 +163,7 @@ class BranchEretA64 : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 // Branch to a target computed with an immediate and a register
 class BranchImmReg64 : public ArmStaticInst
@@ -185,7 +185,7 @@ class BranchImmReg64 : public ArmStaticInst
     using StaticInst::branchTarget;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // Branch to a target computed with two immediates
@@ -211,7 +211,7 @@ class BranchImmImmReg64 : public ArmStaticInst
     using StaticInst::branchTarget;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 }
diff --git a/src/arch/arm/insts/data64.cc b/src/arch/arm/insts/data64.cc
index 3c6b4fb984..847834fbf6 100644
--- a/src/arch/arm/insts/data64.cc
+++ b/src/arch/arm/insts/data64.cc
@@ -42,7 +42,7 @@ namespace ArmISA
 
 std::string
 DataXImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
@@ -52,7 +52,7 @@ DataXImmOp::generateDisassembly(
 
 std::string
 DataXImmOnlyOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -63,7 +63,7 @@ DataXImmOnlyOp::generateDisassembly(
 
 std::string
 DataXSRegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
@@ -73,7 +73,7 @@ DataXSRegOp::generateDisassembly(
 
 std::string
 DataXERegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
@@ -83,7 +83,7 @@ DataXERegOp::generateDisassembly(
 
 std::string
 DataX1RegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -95,7 +95,7 @@ DataX1RegOp::generateDisassembly(
 
 std::string
 DataX1RegImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -108,7 +108,7 @@ DataX1RegImmOp::generateDisassembly(
 
 std::string
 DataX1Reg2ImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -121,7 +121,7 @@ DataX1Reg2ImmOp::generateDisassembly(
 
 std::string
 DataX2RegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -135,7 +135,7 @@ DataX2RegOp::generateDisassembly(
 
 std::string
 DataX2RegImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -150,7 +150,7 @@ DataX2RegImmOp::generateDisassembly(
 
 std::string
 DataX3RegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -166,7 +166,7 @@ DataX3RegOp::generateDisassembly(
 
 std::string
 DataXCondCompImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -179,7 +179,7 @@ DataXCondCompImmOp::generateDisassembly(
 
 std::string
 DataXCondCompRegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -194,7 +194,7 @@ DataXCondCompRegOp::generateDisassembly(
 
 std::string
 DataXCondSelOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
diff --git a/src/arch/arm/insts/data64.hh b/src/arch/arm/insts/data64.hh
index 352a7b1982..cb29f54d0a 100644
--- a/src/arch/arm/insts/data64.hh
+++ b/src/arch/arm/insts/data64.hh
@@ -57,7 +57,7 @@ class DataXImmOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataXImmOnlyOp : public ArmStaticInst
@@ -73,7 +73,7 @@ class DataXImmOnlyOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataXSRegOp : public ArmStaticInst
@@ -92,7 +92,7 @@ class DataXSRegOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataXERegOp : public ArmStaticInst
@@ -111,7 +111,7 @@ class DataXERegOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataX1RegOp : public ArmStaticInst
@@ -125,7 +125,7 @@ class DataX1RegOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataX1RegImmOp : public ArmStaticInst
@@ -141,7 +141,7 @@ class DataX1RegImmOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataX1Reg2ImmOp : public ArmStaticInst
@@ -158,7 +158,7 @@ class DataX1Reg2ImmOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataX2RegOp : public ArmStaticInst
@@ -173,7 +173,7 @@ class DataX2RegOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataX2RegImmOp : public ArmStaticInst
@@ -190,7 +190,7 @@ class DataX2RegImmOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataX3RegOp : public ArmStaticInst
@@ -206,7 +206,7 @@ class DataX3RegOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataXCondCompImmOp : public ArmStaticInst
@@ -225,7 +225,7 @@ class DataXCondCompImmOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataXCondCompRegOp : public ArmStaticInst
@@ -243,7 +243,7 @@ class DataXCondCompRegOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataXCondSelOp : public ArmStaticInst
@@ -260,7 +260,7 @@ class DataXCondSelOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 }
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index a5eb182f66..fa31a95e7b 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -1512,7 +1512,7 @@ MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst,
 
 std::string
 MicroIntImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -1526,7 +1526,7 @@ MicroIntImmOp::generateDisassembly(
 
 std::string
 MicroIntImmXOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -1540,7 +1540,7 @@ MicroIntImmXOp::generateDisassembly(
 
 std::string
 MicroSetPCCPSR::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -1550,7 +1550,7 @@ MicroSetPCCPSR::generateDisassembly(
 
 std::string
 MicroIntRegXOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -1563,7 +1563,7 @@ MicroIntRegXOp::generateDisassembly(
 
 std::string
 MicroIntMov::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -1575,7 +1575,7 @@ MicroIntMov::generateDisassembly(
 
 std::string
 MicroIntOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -1589,7 +1589,7 @@ MicroIntOp::generateDisassembly(
 
 std::string
 MicroMemOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -1607,7 +1607,7 @@ MicroMemOp::generateDisassembly(
 
 std::string
 MicroMemPairOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index 20e3dbd42a..048b54831a 100644
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -262,7 +262,7 @@ class MicroSetPCCPSR : public MicroOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -281,7 +281,7 @@ class MicroIntMov : public MicroOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -301,7 +301,7 @@ class MicroIntImmOp : public MicroOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MicroIntImmXOp : public MicroOpX
@@ -318,7 +318,7 @@ class MicroIntImmXOp : public MicroOpX
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -337,7 +337,7 @@ class MicroIntOp : public MicroOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MicroIntRegXOp : public MicroOp
@@ -357,7 +357,7 @@ class MicroIntRegXOp : public MicroOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -397,7 +397,7 @@ class MicroMemOp : public MicroIntImmOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MicroMemPairOp : public MicroOp
@@ -418,7 +418,7 @@ class MicroMemPairOp : public MicroOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index 8ee3f49290..f72f3373c2 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -74,7 +74,7 @@ MemoryReg::printOffset(std::ostream &os) const
 }
 
 std::string
-RfeOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+RfeOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     switch (mode) {
@@ -99,7 +99,7 @@ RfeOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-SrsOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+SrsOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     switch (mode) {
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index 1ffcebb898..eae6aabbce 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -109,7 +109,7 @@ class RfeOp : public MightBeMicro
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // The address is a base register plus an immediate.
@@ -151,7 +151,7 @@ class SrsOp : public MightBeMicro
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class Memory : public MightBeMicro
@@ -376,7 +376,7 @@ class MemoryOffset : public Base
 
     std::string
     generateDisassembly(Addr pc,
-                        const Loader::SymbolTable *symtab) const override
+                        const loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         this->printInst(ss, Memory::AddrMd_Offset);
@@ -427,7 +427,7 @@ class MemoryPreIndex : public Base
 
     std::string
     generateDisassembly(Addr pc,
-                        const Loader::SymbolTable *symtab) const override
+                        const loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         this->printInst(ss, Memory::AddrMd_PreIndex);
@@ -478,7 +478,7 @@ class MemoryPostIndex : public Base
 
     std::string
     generateDisassembly(Addr pc,
-                        const Loader::SymbolTable *symtab) const override
+                        const loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         this->printInst(ss, Memory::AddrMd_PostIndex);
diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index 44fe7357bf..28ca88f794 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -45,7 +45,7 @@ namespace ArmISA
 {
 
 std::string
-SysDC64::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+SysDC64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -84,7 +84,7 @@ Memory64::setExcAcRel(bool exclusive, bool acrel)
 
 std::string
 MemoryImm64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     startDisassembly(ss);
@@ -96,7 +96,7 @@ MemoryImm64::generateDisassembly(
 
 std::string
 MemoryDImm64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -113,7 +113,7 @@ MemoryDImm64::generateDisassembly(
 
 std::string
 MemoryDImmEx64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -132,7 +132,7 @@ MemoryDImmEx64::generateDisassembly(
 
 std::string
 MemoryPreIndex64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     startDisassembly(ss);
@@ -142,7 +142,7 @@ MemoryPreIndex64::generateDisassembly(
 
 std::string
 MemoryPostIndex64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     startDisassembly(ss);
@@ -154,7 +154,7 @@ MemoryPostIndex64::generateDisassembly(
 
 std::string
 MemoryReg64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     startDisassembly(ss);
@@ -165,7 +165,7 @@ MemoryReg64::generateDisassembly(
 
 std::string
 MemoryRaw64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     startDisassembly(ss);
@@ -175,7 +175,7 @@ MemoryRaw64::generateDisassembly(
 
 std::string
 MemoryEx64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -190,7 +190,7 @@ MemoryEx64::generateDisassembly(
 
 std::string
 MemoryLiteral64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -201,7 +201,7 @@ MemoryLiteral64::generateDisassembly(
 
 std::string
 MemoryAtomicPair64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 54b8869ef0..82635a1273 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -61,7 +61,7 @@ class SysDC64 : public MiscRegOp64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MightBeMicro64 : public ArmStaticInst
@@ -143,7 +143,7 @@ class MemoryImm64 : public Memory64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MemoryDImm64 : public MemoryImm64
@@ -159,7 +159,7 @@ class MemoryDImm64 : public MemoryImm64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MemoryDImmEx64 : public MemoryDImm64
@@ -175,7 +175,7 @@ class MemoryDImmEx64 : public MemoryDImm64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MemoryPreIndex64 : public MemoryImm64
@@ -188,7 +188,7 @@ class MemoryPreIndex64 : public MemoryImm64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MemoryPostIndex64 : public MemoryImm64
@@ -201,7 +201,7 @@ class MemoryPostIndex64 : public MemoryImm64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MemoryReg64 : public Memory64
@@ -220,7 +220,7 @@ class MemoryReg64 : public Memory64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MemoryRaw64 : public Memory64
@@ -232,7 +232,7 @@ class MemoryRaw64 : public Memory64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MemoryEx64 : public Memory64
@@ -247,7 +247,7 @@ class MemoryEx64 : public Memory64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MemoryLiteral64 : public Memory64
@@ -261,7 +261,7 @@ class MemoryLiteral64 : public Memory64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MemoryAtomicPair64 : public Memory64
@@ -281,7 +281,7 @@ class MemoryAtomicPair64 : public Memory64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 }
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 9c79f60b30..37ad1e6a5d 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -43,7 +43,7 @@
 using namespace ArmISA;
 
 std::string
-MrsOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+MrsOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -126,7 +126,7 @@ MsrBase::printMsrBase(std::ostream &os) const
 }
 
 std::string
-MsrImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+MsrImmOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMsrBase(ss);
@@ -135,7 +135,7 @@ MsrImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-MsrRegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+MsrRegOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMsrBase(ss);
@@ -145,7 +145,7 @@ MsrRegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-MrrcOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+MrrcOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -158,7 +158,7 @@ MrrcOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-McrrOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+McrrOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -171,7 +171,7 @@ McrrOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-ImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+ImmOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -180,7 +180,7 @@ ImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-RegImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+RegImmOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -190,7 +190,7 @@ RegImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-RegRegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+RegRegOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -201,7 +201,7 @@ RegRegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+RegOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -211,7 +211,7 @@ RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
 std::string
 RegRegRegImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -226,7 +226,7 @@ RegRegRegImmOp::generateDisassembly(
 
 std::string
 RegRegRegRegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -242,7 +242,7 @@ RegRegRegRegOp::generateDisassembly(
 
 std::string
 RegRegRegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -256,7 +256,7 @@ RegRegRegOp::generateDisassembly(
 
 std::string
 RegRegImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -269,7 +269,7 @@ RegRegImmOp::generateDisassembly(
 
 std::string
 MiscRegRegImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -281,7 +281,7 @@ MiscRegRegImmOp::generateDisassembly(
 
 std::string
 RegMiscRegImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -293,7 +293,7 @@ RegMiscRegImmOp::generateDisassembly(
 
 std::string
 RegImmImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -304,7 +304,7 @@ RegImmImmOp::generateDisassembly(
 
 std::string
 RegRegImmImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -317,7 +317,7 @@ RegRegImmImmOp::generateDisassembly(
 
 std::string
 RegImmRegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -329,7 +329,7 @@ RegImmRegOp::generateDisassembly(
 
 std::string
 RegImmRegShiftOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -342,7 +342,7 @@ RegImmRegShiftOp::generateDisassembly(
 
 std::string
 UnknownOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     return csprintf("%-10s (inst %#08x)", "unknown", encoding());
 }
@@ -371,7 +371,7 @@ McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
 
 std::string
 McrMrcMiscInst::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     return csprintf("%-10s (pipe flush)", mnemonic);
 }
@@ -398,7 +398,7 @@ McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const
 
 std::string
 McrMrcImplDefined::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     return csprintf("%-10s (implementation defined)", mnemonic);
 }
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index cfd73b1717..3fd24eaeae 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -51,7 +51,7 @@ class MrsOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MsrBase : public ArmISA::PredOp
@@ -78,7 +78,7 @@ class MsrImmOp : public MsrBase
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MsrRegOp : public MsrBase
@@ -92,7 +92,7 @@ class MsrRegOp : public MsrBase
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MrrcOp : public ArmISA::PredOp
@@ -111,7 +111,7 @@ class MrrcOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class McrrOp : public ArmISA::PredOp
@@ -130,7 +130,7 @@ class McrrOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class ImmOp : public ArmISA::PredOp
@@ -144,7 +144,7 @@ class ImmOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegImmOp : public ArmISA::PredOp
@@ -159,7 +159,7 @@ class RegImmOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegRegOp : public ArmISA::PredOp
@@ -175,7 +175,7 @@ class RegRegOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegOp : public ArmISA::PredOp
@@ -189,7 +189,7 @@ class RegOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegImmRegOp : public ArmISA::PredOp
@@ -207,7 +207,7 @@ class RegImmRegOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegRegRegImmOp : public ArmISA::PredOp
@@ -227,7 +227,7 @@ class RegRegRegImmOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegRegRegRegOp : public ArmISA::PredOp
@@ -247,7 +247,7 @@ class RegRegRegRegOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegRegRegOp : public ArmISA::PredOp
@@ -265,7 +265,7 @@ class RegRegRegOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegRegImmOp : public ArmISA::PredOp
@@ -283,7 +283,7 @@ class RegRegImmOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MiscRegRegImmOp : public ArmISA::PredOp
@@ -301,7 +301,7 @@ class MiscRegRegImmOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegMiscRegImmOp : public ArmISA::PredOp
@@ -319,7 +319,7 @@ class RegMiscRegImmOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegImmImmOp : public ArmISA::PredOp
@@ -337,7 +337,7 @@ class RegImmImmOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegRegImmImmOp : public ArmISA::PredOp
@@ -356,7 +356,7 @@ class RegRegImmImmOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegImmRegShiftOp : public ArmISA::PredOp
@@ -378,7 +378,7 @@ class RegImmRegShiftOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class UnknownOp : public ArmISA::PredOp
@@ -391,7 +391,7 @@ class UnknownOp : public ArmISA::PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -414,7 +414,7 @@ class McrMrcMiscInst : public ArmISA::ArmStaticInst
                   Trace::InstRecord *traceData) const override;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
 };
 
@@ -432,7 +432,7 @@ class McrMrcImplDefined : public McrMrcMiscInst
                   Trace::InstRecord *traceData) const override;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
 };
 
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 40126cf228..fa434132ed 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -41,7 +41,7 @@
 using namespace ArmISA;
 
 std::string
-ImmOp64::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+ImmOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -51,7 +51,7 @@ ImmOp64::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
 std::string
 RegRegImmImmOp64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -64,7 +64,7 @@ RegRegImmImmOp64::generateDisassembly(
 
 std::string
 RegRegRegImmOp64::generateDisassembly(
-    Addr pc, const Loader::SymbolTable *symtab) const
+    Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -79,7 +79,7 @@ RegRegRegImmOp64::generateDisassembly(
 
 std::string
 UnknownOp64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     return csprintf("%-10s (inst %#08x)", "unknown", encoding());
 }
@@ -808,7 +808,7 @@ MiscRegImmOp64::miscRegImm() const
 
 std::string
 MiscRegImmOp64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -820,7 +820,7 @@ MiscRegImmOp64::generateDisassembly(
 
 std::string
 MiscRegRegImmOp64::generateDisassembly(
-    Addr pc, const Loader::SymbolTable *symtab) const
+    Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -832,7 +832,7 @@ MiscRegRegImmOp64::generateDisassembly(
 
 std::string
 RegMiscRegImmOp64::generateDisassembly(
-    Addr pc, const Loader::SymbolTable *symtab) const
+    Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -867,14 +867,14 @@ MiscRegImplDefined64::execute(ExecContext *xc,
 
 std::string
 MiscRegImplDefined64::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     return csprintf("%-10s (implementation defined)", fullMnemonic.c_str());
 }
 
 std::string
 RegNone::generateDisassembly(
-    Addr pc, const Loader::SymbolTable *symtab) const
+    Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index a07788236c..cc4425db56 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -51,7 +51,7 @@ class ImmOp64 : public ArmISA::ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegRegImmImmOp64 : public ArmISA::ArmStaticInst
@@ -71,7 +71,7 @@ class RegRegImmImmOp64 : public ArmISA::ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegRegRegImmOp64 : public ArmISA::ArmStaticInst
@@ -91,7 +91,7 @@ class RegRegRegImmOp64 : public ArmISA::ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class UnknownOp64 : public ArmISA::ArmStaticInst
@@ -104,7 +104,7 @@ class UnknownOp64 : public ArmISA::ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -167,7 +167,7 @@ class MiscRegImmOp64 : public MiscRegOp64
     RegVal miscRegImm() const;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MiscRegRegImmOp64 : public MiscRegOp64
@@ -185,7 +185,7 @@ class MiscRegRegImmOp64 : public MiscRegOp64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegMiscRegImmOp64 : public MiscRegOp64
@@ -203,7 +203,7 @@ class RegMiscRegImmOp64 : public MiscRegOp64
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class MiscRegImplDefined64 : public MiscRegOp64
@@ -231,7 +231,7 @@ class MiscRegImplDefined64 : public MiscRegOp64
                   Trace::InstRecord *traceData) const override;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class RegNone : public ArmISA::ArmStaticInst
@@ -246,7 +246,7 @@ class RegNone : public ArmISA::ArmStaticInst
     {}
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const;
+        Addr pc, const loader::SymbolTable *symtab) const;
 };
 
 #endif
diff --git a/src/arch/arm/insts/pred_inst.cc b/src/arch/arm/insts/pred_inst.cc
index 9415c141a2..c385e8c3c5 100644
--- a/src/arch/arm/insts/pred_inst.cc
+++ b/src/arch/arm/insts/pred_inst.cc
@@ -44,7 +44,7 @@ namespace ArmISA
 {
 std::string
 PredIntOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     unsigned rotate = machInst.rotate * 2;
@@ -62,7 +62,7 @@ PredIntOp::generateDisassembly(
 
 std::string
 PredImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printDataInst(ss, true, machInst.opcode4 == 0, machInst.sField,
@@ -77,7 +77,7 @@ PredImmOp::generateDisassembly(
 
 std::string
 DataImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
@@ -87,7 +87,7 @@ DataImmOp::generateDisassembly(
 
 std::string
 DataRegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
@@ -97,7 +97,7 @@ DataRegOp::generateDisassembly(
 
 std::string
 DataRegRegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printDataInst(ss, false, false, /*XXX not really s*/ false, dest, op1,
@@ -107,7 +107,7 @@ DataRegRegOp::generateDisassembly(
 
 std::string
 PredMacroOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh
index ca5f3f1d20..ebcca62982 100644
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -251,7 +251,7 @@ class PredImmOp : public PredOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -272,7 +272,7 @@ class PredIntOp : public PredOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataImmOp : public PredOp
@@ -291,7 +291,7 @@ class DataImmOp : public PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataRegOp : public PredOp
@@ -310,7 +310,7 @@ class DataRegOp : public PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class DataRegRegOp : public PredOp
@@ -328,7 +328,7 @@ class DataRegRegOp : public PredOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -372,7 +372,7 @@ class PredMacroOp : public PredOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc
index ff73dbd090..51312e1e69 100644
--- a/src/arch/arm/insts/pseudo.cc
+++ b/src/arch/arm/insts/pseudo.cc
@@ -100,7 +100,7 @@ DecoderFaultInst::faultName() const
 
 std::string
 DecoderFaultInst::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     return csprintf("gem5fault %s", faultName());
 }
@@ -135,7 +135,7 @@ FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
 
 std::string
 FailUnimplemented::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     return csprintf("%-10s (unimplemented)",
                     fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
@@ -177,7 +177,7 @@ WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
 
 std::string
 WarnUnimplemented::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     return csprintf("%-10s (unimplemented)",
                     fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
diff --git a/src/arch/arm/insts/pseudo.hh b/src/arch/arm/insts/pseudo.hh
index 964faf7366..b4eccc07f2 100644
--- a/src/arch/arm/insts/pseudo.hh
+++ b/src/arch/arm/insts/pseudo.hh
@@ -57,7 +57,7 @@ class DecoderFaultInst : public ArmISA::ArmStaticInst
                   Trace::InstRecord *traceData) const override;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -83,7 +83,7 @@ class FailUnimplemented : public ArmISA::ArmStaticInst
                   Trace::InstRecord *traceData) const override;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -113,7 +113,7 @@ class WarnUnimplemented : public ArmISA::ArmStaticInst
                   Trace::InstRecord *traceData) const override;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index e55894cc8a..3489b25bdb 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -393,7 +393,7 @@ ArmStaticInst::printMnemonic(std::ostream &os,
 
 void
 ArmStaticInst::printTarget(std::ostream &os, Addr target,
-                           const Loader::SymbolTable *symtab) const
+                           const loader::SymbolTable *symtab) const
 {
     if (symtab) {
         auto it = symtab->findNearest(target);
@@ -475,7 +475,7 @@ ArmStaticInst::printCondition(std::ostream &os,
 
 void
 ArmStaticInst::printMemSymbol(std::ostream &os,
-                              const Loader::SymbolTable *symtab,
+                              const loader::SymbolTable *symtab,
                               const std::string &prefix,
                               const Addr addr,
                               const std::string &suffix) const
@@ -621,7 +621,7 @@ ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
 
 std::string
 ArmStaticInst::generateDisassembly(Addr pc,
-                                   const Loader::SymbolTable *symtab) const
+                                   const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 6c0c2731c9..b7dbf0dd30 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -173,10 +173,10 @@ class ArmStaticInst : public StaticInst
                        bool withCond64 = false,
                        ConditionCode cond64 = COND_UC) const;
     void printTarget(std::ostream &os, Addr target,
-                     const Loader::SymbolTable *symtab) const;
+                     const loader::SymbolTable *symtab) const;
     void printCondition(std::ostream &os, unsigned code,
                         bool noImplicit=false) const;
-    void printMemSymbol(std::ostream &os, const Loader::SymbolTable *symtab,
+    void printMemSymbol(std::ostream &os, const loader::SymbolTable *symtab,
                         const std::string &prefix, const Addr addr,
                         const std::string &suffix) const;
     void printShiftOperand(std::ostream &os, IntRegIndex rm,
@@ -210,7 +210,7 @@ class ArmStaticInst : public StaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
     static void
     activateBreakpoint(ThreadContext *tc)
diff --git a/src/arch/arm/insts/sve.cc b/src/arch/arm/insts/sve.cc
index 0b8258ccf5..ee9edd5f27 100644
--- a/src/arch/arm/insts/sve.cc
+++ b/src/arch/arm/insts/sve.cc
@@ -56,7 +56,7 @@ svePredTypeToStr(SvePredType pt)
 
 std::string
 SvePredCountPredOp::generateDisassembly(Addr pc,
-        const Loader::SymbolTable *symtab) const
+        const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -70,7 +70,7 @@ SvePredCountPredOp::generateDisassembly(Addr pc,
 
 std::string
 SvePredCountOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -91,7 +91,7 @@ SvePredCountOp::generateDisassembly(
 
 std::string
 SveIndexIIOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -102,7 +102,7 @@ SveIndexIIOp::generateDisassembly(
 
 std::string
 SveIndexIROp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -114,7 +114,7 @@ SveIndexIROp::generateDisassembly(
 
 std::string
 SveIndexRIOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -127,7 +127,7 @@ SveIndexRIOp::generateDisassembly(
 
 std::string
 SveIndexRROp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -141,7 +141,7 @@ SveIndexRROp::generateDisassembly(
 
 std::string
 SveWhileOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -160,7 +160,7 @@ SveWhileOp::generateDisassembly(
 
 std::string
 SveCompTermOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -172,7 +172,7 @@ SveCompTermOp::generateDisassembly(
 
 std::string
 SveUnaryPredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -186,7 +186,7 @@ SveUnaryPredOp::generateDisassembly(
 
 std::string
 SveUnaryUnpredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -198,7 +198,7 @@ SveUnaryUnpredOp::generateDisassembly(
 
 std::string
 SveUnaryWideImmUnpredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -210,7 +210,7 @@ SveUnaryWideImmUnpredOp::generateDisassembly(
 
 std::string
 SveUnaryWideImmPredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -225,7 +225,7 @@ SveUnaryWideImmPredOp::generateDisassembly(
 
 std::string
 SveBinImmUnpredConstrOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -239,7 +239,7 @@ SveBinImmUnpredConstrOp::generateDisassembly(
 
 std::string
 SveBinImmPredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -255,7 +255,7 @@ SveBinImmPredOp::generateDisassembly(
 
 std::string
 SveBinWideImmUnpredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -269,7 +269,7 @@ SveBinWideImmUnpredOp::generateDisassembly(
 
 std::string
 SveBinDestrPredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -285,7 +285,7 @@ SveBinDestrPredOp::generateDisassembly(
 
 std::string
 SveBinConstrPredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -304,7 +304,7 @@ SveBinConstrPredOp::generateDisassembly(
 
 std::string
 SveBinUnpredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -318,7 +318,7 @@ SveBinUnpredOp::generateDisassembly(
 
 std::string
 SveBinIdxUnpredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -335,7 +335,7 @@ SveBinIdxUnpredOp::generateDisassembly(
 
 std::string
 SvePredLogicalOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -355,7 +355,7 @@ SvePredLogicalOp::generateDisassembly(
 
 std::string
 SvePredBinPermOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -368,7 +368,7 @@ SvePredBinPermOp::generateDisassembly(
 }
 
 std::string
-SveCmpOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+SveCmpOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -384,7 +384,7 @@ SveCmpOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
 std::string
 SveCmpImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -400,7 +400,7 @@ SveCmpImmOp::generateDisassembly(
 
 std::string
 SveTerPredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -416,7 +416,7 @@ SveTerPredOp::generateDisassembly(
 
 std::string
 SveTerImmUnpredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -432,7 +432,7 @@ SveTerImmUnpredOp::generateDisassembly(
 
 std::string
 SveReducOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -446,7 +446,7 @@ SveReducOp::generateDisassembly(
 
 std::string
 SveOrdReducOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -462,7 +462,7 @@ SveOrdReducOp::generateDisassembly(
 
 std::string
 SvePtrueOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -476,7 +476,7 @@ SvePtrueOp::generateDisassembly(
 
 std::string
 SveIntCmpOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -496,7 +496,7 @@ SveIntCmpOp::generateDisassembly(
 
 std::string
 SveIntCmpImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -511,7 +511,7 @@ SveIntCmpImmOp::generateDisassembly(
 }
 
 std::string
-SveAdrOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+SveAdrOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -536,7 +536,7 @@ SveAdrOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
 std::string
 SveElemCountOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     static const char suffix[9] =
         {'\0', 'b', 'h', '\0', 'w', '\0', '\0', '\0', 'd'};
@@ -564,7 +564,7 @@ SveElemCountOp::generateDisassembly(
 
 std::string
 SvePartBrkOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -578,7 +578,7 @@ SvePartBrkOp::generateDisassembly(
 
 std::string
 SvePartBrkPropOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -594,7 +594,7 @@ SvePartBrkPropOp::generateDisassembly(
 
 std::string
 SveSelectOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -620,7 +620,7 @@ SveSelectOp::generateDisassembly(
 
 std::string
 SveUnaryPredPredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -633,7 +633,7 @@ SveUnaryPredPredOp::generateDisassembly(
 }
 
 std::string
-SveTblOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+SveTblOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -647,7 +647,7 @@ SveTblOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
 std::string
 SveUnpackOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -659,7 +659,7 @@ SveUnpackOp::generateDisassembly(
 
 std::string
 SvePredTestOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -671,7 +671,7 @@ SvePredTestOp::generateDisassembly(
 
 std::string
 SvePredUnaryWImplicitSrcOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -681,7 +681,7 @@ SvePredUnaryWImplicitSrcOp::generateDisassembly(
 
 std::string
 SvePredUnaryWImplicitSrcPredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -694,7 +694,7 @@ SvePredUnaryWImplicitSrcPredOp::generateDisassembly(
 
 std::string
 SvePredUnaryWImplicitDstOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -704,7 +704,7 @@ SvePredUnaryWImplicitDstOp::generateDisassembly(
 
 std::string
 SveWImplicitSrcDstOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -713,7 +713,7 @@ SveWImplicitSrcDstOp::generateDisassembly(
 
 std::string
 SveBinImmUnpredDestrOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -729,7 +729,7 @@ SveBinImmUnpredDestrOp::generateDisassembly(
 
 std::string
 SveBinImmIdxUnpredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -744,7 +744,7 @@ SveBinImmIdxUnpredOp::generateDisassembly(
 
 std::string
 SveUnarySca2VecUnpredOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -760,7 +760,7 @@ SveUnarySca2VecUnpredOp::generateDisassembly(
 
 std::string
 SveDotProdIdxOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -777,7 +777,7 @@ SveDotProdIdxOp::generateDisassembly(
 
 std::string
 SveDotProdOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -791,7 +791,7 @@ SveDotProdOp::generateDisassembly(
 
 std::string
 SveComplexOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -811,7 +811,7 @@ SveComplexOp::generateDisassembly(
 
 std::string
 SveComplexIdxOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
diff --git a/src/arch/arm/insts/sve.hh b/src/arch/arm/insts/sve.hh
index 5faab8d0c6..22f53d9572 100644
--- a/src/arch/arm/insts/sve.hh
+++ b/src/arch/arm/insts/sve.hh
@@ -68,7 +68,7 @@ class SveIndexIIOp : public ArmStaticInst
         dest(_dest), imm1(_imm1), imm2(_imm2)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class SveIndexIROp : public ArmStaticInst
@@ -85,7 +85,7 @@ class SveIndexIROp : public ArmStaticInst
           dest(_dest), imm1(_imm1), op2(_op2)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class SveIndexRIOp : public ArmStaticInst
@@ -102,7 +102,7 @@ class SveIndexRIOp : public ArmStaticInst
         dest(_dest), op1(_op1), imm2(_imm2)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class SveIndexRROp : public ArmStaticInst
@@ -119,7 +119,7 @@ class SveIndexRROp : public ArmStaticInst
         dest(_dest), op1(_op1), op2(_op2)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // Predicate count SVE instruction.
@@ -139,7 +139,7 @@ class SvePredCountOp : public ArmStaticInst
         srcIs32b(_srcIs32b), destIsVec(_destIsVec)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // Predicate count SVE instruction (predicated).
@@ -157,7 +157,7 @@ class SvePredCountPredOp : public ArmStaticInst
         dest(_dest), op1(_op1), gp(_gp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// While predicate generation SVE instruction.
@@ -174,7 +174,7 @@ class SveWhileOp : public ArmStaticInst
         dest(_dest), op1(_op1), op2(_op2), srcIs32b(_srcIs32b)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Compare and terminate loop SVE instruction.
@@ -189,7 +189,7 @@ class SveCompTermOp : public ArmStaticInst
         op1(_op1), op2(_op2)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Unary, constructive, predicated (merging) SVE instruction.
@@ -205,7 +205,7 @@ class SveUnaryPredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Unary, constructive, unpredicated SVE instruction.
@@ -221,7 +221,7 @@ class SveUnaryUnpredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Unary with wide immediate, constructive, unpredicated SVE instruction.
@@ -239,7 +239,7 @@ class SveUnaryWideImmUnpredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Unary with wide immediate, constructive, predicated SVE instruction.
@@ -260,7 +260,7 @@ class SveUnaryWideImmPredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Binary with immediate, destructive, unpredicated SVE instruction.
@@ -278,7 +278,7 @@ class SveBinImmUnpredConstrOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Binary with immediate, destructive, predicated (merging) SVE instruction.
@@ -295,7 +295,7 @@ class SveBinImmPredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Binary with wide immediate, destructive, unpredicated SVE instruction.
@@ -313,7 +313,7 @@ class SveBinWideImmUnpredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Binary, destructive, predicated (merging) SVE instruction.
@@ -330,7 +330,7 @@ class SveBinDestrPredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Binary, constructive, predicated SVE instruction.
@@ -349,7 +349,7 @@ class SveBinConstrPredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Binary, unpredicated SVE instruction with indexed operand
@@ -365,7 +365,7 @@ class SveBinUnpredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Binary, unpredicated SVE instruction
@@ -383,7 +383,7 @@ class SveBinIdxUnpredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Predicate logical instruction.
@@ -401,7 +401,7 @@ class SvePredLogicalOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Predicate binary permute instruction.
@@ -418,7 +418,7 @@ class SvePredBinPermOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE compare instructions, predicated (zeroing).
@@ -435,7 +435,7 @@ class SveCmpOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE compare-with-immediate instructions, predicated (zeroing).
@@ -453,7 +453,7 @@ class SveCmpImmOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Ternary, destructive, predicated (merging) SVE instruction.
@@ -470,7 +470,7 @@ class SveTerPredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Ternary with immediate, destructive, unpredicated SVE instruction.
@@ -488,7 +488,7 @@ class SveTerImmUnpredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE reductions.
@@ -504,7 +504,7 @@ class SveReducOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE ordered reductions.
@@ -520,7 +520,7 @@ class SveOrdReducOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// PTRUE, PTRUES.
@@ -537,7 +537,7 @@ class SvePtrueOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Integer compare SVE instruction.
@@ -556,7 +556,7 @@ class SveIntCmpOp : public ArmStaticInst
         dest(_dest), op1(_op1), op2(_op2), gp(_gp), op2IsWide(_op2IsWide)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Integer compare with immediate SVE instruction.
@@ -575,7 +575,7 @@ class SveIntCmpImmOp : public ArmStaticInst
         dest(_dest), op1(_op1), imm(_imm), gp(_gp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// ADR.
@@ -603,7 +603,7 @@ class SveAdrOp : public ArmStaticInst
         offsetFormat(_offsetFormat)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Element count SVE instruction.
@@ -625,7 +625,7 @@ class SveElemCountOp : public ArmStaticInst
         dstIs32b(_dstIs32b)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Partition break SVE instruction.
@@ -644,7 +644,7 @@ class SvePartBrkOp : public ArmStaticInst
         dest(_dest), gp(_gp), op1(_op1), isMerging(_isMerging)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Partition break with propagation SVE instruction.
@@ -663,7 +663,7 @@ class SvePartBrkPropOp : public ArmStaticInst
         dest(_dest), op1(_op1), op2(_op2), gp(_gp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Scalar element select SVE instruction.
@@ -688,7 +688,7 @@ class SveSelectOp : public ArmStaticInst
         scalar(_scalar), simdFp(_simdFp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE unary operation on predicate (predicated)
@@ -706,7 +706,7 @@ class SveUnaryPredPredOp : public ArmStaticInst
         dest(_dest), op1(_op1), gp(_gp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE table lookup/permute using vector of element indices (TBL)
@@ -723,7 +723,7 @@ class SveTblOp : public ArmStaticInst
         dest(_dest), op1(_op1), op2(_op2)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE unpack and widen predicate
@@ -739,7 +739,7 @@ class SveUnpackOp : public ArmStaticInst
         dest(_dest), op1(_op1)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE predicate test
@@ -755,7 +755,7 @@ class SvePredTestOp : public ArmStaticInst
         op1(_op1), gp(_gp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE unary predicate instructions with implicit source operand
@@ -770,7 +770,7 @@ class SvePredUnaryWImplicitSrcOp : public ArmStaticInst
         dest(_dest)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE unary predicate instructions, predicated, with implicit source operand
@@ -787,7 +787,7 @@ class SvePredUnaryWImplicitSrcPredOp : public ArmStaticInst
         dest(_dest), gp(_gp)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE unary predicate instructions with implicit destination operand
@@ -802,7 +802,7 @@ class SvePredUnaryWImplicitDstOp : public ArmStaticInst
         op1(_op1)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE unary predicate instructions with implicit destination operand
@@ -814,7 +814,7 @@ class SveWImplicitSrcDstOp : public ArmStaticInst
         ArmStaticInst(mnem, _machInst, __opClass)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE vector - immediate binary operation
@@ -832,7 +832,7 @@ class SveBinImmUnpredDestrOp : public ArmStaticInst
         dest(_dest), op1(_op1), imm(_imm)
     {}
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Binary with immediate index, destructive, unpredicated SVE instruction.
@@ -850,7 +850,7 @@ class SveBinImmIdxUnpredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// Unary unpredicated scalar to vector instruction
@@ -868,7 +868,7 @@ class SveUnarySca2VecUnpredOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE dot product instruction (indexed)
@@ -888,7 +888,7 @@ class SveDotProdIdxOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE dot product instruction (vectors)
@@ -907,7 +907,7 @@ class SveDotProdOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE Complex Instructions (vectors)
@@ -926,7 +926,7 @@ class SveComplexOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /// SVE Complex Instructions (indexed)
@@ -945,7 +945,7 @@ class SveComplexIdxOp : public ArmStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 
diff --git a/src/arch/arm/insts/sve_macromem.hh b/src/arch/arm/insts/sve_macromem.hh
index c38c938d08..eb97e0468c 100644
--- a/src/arch/arm/insts/sve_macromem.hh
+++ b/src/arch/arm/insts/sve_macromem.hh
@@ -94,7 +94,7 @@ class SveLdStructSS : public PredMacroOp
 
     std::string
     generateDisassembly(Addr pc,
-                        const Loader::SymbolTable *symtab) const override
+                        const loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         printMnemonic(ss, "", false);
@@ -167,7 +167,7 @@ class SveStStructSS : public PredMacroOp
 
     std::string
     generateDisassembly(Addr pc,
-                        const Loader::SymbolTable *symtab) const override
+                        const loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         printMnemonic(ss, "", false);
@@ -240,7 +240,7 @@ class SveLdStructSI : public PredMacroOp
 
     std::string
     generateDisassembly(Addr pc,
-                        const Loader::SymbolTable *symtab) const override
+                        const loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         printMnemonic(ss, "", false);
@@ -314,7 +314,7 @@ class SveStStructSI : public PredMacroOp
 
     std::string
     generateDisassembly(Addr pc,
-                        const Loader::SymbolTable *symtab) const override
+                        const loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
         printMnemonic(ss, "", false);
@@ -414,7 +414,7 @@ class SveIndexedMemVI : public PredMacroOp
 
     std::string
     generateDisassembly(Addr pc,
-                        const Loader::SymbolTable *symtab) const override
+                        const loader::SymbolTable *symtab) const override
     {
         // TODO: add suffix to transfer and base registers
         std::stringstream ss;
@@ -519,7 +519,7 @@ class SveIndexedMemSV : public PredMacroOp
 
     std::string
     generateDisassembly(Addr pc,
-                        const Loader::SymbolTable *symtab) const override
+                        const loader::SymbolTable *symtab) const override
     {
         // TODO: add suffix to transfer and base registers
         std::stringstream ss;
diff --git a/src/arch/arm/insts/sve_mem.cc b/src/arch/arm/insts/sve_mem.cc
index 7bdbb7241f..4d3c3370ee 100644
--- a/src/arch/arm/insts/sve_mem.cc
+++ b/src/arch/arm/insts/sve_mem.cc
@@ -42,7 +42,7 @@ namespace ArmISA
 
 std::string
 SveMemVecFillSpill::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -58,7 +58,7 @@ SveMemVecFillSpill::generateDisassembly(
 
 std::string
 SveMemPredFillSpill::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -74,7 +74,7 @@ SveMemPredFillSpill::generateDisassembly(
 
 std::string
 SveContigMemSS::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     // TODO: add suffix to transfer register and scaling factor (LSL #<x>)
     std::stringstream ss;
@@ -94,7 +94,7 @@ SveContigMemSS::generateDisassembly(
 
 std::string
 SveContigMemSI::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     // TODO: add suffix to transfer register
     std::stringstream ss;
diff --git a/src/arch/arm/insts/sve_mem.hh b/src/arch/arm/insts/sve_mem.hh
index ebf1428a96..2bf9b87a28 100644
--- a/src/arch/arm/insts/sve_mem.hh
+++ b/src/arch/arm/insts/sve_mem.hh
@@ -67,7 +67,7 @@ class SveMemVecFillSpill : public ArmStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class SveMemPredFillSpill : public ArmStaticInst
@@ -93,7 +93,7 @@ class SveMemPredFillSpill : public ArmStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class SveContigMemSS : public ArmStaticInst
@@ -120,7 +120,7 @@ class SveContigMemSS : public ArmStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class SveContigMemSI : public ArmStaticInst
@@ -147,7 +147,7 @@ class SveContigMemSI : public ArmStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 }  // namespace ArmISA
diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index 85ffd6dfb7..b7432dfa5b 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -46,7 +46,7 @@ namespace ArmISAInst {
 
 std::string
 TmeImmOp64::generateDisassembly(
-    Addr pc, const Loader::SymbolTable *symtab) const
+    Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -56,7 +56,7 @@ TmeImmOp64::generateDisassembly(
 
 std::string
 TmeRegNone64::generateDisassembly(
-    Addr pc, const Loader::SymbolTable *symtab) const
+    Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -66,7 +66,7 @@ TmeRegNone64::generateDisassembly(
 
 std::string
 MicroTmeBasic64::generateDisassembly(
-    Addr pc, const Loader::SymbolTable *symtab) const
+    Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
diff --git a/src/arch/arm/insts/tme64.hh b/src/arch/arm/insts/tme64.hh
index 0a1e02cfda..40cb320a48 100644
--- a/src/arch/arm/insts/tme64.hh
+++ b/src/arch/arm/insts/tme64.hh
@@ -62,7 +62,7 @@ class MicroTmeBasic64 : public MicroTmeOp
     {}
 
     std::string generateDisassembly(Addr pc,
-                                    const Loader::SymbolTable *symtab) const;
+                                    const loader::SymbolTable *symtab) const;
 };
 
 class TmeImmOp64 : public ArmISA::ArmStaticInst
@@ -77,7 +77,7 @@ class TmeImmOp64 : public ArmISA::ArmStaticInst
     {}
 
     std::string generateDisassembly(Addr pc,
-                                    const Loader::SymbolTable *symtab) const;
+                                    const loader::SymbolTable *symtab) const;
 };
 
 class TmeRegNone64 : public ArmISA::ArmStaticInst
@@ -92,7 +92,7 @@ class TmeRegNone64 : public ArmISA::ArmStaticInst
     {}
 
     std::string generateDisassembly(Addr pc,
-                                    const Loader::SymbolTable *symtab) const;
+                                    const loader::SymbolTable *symtab) const;
 };
 
 class Tstart64 : public TmeRegNone64
diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc
index 4729039bcf..e0c404be06 100644
--- a/src/arch/arm/insts/vfp.cc
+++ b/src/arch/arm/insts/vfp.cc
@@ -47,7 +47,7 @@ using namespace ArmISA;
 
 std::string
 FpCondCompRegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -62,7 +62,7 @@ FpCondCompRegOp::generateDisassembly(
 
 std::string
 FpCondSelOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss, "", false);
@@ -78,7 +78,7 @@ FpCondSelOp::generateDisassembly(
 
 std::string
 FpRegRegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -90,7 +90,7 @@ FpRegRegOp::generateDisassembly(
 
 std::string
 FpRegImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -101,7 +101,7 @@ FpRegImmOp::generateDisassembly(
 
 std::string
 FpRegRegImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -114,7 +114,7 @@ FpRegRegImmOp::generateDisassembly(
 
 std::string
 FpRegRegRegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -128,7 +128,7 @@ FpRegRegRegOp::generateDisassembly(
 
 std::string
 FpRegRegRegCondOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab)
+        Addr pc, const loader::SymbolTable *symtab)
     const
 {
     std::stringstream ss;
@@ -144,7 +144,7 @@ FpRegRegRegCondOp::generateDisassembly(
 
 std::string
 FpRegRegRegRegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
@@ -160,7 +160,7 @@ FpRegRegRegRegOp::generateDisassembly(
 
 std::string
 FpRegRegRegImmOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     printMnemonic(ss);
diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh
index 7685768b0a..40111c79f3 100644
--- a/src/arch/arm/insts/vfp.hh
+++ b/src/arch/arm/insts/vfp.hh
@@ -893,7 +893,7 @@ class FpCondCompRegOp : public FpOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class FpCondSelOp : public FpOp
@@ -910,7 +910,7 @@ class FpCondSelOp : public FpOp
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class FpRegRegOp : public FpOp
@@ -928,7 +928,7 @@ class FpRegRegOp : public FpOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class FpRegImmOp : public FpOp
@@ -946,7 +946,7 @@ class FpRegImmOp : public FpOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class FpRegRegImmOp : public FpOp
@@ -965,7 +965,7 @@ class FpRegRegImmOp : public FpOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class FpRegRegRegOp : public FpOp
@@ -984,7 +984,7 @@ class FpRegRegRegOp : public FpOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class FpRegRegRegCondOp : public FpOp
@@ -1006,7 +1006,7 @@ class FpRegRegRegCondOp : public FpOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class FpRegRegRegRegOp : public FpOp
@@ -1027,7 +1027,7 @@ class FpRegRegRegRegOp : public FpOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class FpRegRegRegImmOp : public FpOp
@@ -1049,7 +1049,7 @@ class FpRegRegRegImmOp : public FpOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 }
diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa
index a9788c49a2..c814157cfa 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -467,7 +467,7 @@ def template SveIndexedMemVIMicroopDeclare {{
 
         std::string
         generateDisassembly(Addr pc,
-                            const Loader::SymbolTable *symtab) const override
+                            const loader::SymbolTable *symtab) const override
         {
             // TODO: add suffix to transfer register
             std::stringstream ss;
@@ -555,7 +555,7 @@ def template SveIndexedMemSVMicroopDeclare {{
 
         std::string
         generateDisassembly(Addr pc,
-                            const Loader::SymbolTable *symtab) const override
+                            const loader::SymbolTable *symtab) const override
         {
             // TODO: add suffix to transfer and base registers
             std::stringstream ss;
@@ -790,7 +790,7 @@ def template SveFirstFaultWritebackMicroopDeclare {{
 
         std::string
         generateDisassembly(Addr pc,
-                            const Loader::SymbolTable *symtab) const override
+                            const loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
             ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
@@ -851,7 +851,7 @@ def template SveGatherLoadCpySrcVecMicroopDeclare {{
 
         std::string
         generateDisassembly(Addr pc,
-                            const Loader::SymbolTable *symtab) const override
+                            const loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
             ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
@@ -929,7 +929,7 @@ def template SveStructMemSIMicroopDeclare {{
 
         std::string
         generateDisassembly(Addr pc,
-                            const Loader::SymbolTable *symtab) const override
+                            const loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
             printMnemonic(ss, "", false);
@@ -1206,7 +1206,7 @@ def template SveStructMemSSMicroopDeclare {{
 
         std::string
         generateDisassembly(Addr pc,
-                            const Loader::SymbolTable *symtab) const override
+                            const loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
             printMnemonic(ss, "", false);
@@ -1275,7 +1275,7 @@ def template SveIntrlvMicroopDeclare {{
 
         std::string
         generateDisassembly(Addr pc,
-                            const Loader::SymbolTable *symtab) const override
+                            const loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
             ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
@@ -1316,7 +1316,7 @@ def template SveDeIntrlvMicroopDeclare {{
 
         std::string
         generateDisassembly(Addr pc,
-                            const Loader::SymbolTable *symtab) const override
+                            const loader::SymbolTable *symtab) const override
         {
             std::stringstream ss;
             ccprintf(ss, "%s", macroOp->disassemble(pc, symtab));
diff --git a/src/arch/arm/linux/fs_workload.cc b/src/arch/arm/linux/fs_workload.cc
index dc3071dd2f..fce4db08bf 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -77,7 +77,7 @@ FsLinux::initState()
     if (params().early_kernel_symbols) {
         auto phys_globals = kernelObj->symtab().globals()->mask(_loadAddrMask);
         kernelSymtab.insert(*phys_globals);
-        Loader::debugSymbolTable.insert(*phys_globals);
+        loader::debugSymbolTable.insert(*phys_globals);
     }
 
     // Setup boot data structure
@@ -93,7 +93,7 @@ FsLinux::initState()
         inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
                 params().dtb_addr);
 
-        auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);
+        auto *dtb_file = new loader::DtbFile(params().dtb_filename);
 
         if (!dtb_file->addBootCmdLine(
                     commandLine.c_str(), commandLine.size())) {
@@ -156,7 +156,7 @@ FsLinux::initState()
         delete[] boot_data;
     }
 
-    if (getArch() == Loader::Arm64) {
+    if (getArch() == loader::Arm64) {
         // We inform the bootloader of the kernel entry point. This was added
         // originally done because the entry offset changed in kernel v5.8.
         // Previously the bootloader just used a hardcoded address.
@@ -191,7 +191,7 @@ FsLinux::startup()
     FsWorkload::startup();
 
     if (enableContextSwitchStatsDump) {
-        if (getArch() == Loader::Arm64)
+        if (getArch() == loader::Arm64)
             dumpStats = addKernelFuncEvent<DumpStats64>("__switch_to");
         else
             dumpStats = addKernelFuncEvent<DumpStats>("__switch_to");
diff --git a/src/arch/arm/linux/process.hh b/src/arch/arm/linux/process.hh
index 92c5f015fb..bca537221b 100644
--- a/src/arch/arm/linux/process.hh
+++ b/src/arch/arm/linux/process.hh
@@ -50,7 +50,7 @@ class ArmLinuxProcess32 : public ArmProcess32
 {
   public:
     ArmLinuxProcess32(const ProcessParams &params,
-                      ::Loader::ObjectFile *objFile, ::Loader::Arch _arch) :
+                      loader::ObjectFile *objFile, loader::Arch _arch) :
         ArmProcess32(params, objFile, _arch)
     {}
 
@@ -65,7 +65,7 @@ class ArmLinuxProcess64 : public ArmProcess64
 {
   public:
     ArmLinuxProcess64(const ProcessParams &params,
-                      ::Loader::ObjectFile *objFile, ::Loader::Arch _arch) :
+                      loader::ObjectFile *objFile, loader::Arch _arch) :
         ArmProcess64(params, objFile, _arch)
     {}
 
diff --git a/src/arch/arm/linux/se_workload.cc b/src/arch/arm/linux/se_workload.cc
index 8080b2b6e1..4297e3cd6e 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -55,30 +55,30 @@ class LinuxLoader : public Process::Loader
 {
   public:
     Process *
-    load(const ProcessParams &params, ::Loader::ObjectFile *obj) override
+    load(const ProcessParams &params, loader::ObjectFile *obj) override
     {
         auto arch = obj->getArch();
         auto opsys = obj->getOpSys();
 
-        if (arch != ::Loader::Arm && arch != ::Loader::Thumb &&
-                arch != ::Loader::Arm64) {
+        if (arch != loader::Arm && arch != loader::Thumb &&
+                arch != loader::Arm64) {
             return nullptr;
         }
 
-        if (opsys == ::Loader::UnknownOpSys) {
+        if (opsys == loader::UnknownOpSys) {
             warn("Unknown operating system; assuming Linux.");
-            opsys = ::Loader::Linux;
+            opsys = loader::Linux;
         }
 
-        if (opsys == ::Loader::LinuxArmOABI) {
+        if (opsys == loader::LinuxArmOABI) {
             fatal("gem5 does not support ARM OABI binaries. Please recompile "
                     "with an EABI compiler.");
         }
 
-        if (opsys != ::Loader::Linux)
+        if (opsys != loader::Linux)
             return nullptr;
 
-        if (arch == ::Loader::Arm64)
+        if (arch == loader::Arm64)
             return new ArmLinuxProcess64(params, obj, arch);
         else
             return new ArmLinuxProcess32(params, obj, arch);
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index ec00e6bddf..3cca6614cb 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -60,7 +60,7 @@
 using namespace ArmISA;
 
 ArmProcess::ArmProcess(const ProcessParams &params,
-                       ::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
+                       loader::ObjectFile *objFile, loader::Arch _arch)
     : Process(params,
               new EmulationPageTable(params.name, params.pid, PageBytes),
               objFile),
@@ -70,7 +70,7 @@ ArmProcess::ArmProcess(const ProcessParams &params,
 }
 
 ArmProcess32::ArmProcess32(const ProcessParams &params,
-        ::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
+        loader::ObjectFile *objFile, loader::Arch _arch)
     : ArmProcess(params, objFile, _arch)
 {
     Addr brk_point = roundUp(image.maxAddr(), PageBytes);
@@ -85,8 +85,8 @@ ArmProcess32::ArmProcess32(const ProcessParams &params,
 }
 
 ArmProcess64::ArmProcess64(
-        const ProcessParams &params, ::Loader::ObjectFile *objFile,
-        ::Loader::Arch _arch)
+        const ProcessParams &params, loader::ObjectFile *objFile,
+        loader::Arch _arch)
     : ArmProcess(params, objFile, _arch)
 {
     Addr brk_point = roundUp(image.maxAddr(), PageBytes);
@@ -271,10 +271,10 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
 
     //Setup the auxilliary vectors. These will already have endian conversion.
     //Auxilliary vectors are loaded only for elf formatted executables.
-    auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile);
+    auto *elfObject = dynamic_cast<loader::ElfObject *>(objFile);
     if (elfObject) {
 
-        if (objFile->getOpSys() == ::Loader::Linux) {
+        if (objFile->getOpSys() == loader::Linux) {
             IntType features = armHwcap<IntType>();
 
             //Bits which describe the system hardware capabilities
@@ -465,9 +465,9 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
     }
 
     PCState pc;
-    pc.thumb(arch == ::Loader::Thumb);
+    pc.thumb(arch == loader::Thumb);
     pc.nextThumb(pc.thumb());
-    pc.aarch64(arch == ::Loader::Arm64);
+    pc.aarch64(arch == loader::Arm64);
     pc.nextAArch64(pc.aarch64());
     pc.set(getStartPC() & ~mask(1));
     tc->pcState(pc);
diff --git a/src/arch/arm/process.hh b/src/arch/arm/process.hh
index ff09b6df3d..bf57575f59 100644
--- a/src/arch/arm/process.hh
+++ b/src/arch/arm/process.hh
@@ -53,9 +53,9 @@
 class ArmProcess : public Process
 {
   protected:
-    ::Loader::Arch arch;
-    ArmProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile,
-               ::Loader::Arch _arch);
+    loader::Arch arch;
+    ArmProcess(const ProcessParams &params, loader::ObjectFile *objFile,
+               loader::Arch _arch);
     template<class IntType>
     void argsInit(int pageSize, ArmISA::IntRegIndex spIndex);
 
@@ -75,8 +75,8 @@ class ArmProcess : public Process
 class ArmProcess32 : public ArmProcess
 {
   public:
-    ArmProcess32(const ProcessParams &params, ::Loader::ObjectFile *objFile,
-                 ::Loader::Arch _arch);
+    ArmProcess32(const ProcessParams &params, loader::ObjectFile *objFile,
+                 loader::Arch _arch);
 
   protected:
     void initState() override;
@@ -88,8 +88,8 @@ class ArmProcess32 : public ArmProcess
 class ArmProcess64 : public ArmProcess
 {
   public:
-    ArmProcess64(const ProcessParams &params, ::Loader::ObjectFile *objFile,
-                 ::Loader::Arch _arch);
+    ArmProcess64(const ProcessParams &params, loader::ObjectFile *objFile,
+                 loader::Arch _arch);
 
   protected:
     void initState() override;
diff --git a/src/arch/arm/se_workload.hh b/src/arch/arm/se_workload.hh
index b14f949841..eac2ad6c43 100644
--- a/src/arch/arm/se_workload.hh
+++ b/src/arch/arm/se_workload.hh
@@ -50,7 +50,7 @@ class SEWorkload : public ::SEWorkload
         gdb = BaseRemoteGDB::build<RemoteGDB>(system);
     }
 
-    ::Loader::Arch getArch() const override { return ::Loader::Arm64; }
+    ::loader::Arch getArch() const override { return ::loader::Arm64; }
 
     using SyscallABI32 = RegABI32;
     using SyscallABI64 = RegABI64;
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index e8efb9cbbb..4d3a70b281 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -85,7 +85,7 @@ ArmSystem::ArmSystem(const Params &p)
                 workload->getEntry(), _resetAddr);
     }
 
-    bool wl_is_64 = (workload->getArch() == Loader::Arm64);
+    bool wl_is_64 = (workload->getArch() == loader::Arm64);
     if (wl_is_64 != _highestELIs64) {
         warn("Highest ARM exception-level set to AArch%d but the workload "
               "is for AArch%d. Assuming you wanted these to match.",
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index fa038a2061..bfc46c23c3 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -53,7 +53,7 @@ output header {{
         void printReg(std::ostream &os, RegId reg) const;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
 
       public:
         ExtMachInst machInst;
@@ -97,7 +97,7 @@ output decoder {{
 
     std::string
     MipsStaticInst::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
 
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 963d31d772..5cbc8a59c4 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -51,7 +51,7 @@ output header {{
         mutable Addr cachedPC;
 
         /// Cached symbol table pointer from last disassembly
-        mutable const Loader::SymbolTable *cachedSymtab;
+        mutable const loader::SymbolTable *cachedSymtab;
 
         /// Constructor
         PCDependentDisassembly(const char *mnem, MachInst _machInst,
@@ -62,7 +62,7 @@ output header {{
         }
 
         const std::string &
-        disassemble(Addr pc, const Loader::SymbolTable *symtab) const;
+        disassemble(Addr pc, const loader::SymbolTable *symtab) const;
     };
 
     /**
@@ -93,7 +93,7 @@ output header {{
         using StaticInst::branchTarget;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 
     /**
@@ -123,7 +123,7 @@ output header {{
         using StaticInst::branchTarget;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 }};
 
@@ -151,7 +151,7 @@ output decoder {{
 
     const std::string &
     PCDependentDisassembly::disassemble(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         if (!cachedDisassembly || pc != cachedPC || symtab != cachedSymtab) {
             if (!cachedDisassembly)
@@ -167,7 +167,7 @@ output decoder {{
 
     std::string
     Branch::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
 
@@ -189,7 +189,7 @@ output decoder {{
 
         Addr target = pc + 4 + disp;
 
-        Loader::SymbolTable::const_iterator it;
+        loader::SymbolTable::const_iterator it;
         if (symtab && (it = symtab->find(target)) != symtab->end())
             ss << it->name;
         else
@@ -199,7 +199,7 @@ output decoder {{
     }
 
     std::string
-    Jump::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    Jump::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
 
@@ -209,7 +209,7 @@ output decoder {{
             Addr npc = pc + 4;
             ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
         } else if (_numSrcRegs == 0) {
-            Loader::SymbolTable::const_iterator it;
+            loader::SymbolTable::const_iterator it;
             if (symtab && (it = symtab->find(disp)) != symtab->end())
                 ss << it->name;
             else
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index bb75ea8388..67efc864c7 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -39,7 +39,7 @@ output header {{
         using MipsStaticInst::MipsStaticInst;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
     class CP0TLB : public MipsStaticInst
     {
@@ -47,7 +47,7 @@ output header {{
         using MipsStaticInst::MipsStaticInst;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 
 
@@ -57,7 +57,7 @@ output header {{
         using MipsStaticInst::MipsStaticInst;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 }};
 
@@ -139,7 +139,7 @@ def template ControlTLBExecute {{
 output decoder {{
     std::string
     CP0Control::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
         ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
@@ -147,7 +147,7 @@ output decoder {{
     }
     std::string
     CP0TLB::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
         ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
@@ -155,7 +155,7 @@ output decoder {{
     }
     std::string
     CP1Control::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
         ccprintf(ss, "%-10s r%d, f%d", mnemonic, RT, FS);
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 368aa5589b..3f1e37eff2 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -49,14 +49,14 @@ output header {{
         using FPOp::FPOp;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string
     FPCompareOp::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
 
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 35bbef691d..f0306965d3 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -41,7 +41,7 @@ output header {{
         using MipsStaticInst::MipsStaticInst;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 
 
@@ -51,7 +51,7 @@ output header {{
         using IntOp::IntOp;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 
     class HiLoRsSelOp: public HiLoOp
@@ -60,7 +60,7 @@ output header {{
         using HiLoOp::HiLoOp;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 
     class HiLoRdSelOp: public HiLoOp
@@ -69,7 +69,7 @@ output header {{
         using HiLoOp::HiLoOp;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 
     class HiLoRdSelValOp: public HiLoOp
@@ -78,7 +78,7 @@ output header {{
         using HiLoOp::HiLoOp;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 
     class IntImmOp : public MipsStaticInst
@@ -100,7 +100,7 @@ output header {{
         }
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 
 }};
@@ -177,7 +177,7 @@ def template HiLoRdSelExecute {{
 output decoder {{
     std::string
     IntOp::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
 
@@ -207,7 +207,7 @@ output decoder {{
 
     std::string
     HiLoOp::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
 
@@ -228,7 +228,7 @@ output decoder {{
 
     std::string
     HiLoRsSelOp::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
 
@@ -245,7 +245,7 @@ output decoder {{
 
     std::string
     HiLoRdSelOp::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
 
@@ -262,7 +262,7 @@ output decoder {{
 
     std::string
     HiLoRdSelValOp::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
 
@@ -279,7 +279,7 @@ output decoder {{
 
     std::string
     IntImmOp::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
 
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 431f174102..402a96de27 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -51,7 +51,7 @@ output header {{
         }
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 
      /**
@@ -64,7 +64,7 @@ output header {{
         using Memory::Memory;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 }};
 
@@ -72,7 +72,7 @@ output header {{
 output decoder {{
     std::string
     Memory::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
                         flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
@@ -80,7 +80,7 @@ output decoder {{
 
     std::string
     MemoryNoDisp::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
                         flags[IsFloating] ? 'f' : 'r',
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 97cae4133b..5572e0602d 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -41,7 +41,7 @@ output header {{
         using MipsStaticInst::MipsStaticInst;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
 
         bool user_mode = false;
     };
@@ -59,7 +59,7 @@ output header {{
 
 output decoder {{
     std::string
-    MTOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    MTOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
 
diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa
index f361d49a73..8ca30b9c05 100644
--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -52,7 +52,7 @@ output header {{
         ~Nop() { }
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
 
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
     };
@@ -60,7 +60,7 @@ output header {{
 
 output decoder {{
     std::string
-    Nop::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+    Nop::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s %s", "nop", originalDisassembly);
     }
diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa
index ed613be98c..a8d50765dc 100644
--- a/src/arch/mips/isa/formats/tlbop.isa
+++ b/src/arch/mips/isa/formats/tlbop.isa
@@ -41,14 +41,14 @@ output header {{
         using MipsStaticInst::MipsStaticInst;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string
     TlbOp::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return "Disassembly of integer instruction\n";
     }
diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa
index 669f131bd4..8b353ac9c9 100644
--- a/src/arch/mips/isa/formats/trap.isa
+++ b/src/arch/mips/isa/formats/trap.isa
@@ -41,7 +41,7 @@ output header {{
         using MipsStaticInst::MipsStaticInst;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
     class TrapImm : public MipsStaticInst
     {
@@ -53,20 +53,20 @@ output header {{
         {}
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string
     Trap::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return "Disassembly of trap instruction\n";
     }
     std::string
     TrapImm::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return "Disassembly of trap instruction\n";
     }
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index cd0630d17e..5a40a6cd39 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -54,7 +54,7 @@ output header {{
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
     class CP0Unimplemented : public MipsStaticInst
     {
@@ -71,7 +71,7 @@ output header {{
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
     class CP1Unimplemented : public MipsStaticInst
     {
@@ -88,7 +88,7 @@ output header {{
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
     class CP2Unimplemented : public MipsStaticInst
     {
@@ -105,7 +105,7 @@ output header {{
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 
     /**
@@ -136,41 +136,41 @@ output header {{
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string
     FailUnimplemented::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s (unimplemented)", mnemonic);
     }
 
     std::string
     CP0Unimplemented::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s (unimplemented)", mnemonic);
     }
 
     std::string
     CP1Unimplemented::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s (unimplemented)", mnemonic);
     }
     std::string
     CP2Unimplemented::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s (unimplemented)", mnemonic);
     }
 
     std::string
     WarnUnimplemented::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s (unimplemented)", mnemonic);
     }
diff --git a/src/arch/mips/isa/formats/unknown.isa b/src/arch/mips/isa/formats/unknown.isa
index c5ef708617..fead3c4494 100644
--- a/src/arch/mips/isa/formats/unknown.isa
+++ b/src/arch/mips/isa/formats/unknown.isa
@@ -52,14 +52,14 @@ output header {{
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string
     Unknown::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
                         "unknown", machInst, OPCODE, inst2string(machInst));
diff --git a/src/arch/mips/linux/se_workload.cc b/src/arch/mips/linux/se_workload.cc
index 2c6b9d58fc..d0460fc7d5 100644
--- a/src/arch/mips/linux/se_workload.cc
+++ b/src/arch/mips/linux/se_workload.cc
@@ -45,19 +45,19 @@ class LinuxLoader : public Process::Loader
 {
   public:
     Process *
-    load(const ProcessParams &params, ::Loader::ObjectFile *obj) override
+    load(const ProcessParams &params, loader::ObjectFile *obj) override
     {
-        if (obj->getArch() != ::Loader::Mips)
+        if (obj->getArch() != loader::Mips)
             return nullptr;
 
         auto opsys = obj->getOpSys();
 
-        if (opsys == ::Loader::UnknownOpSys) {
+        if (opsys == loader::UnknownOpSys) {
             warn("Unknown operating system; assuming Linux.");
-            opsys = ::Loader::Linux;
+            opsys = loader::Linux;
         }
 
-        if (opsys != ::Loader::Linux)
+        if (opsys != loader::Linux)
             return nullptr;
 
         return new MipsProcess(params, obj);
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index 150a1637a3..c8553940ec 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -47,7 +47,7 @@
 using namespace MipsISA;
 
 MipsProcess::MipsProcess(const ProcessParams &params,
-                         ::Loader::ObjectFile *objFile)
+                         loader::ObjectFile *objFile)
     : Process(params,
               new EmulationPageTable(params.name, params.pid, PageBytes),
               objFile)
@@ -90,7 +90,7 @@ MipsProcess::argsInit(int pageSize)
 
     std::vector<gem5::auxv::AuxVector<IntType>> auxv;
 
-    auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile);
+    auto *elfObject = dynamic_cast<loader::ElfObject *>(objFile);
     if (elfObject)
     {
         // Set the system page size
diff --git a/src/arch/mips/process.hh b/src/arch/mips/process.hh
index c356d7e88b..5d354e187a 100644
--- a/src/arch/mips/process.hh
+++ b/src/arch/mips/process.hh
@@ -31,15 +31,16 @@
 
 #include "sim/process.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 class ObjectFile;
-} // namespace Loader
+} // namespace loader
 
 class MipsProcess : public Process
 {
   public:
-    MipsProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile);
+    MipsProcess(const ProcessParams &params, loader::ObjectFile *objFile);
 
   protected:
     void initState();
diff --git a/src/arch/mips/se_workload.hh b/src/arch/mips/se_workload.hh
index 70b3c9d838..489f1d19e2 100644
--- a/src/arch/mips/se_workload.hh
+++ b/src/arch/mips/se_workload.hh
@@ -52,7 +52,7 @@ class SEWorkload : public ::SEWorkload
         gdb = BaseRemoteGDB::build<RemoteGDB>(system);
     }
 
-    ::Loader::Arch getArch() const override { return ::Loader::Mips; }
+    ::loader::Arch getArch() const override { return ::loader::Mips; }
 
     struct SyscallABI : public GenericSyscallABI64
     {
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index 1789734448..cb769cd4c0 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -35,7 +35,7 @@ using namespace PowerISA;
 
 const std::string &
 PCDependentDisassembly::disassemble(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     if (!cachedDisassembly || pc != cachedPC || symtab != cachedSymtab) {
         if (!cachedDisassembly)
@@ -62,7 +62,7 @@ BranchOp::branchTarget(const PowerISA::PCState &pc) const
 
 std::string
 BranchOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     Addr target;
@@ -83,7 +83,7 @@ BranchOp::generateDisassembly(
     else
         target = pc + li;
 
-    Loader::SymbolTable::const_iterator it;
+    loader::SymbolTable::const_iterator it;
     if (symtab && (it = symtab->find(target)) != symtab->end())
         ss << it->name;
     else
@@ -106,7 +106,7 @@ BranchDispCondOp::branchTarget(const PowerISA::PCState &pc) const
 
 std::string
 BranchDispCondOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     Addr target;
@@ -130,7 +130,7 @@ BranchDispCondOp::generateDisassembly(
     else
         target = pc + bd;
 
-    Loader::SymbolTable::const_iterator it;
+    loader::SymbolTable::const_iterator it;
     if (symtab && (it = symtab->find(target)) != symtab->end())
         ss << it->name;
     else
@@ -150,7 +150,7 @@ BranchRegCondOp::branchTarget(ThreadContext *tc) const
 
 std::string
 BranchRegCondOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh
index 532a4a2dab..e4f63e8872 100644
--- a/src/arch/power/insts/branch.hh
+++ b/src/arch/power/insts/branch.hh
@@ -49,7 +49,7 @@ class PCDependentDisassembly : public PowerStaticInst
     /// Cached program counter from last disassembly
     mutable Addr cachedPC;
     /// Cached symbol table pointer from last disassembly
-    mutable const Loader::SymbolTable *cachedSymtab;
+    mutable const loader::SymbolTable *cachedSymtab;
 
     /// Constructor
     PCDependentDisassembly(const char *mnem, ExtMachInst _machInst,
@@ -60,7 +60,7 @@ class PCDependentDisassembly : public PowerStaticInst
     }
 
     const std::string &
-    disassemble(Addr pc, const Loader::SymbolTable *symtab) const;
+    disassemble(Addr pc, const loader::SymbolTable *symtab) const;
 };
 
 
@@ -90,7 +90,7 @@ class BranchOp : public PCDependentDisassembly
     using StaticInst::branchTarget;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 
@@ -161,7 +161,7 @@ class BranchDispCondOp : public BranchCondOp
     using StaticInst::branchTarget;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 
@@ -188,7 +188,7 @@ class BranchRegCondOp : public BranchCondOp
     using StaticInst::branchTarget;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 } // namespace PowerISA
diff --git a/src/arch/power/insts/condition.cc b/src/arch/power/insts/condition.cc
index f08fcb4772..017847322f 100644
--- a/src/arch/power/insts/condition.cc
+++ b/src/arch/power/insts/condition.cc
@@ -32,7 +32,7 @@ using namespace PowerISA;
 
 std::string
 CondLogicOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
@@ -46,7 +46,7 @@ CondLogicOp::generateDisassembly(
 
 std::string
 CondMoveOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
diff --git a/src/arch/power/insts/condition.hh b/src/arch/power/insts/condition.hh
index a38f714dd7..deaaa512ba 100644
--- a/src/arch/power/insts/condition.hh
+++ b/src/arch/power/insts/condition.hh
@@ -56,7 +56,7 @@ class CondLogicOp : public PowerStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -78,7 +78,7 @@ class CondMoveOp : public PowerStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 } // namespace PowerISA
diff --git a/src/arch/power/insts/floating.cc b/src/arch/power/insts/floating.cc
index 5ccaac9df6..6a53d3c3ab 100644
--- a/src/arch/power/insts/floating.cc
+++ b/src/arch/power/insts/floating.cc
@@ -31,7 +31,7 @@
 using namespace PowerISA;
 
 std::string
-FloatOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+FloatOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
diff --git a/src/arch/power/insts/floating.hh b/src/arch/power/insts/floating.hh
index 0acefdf0d8..02dbbb2ed2 100644
--- a/src/arch/power/insts/floating.hh
+++ b/src/arch/power/insts/floating.hh
@@ -143,7 +143,7 @@ class FloatOp : public PowerStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 } // namespace PowerISA
diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
index c10abe603c..a65d7b716d 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -31,7 +31,7 @@
 using namespace PowerISA;
 
 std::string
-IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+IntOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     bool printDest = true;
@@ -87,7 +87,7 @@ IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
 
 std::string
-IntImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+IntImmOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
@@ -124,7 +124,7 @@ IntImmOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
 std::string
 IntShiftOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
@@ -152,7 +152,7 @@ IntShiftOp::generateDisassembly(
 
 std::string
 IntRotateOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh
index 0ede72411e..04222a19e0 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -93,7 +93,7 @@ class IntOp : public PowerStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 
@@ -116,7 +116,7 @@ class IntImmOp : public IntOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 
@@ -137,7 +137,7 @@ class IntShiftOp : public IntOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 
@@ -173,7 +173,7 @@ class IntRotateOp : public IntShiftOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 } // namespace PowerISA
diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc
index 4c2688c8cd..3275623e37 100644
--- a/src/arch/power/insts/mem.cc
+++ b/src/arch/power/insts/mem.cc
@@ -33,14 +33,14 @@
 using namespace PowerISA;
 
 std::string
-MemOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+MemOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     return csprintf("%-10s", mnemonic);
 }
 
 std::string
 MemDispOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh
index e982515cbe..18f81986a0 100644
--- a/src/arch/power/insts/mem.hh
+++ b/src/arch/power/insts/mem.hh
@@ -52,7 +52,7 @@ class MemOp : public PowerStaticInst
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 
@@ -73,7 +73,7 @@ class MemDispOp : public MemOp
     }
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
diff --git a/src/arch/power/insts/misc.cc b/src/arch/power/insts/misc.cc
index 25177c573a..ec3a939087 100644
--- a/src/arch/power/insts/misc.cc
+++ b/src/arch/power/insts/misc.cc
@@ -31,7 +31,7 @@
 using namespace PowerISA;
 
 std::string
-MiscOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+MiscOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
diff --git a/src/arch/power/insts/misc.hh b/src/arch/power/insts/misc.hh
index a81c623fa3..8cf9afc9b3 100644
--- a/src/arch/power/insts/misc.hh
+++ b/src/arch/power/insts/misc.hh
@@ -43,7 +43,7 @@ class MiscOp : public PowerStaticInst
     using PowerStaticInst::PowerStaticInst;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 } // namespace PowerISA
diff --git a/src/arch/power/insts/static_inst.cc b/src/arch/power/insts/static_inst.cc
index 35cf286478..d10c8615dd 100644
--- a/src/arch/power/insts/static_inst.cc
+++ b/src/arch/power/insts/static_inst.cc
@@ -60,7 +60,7 @@ PowerStaticInst::printReg(std::ostream &os, RegId reg) const
 
 std::string
 PowerStaticInst::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
diff --git a/src/arch/power/insts/static_inst.hh b/src/arch/power/insts/static_inst.hh
index eed7c8668f..9eb87a1f21 100644
--- a/src/arch/power/insts/static_inst.hh
+++ b/src/arch/power/insts/static_inst.hh
@@ -62,7 +62,7 @@ class PowerStaticInst : public StaticInst
     printReg(std::ostream &os, RegId reg) const;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
     void
     advancePC(PowerISA::PCState &pcState) const override
diff --git a/src/arch/power/isa/formats/unimp.isa b/src/arch/power/isa/formats/unimp.isa
index a3f4692c89..853fbe8eac 100644
--- a/src/arch/power/isa/formats/unimp.isa
+++ b/src/arch/power/isa/formats/unimp.isa
@@ -55,7 +55,7 @@ output header {{
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 
     /**
@@ -86,21 +86,21 @@ output header {{
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string
     FailUnimplemented::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s (unimplemented)", mnemonic);
     }
 
     std::string
     WarnUnimplemented::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s (unimplemented)", mnemonic);
     }
diff --git a/src/arch/power/isa/formats/unknown.isa b/src/arch/power/isa/formats/unknown.isa
index d83f79cf22..31290d54cc 100644
--- a/src/arch/power/isa/formats/unknown.isa
+++ b/src/arch/power/isa/formats/unknown.isa
@@ -53,14 +53,14 @@ output header {{
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string
     Unknown::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
                         "unknown", machInst, PO, inst2string(machInst));
diff --git a/src/arch/power/linux/se_workload.cc b/src/arch/power/linux/se_workload.cc
index 90add2fcba..c699b62da2 100644
--- a/src/arch/power/linux/se_workload.cc
+++ b/src/arch/power/linux/se_workload.cc
@@ -45,19 +45,19 @@ class LinuxLoader : public Process::Loader
 {
   public:
     Process *
-    load(const ProcessParams &params, ::Loader::ObjectFile *obj) override
+    load(const ProcessParams &params, loader::ObjectFile *obj) override
     {
-        if (obj->getArch() != ::Loader::Power)
+        if (obj->getArch() != loader::Power)
             return nullptr;
 
         auto opsys = obj->getOpSys();
 
-        if (opsys == ::Loader::UnknownOpSys) {
+        if (opsys == loader::UnknownOpSys) {
             warn("Unknown operating system; assuming Linux.");
-            opsys = ::Loader::Linux;
+            opsys = loader::Linux;
         }
 
-        if (opsys != ::Loader::Linux)
+        if (opsys != loader::Linux)
             return nullptr;
 
         return new PowerProcess(params, obj);
diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc
index 810953b83c..050dff3281 100644
--- a/src/arch/power/process.cc
+++ b/src/arch/power/process.cc
@@ -48,7 +48,7 @@
 using namespace PowerISA;
 
 PowerProcess::PowerProcess(
-       const ProcessParams &params, ::Loader::ObjectFile *objFile)
+       const ProcessParams &params, loader::ObjectFile *objFile)
     : Process(params,
               new EmulationPageTable(params.name, params.pid, PageBytes),
               objFile)
@@ -101,7 +101,7 @@ PowerProcess::argsInit(int intSize, int pageSize)
 
     //Setup the auxilliary vectors. These will already have endian conversion.
     //Auxilliary vectors are loaded only for elf formatted executables.
-    auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile);
+    auto *elfObject = dynamic_cast<loader::ElfObject *>(objFile);
     if (elfObject) {
         uint32_t features = 0;
 
diff --git a/src/arch/power/process.hh b/src/arch/power/process.hh
index 5e5a5036fc..b60328148e 100644
--- a/src/arch/power/process.hh
+++ b/src/arch/power/process.hh
@@ -32,10 +32,11 @@
 
 #include "sim/process.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 class ObjectFile;
-} // namespace Loader;
+} // namespace loader
 
 class PowerProcess : public Process
 {
@@ -43,7 +44,7 @@ class PowerProcess : public Process
     void initState() override;
 
   public:
-    PowerProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile);
+    PowerProcess(const ProcessParams &params, loader::ObjectFile *objFile);
 
     void argsInit(int intSize, int pageSize);
 };
diff --git a/src/arch/power/se_workload.hh b/src/arch/power/se_workload.hh
index 1aeea6b691..ad7896b990 100644
--- a/src/arch/power/se_workload.hh
+++ b/src/arch/power/se_workload.hh
@@ -52,7 +52,7 @@ class SEWorkload : public ::SEWorkload
         gdb = BaseRemoteGDB::build<RemoteGDB>(system);
     }
 
-    ::Loader::Arch getArch() const override { return ::Loader::Power; }
+    ::loader::Arch getArch() const override { return ::loader::Power; }
 
     struct SyscallABI : public GenericSyscallABI64
     {
diff --git a/src/arch/riscv/bare_metal/fs_workload.cc b/src/arch/riscv/bare_metal/fs_workload.cc
index 9607e19b69..b9fb3a3ad9 100644
--- a/src/arch/riscv/bare_metal/fs_workload.cc
+++ b/src/arch/riscv/bare_metal/fs_workload.cc
@@ -39,7 +39,7 @@ namespace RiscvISA
 
 BareMetal::BareMetal(const Params &p) : Workload(p),
     _isBareMetal(p.bare_metal), _resetVect(p.reset_vect),
-    bootloader(Loader::createObjectFile(p.bootloader))
+    bootloader(loader::createObjectFile(p.bootloader))
 {
     fatal_if(!bootloader, "Could not load bootloader file %s.", p.bootloader);
     _resetVect = bootloader->entryPoint();
diff --git a/src/arch/riscv/bare_metal/fs_workload.hh b/src/arch/riscv/bare_metal/fs_workload.hh
index d7545f271e..0bcda8f538 100644
--- a/src/arch/riscv/bare_metal/fs_workload.hh
+++ b/src/arch/riscv/bare_metal/fs_workload.hh
@@ -43,8 +43,8 @@ class BareMetal : public Workload
     bool _isBareMetal;
     // entry point for simulation
     Addr _resetVect;
-    Loader::ObjectFile *bootloader;
-    Loader::SymbolTable bootloaderSymtab;
+    loader::ObjectFile *bootloader;
+    loader::SymbolTable bootloaderSymtab;
 
   public:
     PARAMS(RiscvBareMetal);
@@ -60,15 +60,16 @@ class BareMetal : public Workload
         gdb = BaseRemoteGDB::build<RemoteGDB>(system);
     }
 
-    Loader::Arch getArch() const override { return bootloader->getArch(); }
-    const Loader::SymbolTable &
+    loader::Arch getArch() const override { return bootloader->getArch(); }
+
+    const loader::SymbolTable &
     symtab(ThreadContext *tc) override
     {
         return bootloaderSymtab;
     }
 
     bool
-    insertSymbol(const Loader::Symbol &symbol) override
+    insertSymbol(const loader::Symbol &symbol) override
     {
         return bootloaderSymtab.insert(symbol);
     }
diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc
index 305cee81e3..55521fb50f 100644
--- a/src/arch/riscv/insts/amo.cc
+++ b/src/arch/riscv/insts/amo.cc
@@ -43,7 +43,7 @@ namespace RiscvISA
 // memfence micro instruction
 std::string
 MemFenceMicro::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     ss << csprintf("0x%08x", machInst) << ' ' << mnemonic;
@@ -59,7 +59,7 @@ Fault MemFenceMicro::execute(ExecContext *xc,
 // load-reserved
 std::string
 LoadReserved::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     ss << mnemonic;
@@ -76,7 +76,7 @@ LoadReserved::generateDisassembly(
 
 std::string
 LoadReservedMicro::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ("
@@ -87,7 +87,7 @@ LoadReservedMicro::generateDisassembly(
 // store-conditional
 std::string
 StoreCond::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     ss << mnemonic;
@@ -105,7 +105,7 @@ StoreCond::generateDisassembly(
 
 std::string
 StoreCondMicro::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
@@ -117,7 +117,7 @@ StoreCondMicro::generateDisassembly(
 // AMOs
 std::string
 AtomicMemOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     ss << mnemonic;
@@ -135,7 +135,7 @@ AtomicMemOp::generateDisassembly(
 
 std::string
 AtomicMemOpMicro::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", "
diff --git a/src/arch/riscv/insts/amo.hh b/src/arch/riscv/insts/amo.hh
index e4f3a4e46b..d0327357df 100644
--- a/src/arch/riscv/insts/amo.hh
+++ b/src/arch/riscv/insts/amo.hh
@@ -51,7 +51,7 @@ class MemFenceMicro : public RiscvMicroInst
 
     Fault execute(ExecContext *, Trace::InstRecord *) const override;
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // load-reserved
@@ -61,7 +61,7 @@ class LoadReserved : public RiscvMacroInst
     using RiscvMacroInst::RiscvMacroInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class LoadReservedMicro : public RiscvMicroInst
@@ -71,7 +71,7 @@ class LoadReservedMicro : public RiscvMicroInst
     using RiscvMicroInst::RiscvMicroInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // store-cond
@@ -81,7 +81,7 @@ class StoreCond : public RiscvMacroInst
     using RiscvMacroInst::RiscvMacroInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class StoreCondMicro : public RiscvMicroInst
@@ -91,7 +91,7 @@ class StoreCondMicro : public RiscvMicroInst
     using RiscvMicroInst::RiscvMicroInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // AMOs
@@ -101,7 +101,7 @@ class AtomicMemOp : public RiscvMacroInst
     using RiscvMacroInst::RiscvMacroInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class AtomicMemOpMicro : public RiscvMicroInst
@@ -111,7 +111,7 @@ class AtomicMemOpMicro : public RiscvMicroInst
     using RiscvMicroInst::RiscvMicroInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
diff --git a/src/arch/riscv/insts/compressed.cc b/src/arch/riscv/insts/compressed.cc
index 327bcf462f..246838262d 100644
--- a/src/arch/riscv/insts/compressed.cc
+++ b/src/arch/riscv/insts/compressed.cc
@@ -40,7 +40,7 @@ namespace RiscvISA
 
 std::string
 CompRegOp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
diff --git a/src/arch/riscv/insts/compressed.hh b/src/arch/riscv/insts/compressed.hh
index b2f89daddc..01a612e3e8 100644
--- a/src/arch/riscv/insts/compressed.hh
+++ b/src/arch/riscv/insts/compressed.hh
@@ -47,7 +47,7 @@ class CompRegOp : public RiscvStaticInst
     using RiscvStaticInst::RiscvStaticInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 }
diff --git a/src/arch/riscv/insts/mem.cc b/src/arch/riscv/insts/mem.cc
index 383ba96356..a4336c91c1 100644
--- a/src/arch/riscv/insts/mem.cc
+++ b/src/arch/riscv/insts/mem.cc
@@ -41,7 +41,7 @@ namespace RiscvISA
 {
 
 std::string
-Load::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+Load::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
@@ -50,7 +50,7 @@ Load::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-Store::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+Store::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     ss << mnemonic << ' ' << registerName(srcRegIdx(1)) << ", " <<
diff --git a/src/arch/riscv/insts/mem.hh b/src/arch/riscv/insts/mem.hh
index 0d4676c9ff..0d8733e7b5 100644
--- a/src/arch/riscv/insts/mem.hh
+++ b/src/arch/riscv/insts/mem.hh
@@ -56,7 +56,7 @@ class Load : public MemInst
     using MemInst::MemInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class Store : public MemInst
@@ -65,7 +65,7 @@ class Store : public MemInst
     using MemInst::MemInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 }
diff --git a/src/arch/riscv/insts/pseudo.hh b/src/arch/riscv/insts/pseudo.hh
index 53fe6858dc..56962f0f9c 100644
--- a/src/arch/riscv/insts/pseudo.hh
+++ b/src/arch/riscv/insts/pseudo.hh
@@ -42,7 +42,7 @@ class PseudoOp : public RiscvStaticInst
     using RiscvStaticInst::RiscvStaticInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override
+        Addr pc, const loader::SymbolTable *symtab) const override
     {
         return mnemonic;
     }
diff --git a/src/arch/riscv/insts/standard.cc b/src/arch/riscv/insts/standard.cc
index 6ea2253f80..43f6bc7212 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -42,7 +42,7 @@ namespace RiscvISA
 {
 
 std::string
-RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+RegOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
@@ -55,7 +55,7 @@ RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+CSROp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
     ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ";
@@ -72,7 +72,7 @@ CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-SystemOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+SystemOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     if (strcmp(mnemonic, "fence_vma") == 0) {
         std::stringstream ss;
diff --git a/src/arch/riscv/insts/standard.hh b/src/arch/riscv/insts/standard.hh
index 1e9fcb74cd..5b6728a9f2 100644
--- a/src/arch/riscv/insts/standard.hh
+++ b/src/arch/riscv/insts/standard.hh
@@ -51,7 +51,7 @@ class RegOp : public RiscvStaticInst
     using RiscvStaticInst::RiscvStaticInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -77,7 +77,7 @@ class SystemOp : public RiscvStaticInst
     using RiscvStaticInst::RiscvStaticInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -119,7 +119,7 @@ class CSROp : public RiscvStaticInst
     }
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 }
diff --git a/src/arch/riscv/insts/unknown.hh b/src/arch/riscv/insts/unknown.hh
index fe7825c6d0..9c851ce285 100644
--- a/src/arch/riscv/insts/unknown.hh
+++ b/src/arch/riscv/insts/unknown.hh
@@ -62,7 +62,7 @@ class Unknown : public RiscvStaticInst
 
     std::string
     generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override
+            Addr pc, const loader::SymbolTable *symtab) const override
     {
         return csprintf("unknown opcode %#02x", OPCODE);
     }
diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa
index d467ea6273..a2da59df11 100644
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -128,7 +128,7 @@ def template CBasicDeclare {{
         %(class_name)s(MachInst machInst);
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
     };
 }};
 
@@ -147,7 +147,7 @@ def template CBasicExecute {{
 
     std::string
     %(class_name)s::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::vector<RegId> indices = {%(regs)s};
         std::stringstream ss;
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index dba460f690..edb22683a6 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -47,7 +47,7 @@ def template ImmDeclare {{
         %(class_name)s(MachInst machInst);
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
         std::string generateDisassembly(Addr pc,
-            const Loader::SymbolTable *symtab) const override;
+            const loader::SymbolTable *symtab) const override;
     };
 }};
 
@@ -75,7 +75,7 @@ def template ImmExecute {{
 
     std::string
     %(class_name)s::generateDisassembly(Addr pc,
-            const Loader::SymbolTable *symtab) const
+            const loader::SymbolTable *symtab) const
     {
         std::vector<RegId> indices = {%(regs)s};
         std::stringstream ss;
@@ -101,7 +101,7 @@ def template CILuiExecute {{
 
     std::string
     %(class_name)s::generateDisassembly(Addr pc,
-            const Loader::SymbolTable *symtab) const
+            const loader::SymbolTable *symtab) const
     {
         std::vector<RegId> indices = {%(regs)s};
         std::stringstream ss;
@@ -129,7 +129,7 @@ def template FenceExecute {{
 
     std::string
     %(class_name)s::generateDisassembly(Addr pc,
-            const Loader::SymbolTable *symtab) const
+            const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
         ss << mnemonic;
@@ -173,7 +173,7 @@ def template BranchDeclare {{
 
         std::string
         generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
 
         RiscvISA::PCState
         branchTarget(const RiscvISA::PCState &branchPC) const override;
@@ -202,7 +202,7 @@ def template BranchExecute {{
 
     std::string
     %(class_name)s::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::vector<RegId> indices = {%(regs)s};
         std::stringstream ss;
@@ -230,7 +230,7 @@ def template JumpDeclare {{
 
         std::string
         generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
 
         RiscvISA::PCState
         branchTarget(ThreadContext *tc) const override;
@@ -261,7 +261,7 @@ def template JumpExecute {{
 
     std::string
     %(class_name)s::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream ss;
         ss << mnemonic << ' ';
diff --git a/src/arch/riscv/linux/fs_workload.cc b/src/arch/riscv/linux/fs_workload.cc
index fca839cc82..e6b1b9bb2c 100644
--- a/src/arch/riscv/linux/fs_workload.cc
+++ b/src/arch/riscv/linux/fs_workload.cc
@@ -47,7 +47,7 @@ FsLinux::initState()
         inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
                 params().dtb_addr);
 
-        auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);
+        auto *dtb_file = new loader::DtbFile(params().dtb_filename);
 
         if (!dtb_file->addBootCmdLine(
                     commandLine.c_str(), commandLine.size())) {
diff --git a/src/arch/riscv/linux/se_workload.cc b/src/arch/riscv/linux/se_workload.cc
index 7ffc5f6132..09f4758e96 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -45,23 +45,23 @@ class LinuxLoader : public Process::Loader
 {
   public:
     Process *
-    load(const ProcessParams &params, ::Loader::ObjectFile *obj) override
+    load(const ProcessParams &params, loader::ObjectFile *obj) override
     {
         auto arch = obj->getArch();
         auto opsys = obj->getOpSys();
 
-        if (arch != ::Loader::Riscv64 && arch != ::Loader::Riscv32)
+        if (arch != loader::Riscv64 && arch != loader::Riscv32)
             return nullptr;
 
-        if (opsys == ::Loader::UnknownOpSys) {
+        if (opsys == loader::UnknownOpSys) {
             warn("Unknown operating system; assuming Linux.");
-            opsys = ::Loader::Linux;
+            opsys = loader::Linux;
         }
 
-        if (opsys != ::Loader::Linux)
+        if (opsys != loader::Linux)
             return nullptr;
 
-        if (arch == ::Loader::Riscv64)
+        if (arch == loader::Riscv64)
             return new RiscvProcess64(params, obj);
         else
             return new RiscvProcess32(params, obj);
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index 2142c5c5a7..fd014cdc98 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -58,7 +58,7 @@
 using namespace RiscvISA;
 
 RiscvProcess::RiscvProcess(const ProcessParams &params,
-        ::Loader::ObjectFile *objFile) :
+        loader::ObjectFile *objFile) :
         Process(params,
                 new EmulationPageTable(params.name, params.pid, PageBytes),
                 objFile)
@@ -67,7 +67,7 @@ RiscvProcess::RiscvProcess(const ProcessParams &params,
 }
 
 RiscvProcess64::RiscvProcess64(const ProcessParams &params,
-        ::Loader::ObjectFile *objFile) :
+        loader::ObjectFile *objFile) :
         RiscvProcess(params, objFile)
 {
     const Addr stack_base = 0x7FFFFFFFFFFFFFFFL;
@@ -80,7 +80,7 @@ RiscvProcess64::RiscvProcess64(const ProcessParams &params,
 }
 
 RiscvProcess32::RiscvProcess32(const ProcessParams &params,
-        ::Loader::ObjectFile *objFile) :
+        loader::ObjectFile *objFile) :
         RiscvProcess(params, objFile)
 {
     const Addr stack_base = 0x7FFFFFFF;
@@ -123,7 +123,7 @@ RiscvProcess::argsInit(int pageSize)
     const int RandomBytes = 16;
     const int addrSize = sizeof(IntType);
 
-    auto *elfObject = dynamic_cast<::Loader::ElfObject*>(objFile);
+    auto *elfObject = dynamic_cast<loader::ElfObject*>(objFile);
     memState->setStackMin(memState->getStackBase());
 
     // Determine stack size and populate auxv
diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh
index 105d1eb7f8..25299aefae 100644
--- a/src/arch/riscv/process.hh
+++ b/src/arch/riscv/process.hh
@@ -37,17 +37,18 @@
 #include "sim/process.hh"
 #include "sim/syscall_abi.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 class ObjectFile;
-} // namespace Loader
+} // namespace loader
 
 class System;
 
 class RiscvProcess : public Process
 {
   protected:
-    RiscvProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile);
+    RiscvProcess(const ProcessParams &params, loader::ObjectFile *objFile);
     template<class IntType>
     void argsInit(int pageSize);
 
@@ -58,7 +59,7 @@ class RiscvProcess : public Process
 class RiscvProcess64 : public RiscvProcess
 {
   public:
-    RiscvProcess64(const ProcessParams &params, ::Loader::ObjectFile *objFile);
+    RiscvProcess64(const ProcessParams &params, loader::ObjectFile *objFile);
 
   protected:
     void initState() override;
@@ -67,7 +68,7 @@ class RiscvProcess64 : public RiscvProcess
 class RiscvProcess32 : public RiscvProcess
 {
   public:
-    RiscvProcess32(const ProcessParams &params, ::Loader::ObjectFile *objFile);
+    RiscvProcess32(const ProcessParams &params, loader::ObjectFile *objFile);
 
   protected:
     void initState() override;
diff --git a/src/arch/riscv/se_workload.hh b/src/arch/riscv/se_workload.hh
index 8196f73a82..5bca1bc702 100644
--- a/src/arch/riscv/se_workload.hh
+++ b/src/arch/riscv/se_workload.hh
@@ -52,7 +52,7 @@ class SEWorkload : public ::SEWorkload
         gdb = BaseRemoteGDB::build<RemoteGDB>(system);
     }
 
-    ::Loader::Arch getArch() const override { return ::Loader::Riscv64; }
+    ::loader::Arch getArch() const override { return ::loader::Riscv64; }
 
     //FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
     using SyscallABI = RegABI64;
diff --git a/src/arch/sparc/fs_workload.hh b/src/arch/sparc/fs_workload.hh
index 8eae7cd064..e3c3f5bc1d 100644
--- a/src/arch/sparc/fs_workload.hh
+++ b/src/arch/sparc/fs_workload.hh
@@ -40,7 +40,7 @@ namespace SparcISA
 class FsWorkload : public Workload
 {
   protected:
-    Loader::SymbolTable defaultSymtab;
+    loader::SymbolTable defaultSymtab;
 
   public:
     FsWorkload(const SparcFsWorkloadParams &params) : Workload(params) {}
@@ -60,16 +60,16 @@ class FsWorkload : public Workload
         getREDVector(0x001, pc, npc);
         return pc;
     }
-    Loader::Arch getArch() const override { return Loader::SPARC64; }
+    loader::Arch getArch() const override { return loader::SPARC64; }
 
-    const Loader::SymbolTable &
+    const loader::SymbolTable &
     symtab(ThreadContext *tc) override
     {
         return defaultSymtab;
     }
 
     bool
-    insertSymbol(const Loader::Symbol &symbol) override
+    insertSymbol(const loader::Symbol &symbol) override
     {
         return defaultSymtab.insert(symbol);
     }
diff --git a/src/arch/sparc/insts/blockmem.cc b/src/arch/sparc/insts/blockmem.cc
index d83332b128..6b1d8eea04 100644
--- a/src/arch/sparc/insts/blockmem.cc
+++ b/src/arch/sparc/insts/blockmem.cc
@@ -33,7 +33,7 @@ namespace SparcISA
 
 std::string
 BlockMemMicro::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
     bool load = flags[IsLoad];
@@ -59,7 +59,7 @@ BlockMemMicro::generateDisassembly(
 
 std::string
 BlockMemImmMicro::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
     bool load = flags[IsLoad];
diff --git a/src/arch/sparc/insts/blockmem.hh b/src/arch/sparc/insts/blockmem.hh
index f5bc39765a..5f7a8837b1 100644
--- a/src/arch/sparc/insts/blockmem.hh
+++ b/src/arch/sparc/insts/blockmem.hh
@@ -64,7 +64,7 @@ class BlockMemMicro : public SparcMicroInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
     const int8_t offset;
 };
@@ -79,7 +79,7 @@ class BlockMemImmMicro : public BlockMemMicro
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
     const int32_t imm;
 };
diff --git a/src/arch/sparc/insts/branch.cc b/src/arch/sparc/insts/branch.cc
index 2f195550eb..f3fae550c9 100644
--- a/src/arch/sparc/insts/branch.cc
+++ b/src/arch/sparc/insts/branch.cc
@@ -41,7 +41,7 @@ template class BranchNBits<22>;
 template class BranchNBits<30>;
 
 std::string
-Branch::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+Branch::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
 
@@ -56,7 +56,7 @@ Branch::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
 std::string
 BranchImm13::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
 
@@ -74,7 +74,7 @@ BranchImm13::generateDisassembly(
 
 std::string
 BranchDisp::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
 
@@ -83,7 +83,7 @@ BranchDisp::generateDisassembly(
     printMnemonic(response, mnemonic);
     ccprintf(response, "%#x", target);
 
-    Loader::SymbolTable::const_iterator it;
+    loader::SymbolTable::const_iterator it;
     if (symtab && (it = symtab->findNearest(target)) != symtab->end()) {
         ccprintf(response, " <%s", it->name);
         if (it->address != target)
diff --git a/src/arch/sparc/insts/branch.hh b/src/arch/sparc/insts/branch.hh
index 915c0d8cde..68a1220810 100644
--- a/src/arch/sparc/insts/branch.hh
+++ b/src/arch/sparc/insts/branch.hh
@@ -48,7 +48,7 @@ class Branch : public SparcStaticInst
     using SparcStaticInst::SparcStaticInst;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -63,7 +63,7 @@ class BranchDisp : public Branch
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
     int32_t disp;
 };
@@ -108,7 +108,7 @@ class BranchImm13 : public Branch
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
     int32_t imm;
 };
diff --git a/src/arch/sparc/insts/integer.cc b/src/arch/sparc/insts/integer.cc
index d58334f467..8ed0d89e25 100644
--- a/src/arch/sparc/insts/integer.cc
+++ b/src/arch/sparc/insts/integer.cc
@@ -38,7 +38,7 @@ namespace SparcISA
 
 bool
 IntOp::printPseudoOps(std::ostream &os, Addr pc,
-                      const Loader::SymbolTable *symbab) const
+                      const loader::SymbolTable *symbab) const
 {
     if (!std::strcmp(mnemonic, "or") && srcRegIdx(0).index() == 0) {
         printMnemonic(os, "mov");
@@ -52,7 +52,7 @@ IntOp::printPseudoOps(std::ostream &os, Addr pc,
 
 bool
 IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
-                         const Loader::SymbolTable *symbab) const
+                         const loader::SymbolTable *symbab) const
 {
     if (!std::strcmp(mnemonic, "or")) {
         if (_numSrcRegs > 0 && srcRegIdx(0).index() == 0) {
@@ -76,7 +76,7 @@ IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
 }
 
 std::string
-IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+IntOp::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
 
@@ -91,7 +91,7 @@ IntOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-IntOpImm::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+IntOpImm::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
 
@@ -109,7 +109,7 @@ IntOpImm::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-SetHi::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+SetHi::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
 
diff --git a/src/arch/sparc/insts/integer.hh b/src/arch/sparc/insts/integer.hh
index 890ed058b5..ae3f6294d7 100644
--- a/src/arch/sparc/insts/integer.hh
+++ b/src/arch/sparc/insts/integer.hh
@@ -48,10 +48,10 @@ class IntOp : public SparcStaticInst
     using SparcStaticInst::SparcStaticInst;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
     virtual bool printPseudoOps(std::ostream &os, Addr pc,
-                                const Loader::SymbolTable *symtab) const;
+                                const loader::SymbolTable *symtab) const;
 };
 
 /**
@@ -69,10 +69,10 @@ class IntOpImm : public IntOp
     int64_t imm;
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
     bool printPseudoOps(std::ostream &os, Addr pc,
-                        const Loader::SymbolTable *symtab) const override;
+                        const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -121,7 +121,7 @@ class SetHi : public IntOpImm
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 }
diff --git a/src/arch/sparc/insts/mem.cc b/src/arch/sparc/insts/mem.cc
index 2d7ebc62fe..60cfc59157 100644
--- a/src/arch/sparc/insts/mem.cc
+++ b/src/arch/sparc/insts/mem.cc
@@ -32,7 +32,7 @@ namespace SparcISA
 {
 
 std::string
-Mem::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+Mem::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
     bool load = flags[IsLoad];
@@ -59,7 +59,7 @@ Mem::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-MemImm::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+MemImm::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
     bool load = flags[IsLoad];
diff --git a/src/arch/sparc/insts/mem.hh b/src/arch/sparc/insts/mem.hh
index fb1f0ec56a..53c664c47c 100644
--- a/src/arch/sparc/insts/mem.hh
+++ b/src/arch/sparc/insts/mem.hh
@@ -48,7 +48,7 @@ class Mem : public SparcStaticInst
     using SparcStaticInst::SparcStaticInst;
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -64,7 +64,7 @@ class MemImm : public Mem
     {}
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 
     const int32_t imm;
 };
diff --git a/src/arch/sparc/insts/micro.cc b/src/arch/sparc/insts/micro.cc
index 7bfeda1a6c..2652a90a41 100644
--- a/src/arch/sparc/insts/micro.cc
+++ b/src/arch/sparc/insts/micro.cc
@@ -33,7 +33,7 @@ namespace SparcISA
 
 std::string
 SparcMacroInst::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
     printMnemonic(response, mnemonic);
diff --git a/src/arch/sparc/insts/micro.hh b/src/arch/sparc/insts/micro.hh
index 2cb2283b25..33d0f87399 100644
--- a/src/arch/sparc/insts/micro.hh
+++ b/src/arch/sparc/insts/micro.hh
@@ -56,7 +56,7 @@ class SparcMacroInst : public SparcStaticInst
     }
 
     std::string generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const override;
+        Addr pc, const loader::SymbolTable *symtab) const override;
 
     StaticInstPtr *microops;
 
diff --git a/src/arch/sparc/insts/nop.cc b/src/arch/sparc/insts/nop.cc
index 990b93dcfc..0d2aa2169d 100644
--- a/src/arch/sparc/insts/nop.cc
+++ b/src/arch/sparc/insts/nop.cc
@@ -54,14 +54,14 @@ output header {{
             }
 
             std::string generateDisassembly(Addr pc,
-                    const Loader::SymbolTable *symtab) const override;
+                    const loader::SymbolTable *symtab) const override;
         };
 }};
 
 output decoder {{
         std::string
         Nop::generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const
+                Addr pc, const loader::SymbolTable *symtab) const
         {
             std::stringstream response;
             printMnemonic(response, mnemonic);
diff --git a/src/arch/sparc/insts/nop.hh b/src/arch/sparc/insts/nop.hh
index 8bc100348d..d9feb981e9 100644
--- a/src/arch/sparc/insts/nop.hh
+++ b/src/arch/sparc/insts/nop.hh
@@ -60,7 +60,7 @@ class Nop : public SparcStaticInst
 
     std::string
     generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override
+            Addr pc, const loader::SymbolTable *symtab) const override
     {
         std::stringstream response;
         printMnemonic(response, mnemonic);
diff --git a/src/arch/sparc/insts/priv.cc b/src/arch/sparc/insts/priv.cc
index f17853f9a9..015b74bd7b 100644
--- a/src/arch/sparc/insts/priv.cc
+++ b/src/arch/sparc/insts/priv.cc
@@ -33,7 +33,7 @@ namespace SparcISA
 {
 
 std::string
-Priv::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+Priv::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
 
@@ -43,7 +43,7 @@ Priv::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-RdPriv::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+RdPriv::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
 
@@ -56,7 +56,7 @@ RdPriv::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 }
 
 std::string
-WrPriv::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+WrPriv::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
 
@@ -77,7 +77,7 @@ WrPriv::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 
 std::string
 WrPrivImm::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
 
diff --git a/src/arch/sparc/insts/priv.hh b/src/arch/sparc/insts/priv.hh
index f98cf6e4ba..a152dda04a 100644
--- a/src/arch/sparc/insts/priv.hh
+++ b/src/arch/sparc/insts/priv.hh
@@ -43,7 +43,7 @@ class Priv : public SparcStaticInst
   protected:
     using SparcStaticInst::SparcStaticInst;
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 class PrivReg : public Priv
@@ -64,7 +64,7 @@ class RdPriv : public PrivReg
   protected:
     using PrivReg::PrivReg;
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 // This class is for instructions that explicitly write control
@@ -74,7 +74,7 @@ class WrPriv : public PrivReg
   protected:
     using PrivReg::PrivReg;
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 };
 
 /**
@@ -103,7 +103,7 @@ class WrPrivImm : public PrivImm
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
     char const *regName;
 };
diff --git a/src/arch/sparc/insts/static_inst.cc b/src/arch/sparc/insts/static_inst.cc
index 6369152fe6..2fdb79f506 100644
--- a/src/arch/sparc/insts/static_inst.cc
+++ b/src/arch/sparc/insts/static_inst.cc
@@ -251,7 +251,7 @@ SparcStaticInst::printReg(std::ostream &os, RegId reg)
 
 std::string
 SparcStaticInst::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
diff --git a/src/arch/sparc/insts/static_inst.hh b/src/arch/sparc/insts/static_inst.hh
index f8af2d952b..51b0305e0a 100644
--- a/src/arch/sparc/insts/static_inst.hh
+++ b/src/arch/sparc/insts/static_inst.hh
@@ -96,7 +96,7 @@ class SparcStaticInst : public StaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
     static void printMnemonic(std::ostream &os, const char *mnemonic);
     static void printReg(std::ostream &os, RegId reg);
diff --git a/src/arch/sparc/insts/trap.cc b/src/arch/sparc/insts/trap.cc
index 120900ac09..caa3c755d2 100644
--- a/src/arch/sparc/insts/trap.cc
+++ b/src/arch/sparc/insts/trap.cc
@@ -32,7 +32,7 @@ namespace SparcISA
 {
 
 std::string
-Trap::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
+Trap::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream response;
 
diff --git a/src/arch/sparc/insts/trap.hh b/src/arch/sparc/insts/trap.hh
index 4f3c6def3a..b38ea0ed93 100644
--- a/src/arch/sparc/insts/trap.hh
+++ b/src/arch/sparc/insts/trap.hh
@@ -54,7 +54,7 @@ class Trap : public SparcStaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
     int trapNum;
 };
@@ -66,7 +66,7 @@ class FpUnimpl : public SparcStaticInst
 
     std::string
     generateDisassembly(
-            Addr pc,  const Loader::SymbolTable *symtab) const override
+            Addr pc,  const loader::SymbolTable *symtab) const override
     {
         return mnemonic;
     }
diff --git a/src/arch/sparc/insts/unimp.hh b/src/arch/sparc/insts/unimp.hh
index a1f6b805f5..6b1e9a4baa 100644
--- a/src/arch/sparc/insts/unimp.hh
+++ b/src/arch/sparc/insts/unimp.hh
@@ -68,7 +68,7 @@ class FailUnimplemented : public SparcStaticInst
 
     std::string
     generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override
+            Addr pc, const loader::SymbolTable *symtab) const override
     {
         return csprintf("%-10s (unimplemented)", mnemonic);
     }
@@ -108,7 +108,7 @@ class WarnUnimplemented : public SparcStaticInst
 
     std::string
     generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override
+            Addr pc, const loader::SymbolTable *symtab) const override
     {
         return csprintf("%-10s (unimplemented)", mnemonic);
     }
diff --git a/src/arch/sparc/insts/unknown.hh b/src/arch/sparc/insts/unknown.hh
index f5c3b73185..da2b3eeda3 100644
--- a/src/arch/sparc/insts/unknown.hh
+++ b/src/arch/sparc/insts/unknown.hh
@@ -54,7 +54,7 @@ class Unknown : public SparcStaticInst
 
     std::string
     generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override
+            Addr pc, const loader::SymbolTable *symtab) const override
     {
         return "Unknown instruction";
     }
diff --git a/src/arch/sparc/linux/se_workload.cc b/src/arch/sparc/linux/se_workload.cc
index 1659163129..57961c93e0 100644
--- a/src/arch/sparc/linux/se_workload.cc
+++ b/src/arch/sparc/linux/se_workload.cc
@@ -43,23 +43,23 @@ class LinuxLoader : public Process::Loader
 {
   public:
     Process *
-    load(const ProcessParams &params, ::Loader::ObjectFile *obj) override
+    load(const ProcessParams &params, loader::ObjectFile *obj) override
     {
         auto arch = obj->getArch();
         auto opsys = obj->getOpSys();
 
-        if (arch != ::Loader::SPARC64 && arch != ::Loader::SPARC32)
+        if (arch != loader::SPARC64 && arch != loader::SPARC32)
             return nullptr;
 
-        if (opsys == ::Loader::UnknownOpSys) {
+        if (opsys == loader::UnknownOpSys) {
             warn("Unknown operating system; assuming Linux.");
-            opsys = ::Loader::Linux;
+            opsys = loader::Linux;
         }
 
-        if (opsys != ::Loader::Linux)
+        if (opsys != loader::Linux)
             return nullptr;
 
-        if (arch == ::Loader::SPARC64)
+        if (arch == loader::SPARC64)
             return new Sparc64Process(params, obj);
         else
             return new Sparc32Process(params, obj);
diff --git a/src/arch/sparc/linux/se_workload.hh b/src/arch/sparc/linux/se_workload.hh
index 1a0afef8c2..8c0401d350 100644
--- a/src/arch/sparc/linux/se_workload.hh
+++ b/src/arch/sparc/linux/se_workload.hh
@@ -54,7 +54,7 @@ class EmuLinux : public SEWorkload
 
     EmuLinux(const Params &p);
 
-    ::Loader::Arch getArch() const override { return ::Loader::SPARC64; }
+    loader::Arch getArch() const override { return loader::SPARC64; }
 
     void handleTrap(ThreadContext *tc, int trapNum) override;
     void syscall(ThreadContext *tc) override;
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index b2eece7f21..e28fb19f34 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -50,7 +50,7 @@
 using namespace SparcISA;
 
 SparcProcess::SparcProcess(const ProcessParams &params,
-                           ::Loader::ObjectFile *objFile, Addr _StackBias)
+                           loader::ObjectFile *objFile, Addr _StackBias)
     : Process(params,
               new EmulationPageTable(params.name, params.pid, PageBytes),
               objFile),
@@ -176,7 +176,7 @@ SparcProcess::argsInit(int pageSize)
 
     // Setup the auxilliary vectors. These will already have endian conversion.
     // Auxilliary vectors are loaded only for elf formatted executables.
-    auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile);
+    auto *elfObject = dynamic_cast<loader::ElfObject *>(objFile);
     if (elfObject) {
         // Bits which describe the system hardware capabilities
         auxv.emplace_back(gem5::auxv::Hwcap, hwcap);
diff --git a/src/arch/sparc/process.hh b/src/arch/sparc/process.hh
index 8c5bf1cfdd..84519ff225 100644
--- a/src/arch/sparc/process.hh
+++ b/src/arch/sparc/process.hh
@@ -47,7 +47,7 @@ class SparcProcess : public Process
     // The locations of the fill and spill handlers
     Addr fillStart, spillStart;
 
-    SparcProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile,
+    SparcProcess(const ProcessParams &params, loader::ObjectFile *objFile,
                  Addr _StackBias);
 
     void initState() override;
@@ -69,7 +69,7 @@ class Sparc32Process : public SparcProcess
 
   public:
 
-    Sparc32Process(const ProcessParams &params, ::Loader::ObjectFile *objFile)
+    Sparc32Process(const ProcessParams &params, loader::ObjectFile *objFile)
         : SparcProcess(params, objFile, 0)
     {
         Addr brk_point = image.maxAddr();
@@ -104,7 +104,7 @@ class Sparc64Process : public SparcProcess
 
   public:
 
-    Sparc64Process(const ProcessParams &params, ::Loader::ObjectFile *objFile)
+    Sparc64Process(const ProcessParams &params, loader::ObjectFile *objFile)
         : SparcProcess(params, objFile, 2047)
     {
         Addr brk_point = image.maxAddr();
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index 749e74337a..b1eea90bae 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -167,7 +167,7 @@ PageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
             panic("Tried to %s unmapped address %#x.\nPC: %#x, Instr: %s",
                   modeStr, addr, tc->pcState().pc(),
                   inst->disassemble(tc->pcState().pc(),
-                      &Loader::debugSymbolTable));
+                      &loader::debugSymbolTable));
         }
     }
 }
diff --git a/src/arch/x86/fs_workload.cc b/src/arch/x86/fs_workload.cc
index f9818c5370..8fa564db7c 100644
--- a/src/arch/x86/fs_workload.cc
+++ b/src/arch/x86/fs_workload.cc
@@ -122,7 +122,7 @@ FsWorkload::initState()
 
     fatal_if(!kernelObj, "No kernel to load.");
 
-    fatal_if(kernelObj->getArch() == Loader::I386,
+    fatal_if(kernelObj->getArch() == loader::I386,
              "Loading a 32 bit x86 kernel is not supported.");
 
     ThreadContext *tc = system->threads[0];
diff --git a/src/arch/x86/insts/macroop.hh b/src/arch/x86/insts/macroop.hh
index 5b27127e97..7e3b8906a0 100644
--- a/src/arch/x86/insts/macroop.hh
+++ b/src/arch/x86/insts/macroop.hh
@@ -83,7 +83,7 @@ class MacroopBase : public X86StaticInst
 
     std::string
     generateDisassembly(Addr pc,
-                        const Loader::SymbolTable *symtab) const override
+                        const loader::SymbolTable *symtab) const override
     {
         return mnemonic;
     }
diff --git a/src/arch/x86/insts/microdebug.hh b/src/arch/x86/insts/microdebug.hh
index b3af1e7827..6c4e5d2d64 100644
--- a/src/arch/x86/insts/microdebug.hh
+++ b/src/arch/x86/insts/microdebug.hh
@@ -53,7 +53,7 @@ class MicroDebug : public X86ISA::X86MicroopBase
 
     std::string
     generateDisassembly(Addr pc,
-                        const Loader::SymbolTable *symtab) const override
+                        const loader::SymbolTable *symtab) const override
     {
         std::stringstream response;
 
diff --git a/src/arch/x86/insts/microop.hh b/src/arch/x86/insts/microop.hh
index e71fcadfea..e3a2a56750 100644
--- a/src/arch/x86/insts/microop.hh
+++ b/src/arch/x86/insts/microop.hh
@@ -117,7 +117,7 @@ class X86MicroopBase : public X86StaticInst
 
     std::string
     generateDisassembly(Addr pc,
-                       const Loader::SymbolTable *symtab) const override
+                       const loader::SymbolTable *symtab) const override
     {
         std::stringstream ss;
 
diff --git a/src/arch/x86/insts/microop_args.hh b/src/arch/x86/insts/microop_args.hh
index f810a740a8..5e7f7c402b 100644
--- a/src/arch/x86/insts/microop_args.hh
+++ b/src/arch/x86/insts/microop_args.hh
@@ -364,7 +364,7 @@ class InstOperands : public Base, public Operands...
 
     std::string
     generateDisassembly(Addr pc,
-            const Loader::SymbolTable *symtab) const override
+            const loader::SymbolTable *symtab) const override
     {
         std::stringstream response;
         Base::printMnemonic(response, this->instMnem, this->mnemonic);
diff --git a/src/arch/x86/insts/static_inst.cc b/src/arch/x86/insts/static_inst.cc
index a0f3a6e339..6c90d50cdf 100644
--- a/src/arch/x86/insts/static_inst.cc
+++ b/src/arch/x86/insts/static_inst.cc
@@ -288,7 +288,7 @@ X86StaticInst::printMem(std::ostream &os, uint8_t segment,
 
 std::string
 X86StaticInst::generateDisassembly(
-        Addr pc, const Loader::SymbolTable *symtab) const
+        Addr pc, const loader::SymbolTable *symtab) const
 {
     std::stringstream ss;
 
diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh
index dc04a4f5be..92489dcf58 100644
--- a/src/arch/x86/insts/static_inst.hh
+++ b/src/arch/x86/insts/static_inst.hh
@@ -118,7 +118,7 @@ class X86StaticInst : public StaticInst
     {}
 
     std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const override;
+            Addr pc, const loader::SymbolTable *symtab) const override;
 
     static void divideStep(uint64_t divident, uint64_t divisor,
             uint64_t &quotient, uint64_t &remainder);
diff --git a/src/arch/x86/isa/formats/cpuid.isa b/src/arch/x86/isa/formats/cpuid.isa
index 0a9a015c21..b68b19e563 100644
--- a/src/arch/x86/isa/formats/cpuid.isa
+++ b/src/arch/x86/isa/formats/cpuid.isa
@@ -48,14 +48,14 @@ output header {{
         }
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const override;
+                const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string
     CPUIDInst::generateDisassembly(
-            Addr PC, const Loader::SymbolTable *symtab) const
+            Addr PC, const loader::SymbolTable *symtab) const
     {
         std::stringstream response;
 
diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa b/src/arch/x86/isa/formats/monitor_mwait.isa
index 2d25db113a..49a0158175 100644
--- a/src/arch/x86/isa/formats/monitor_mwait.isa
+++ b/src/arch/x86/isa/formats/monitor_mwait.isa
@@ -15,14 +15,14 @@ output header {{
         { }
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const override;
+                const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string
     MonitorInst::generateDisassembly(
-            Addr PC, const Loader::SymbolTable *symtab) const
+            Addr PC, const loader::SymbolTable *symtab) const
     {
         std::stringstream response;
 
@@ -97,14 +97,14 @@ output header {{
         }
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const override;
+                const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string
     MwaitInst::generateDisassembly(
-            Addr PC, const Loader::SymbolTable *symtab) const
+            Addr PC, const loader::SymbolTable *symtab) const
     {
         std::stringstream response;
 
diff --git a/src/arch/x86/isa/formats/nop.isa b/src/arch/x86/isa/formats/nop.isa
index 1f52c31eb5..c0f6e13082 100644
--- a/src/arch/x86/isa/formats/nop.isa
+++ b/src/arch/x86/isa/formats/nop.isa
@@ -54,13 +54,13 @@ output header {{
         }
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const override;
+                const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string NopInst::generateDisassembly(Addr PC,
-            const Loader::SymbolTable *symtab) const
+            const loader::SymbolTable *symtab) const
     {
         std::stringstream response;
 
diff --git a/src/arch/x86/isa/formats/syscall.isa b/src/arch/x86/isa/formats/syscall.isa
index 3044d3a1bd..28e1fcfb39 100644
--- a/src/arch/x86/isa/formats/syscall.isa
+++ b/src/arch/x86/isa/formats/syscall.isa
@@ -54,14 +54,14 @@ output header {{
         }
 
         std::string generateDisassembly(Addr pc,
-                const Loader::SymbolTable *symtab) const override;
+                const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string
     SyscallInst::generateDisassembly(
-            Addr PC, const Loader::SymbolTable *symtab) const
+            Addr PC, const loader::SymbolTable *symtab) const
     {
         std::stringstream response;
 
diff --git a/src/arch/x86/isa/formats/unimp.isa b/src/arch/x86/isa/formats/unimp.isa
index 066ca595e7..ac7fad7c6e 100644
--- a/src/arch/x86/isa/formats/unimp.isa
+++ b/src/arch/x86/isa/formats/unimp.isa
@@ -64,7 +64,7 @@ output header {{
 
         std::string
         generateDisassembly(Addr pc,
-                            const Loader::SymbolTable *symtab) const override;
+                            const loader::SymbolTable *symtab) const override;
     };
 
     /**
@@ -96,21 +96,21 @@ output header {{
 
         std::string
         generateDisassembly(Addr pc,
-                            const Loader::SymbolTable *symtab) const override;
+                            const loader::SymbolTable *symtab) const override;
     };
 }};
 
 output decoder {{
     std::string
     FailUnimplemented::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s (unimplemented)", mnemonic);
     }
 
     std::string
     WarnUnimplemented::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return csprintf("%-10s (unimplemented)", mnemonic);
     }
diff --git a/src/arch/x86/isa/formats/unknown.isa b/src/arch/x86/isa/formats/unknown.isa
index 9d1f5bf57a..3e0dc550da 100644
--- a/src/arch/x86/isa/formats/unknown.isa
+++ b/src/arch/x86/isa/formats/unknown.isa
@@ -58,7 +58,7 @@ output header {{
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
         std::string generateDisassembly(
-                Addr pc, const Loader::SymbolTable *symtab) const override;
+                Addr pc, const loader::SymbolTable *symtab) const override;
 
     };
 }};
@@ -66,7 +66,7 @@ output header {{
 output decoder {{
     std::string
     Unknown::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         return "Unknown instruction";
     }
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index 64c75b9571..97646ff5f5 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -91,7 +91,7 @@ def template MacroDeclare {{
             %(class_name)s(ExtMachInst machInst, X86ISA::EmulEnv _env);
 
             std::string generateDisassembly(
-                    Addr pc, const Loader::SymbolTable *symtab) const override;
+                    Addr pc, const loader::SymbolTable *symtab) const override;
         };
     }
 }};
@@ -99,7 +99,7 @@ def template MacroDeclare {{
 def template MacroDisassembly {{
     std::string
     x86_macroop::%(class_name)s::generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const
+            Addr pc, const loader::SymbolTable *symtab) const
     {
         std::stringstream out;
         out << mnemonic << "\t";
diff --git a/src/arch/x86/linux/se_workload.cc b/src/arch/x86/linux/se_workload.cc
index f00d5b39b9..1bb7d2c278 100644
--- a/src/arch/x86/linux/se_workload.cc
+++ b/src/arch/x86/linux/se_workload.cc
@@ -59,23 +59,23 @@ class LinuxLoader : public Process::Loader
 {
   public:
     Process *
-    load(const ProcessParams &params, ::Loader::ObjectFile *obj_file)
+    load(const ProcessParams &params, loader::ObjectFile *obj_file)
     {
         auto arch = obj_file->getArch();
         auto opsys = obj_file->getOpSys();
 
-        if (arch != ::Loader::X86_64 && arch != ::Loader::I386)
+        if (arch != loader::X86_64 && arch != loader::I386)
             return nullptr;
 
-        if (opsys == ::Loader::UnknownOpSys) {
+        if (opsys == loader::UnknownOpSys) {
             warn("Unknown operating system; assuming Linux.");
-            opsys = ::Loader::Linux;
+            opsys = loader::Linux;
         }
 
-        if (opsys != ::Loader::Linux)
+        if (opsys != loader::Linux)
             return nullptr;
 
-        if (arch == ::Loader::X86_64)
+        if (arch == loader::X86_64)
             return new X86ISA::X86_64Process(params, obj_file);
         else
             return new X86ISA::I386Process(params, obj_file);
diff --git a/src/arch/x86/linux/se_workload.hh b/src/arch/x86/linux/se_workload.hh
index 9bd6f75701..85c2cb3e0c 100644
--- a/src/arch/x86/linux/se_workload.hh
+++ b/src/arch/x86/linux/se_workload.hh
@@ -64,7 +64,7 @@ class EmuLinux : public SEWorkload
         gdb = BaseRemoteGDB::build<RemoteGDB>(system);
     }
 
-    ::Loader::Arch getArch() const override { return ::Loader::X86_64; }
+    ::loader::Arch getArch() const override { return ::loader::X86_64; }
 
     void syscall(ThreadContext *tc) override;
     void event(ThreadContext *tc) override;
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 4635639f9f..a35d063181 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -78,7 +78,7 @@ typedef MultiLevelPageTable<LongModePTE<47, 39>,
                             LongModePTE<20, 12> > ArchPageTable;
 
 X86Process::X86Process(const ProcessParams &params,
-                       ::Loader::ObjectFile *objFile) :
+                       loader::ObjectFile *objFile) :
     Process(params, params.useArchPT ?
                     static_cast<EmulationPageTable *>(
                             new ArchPageTable(params.name, params.pid,
@@ -98,7 +98,7 @@ void X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
 }
 
 X86_64Process::X86_64Process(const ProcessParams &params,
-                             ::Loader::ObjectFile *objFile) :
+                             loader::ObjectFile *objFile) :
     X86Process(params, objFile)
 {
     vsyscallPage.base = 0xffffffffff600000ULL;
@@ -119,7 +119,7 @@ X86_64Process::X86_64Process(const ProcessParams &params,
 
 
 I386Process::I386Process(const ProcessParams &params,
-                         ::Loader::ObjectFile *objFile) :
+                         loader::ObjectFile *objFile) :
     X86Process(params, objFile)
 {
     if (kvmInSE)
@@ -770,7 +770,7 @@ X86Process::argsInit(int pageSize,
     // conversion. Auxiliary vectors are loaded only for elf formatted
     // executables; the auxv is responsible for passing information from
     // the OS to the interpreter.
-    auto *elfObject = dynamic_cast<::Loader::ElfObject *>(objFile);
+    auto *elfObject = dynamic_cast<loader::ElfObject *>(objFile);
     if (elfObject) {
         uint64_t features =
             X86_OnboardFPU |
diff --git a/src/arch/x86/process.hh b/src/arch/x86/process.hh
index 8585f94bcb..0724029b2c 100644
--- a/src/arch/x86/process.hh
+++ b/src/arch/x86/process.hh
@@ -67,7 +67,7 @@ namespace X86ISA
         Addr _gdtStart;
         Addr _gdtSize;
 
-        X86Process(const ProcessParams &params, ::Loader::ObjectFile *objFile);
+        X86Process(const ProcessParams &params, loader::ObjectFile *objFile);
 
         template<class IntType>
         void argsInit(int pageSize,
@@ -122,7 +122,7 @@ namespace X86ISA
 
       public:
         X86_64Process(const ProcessParams &params,
-                      ::Loader::ObjectFile *objFile);
+                      loader::ObjectFile *objFile);
 
         void argsInit(int pageSize);
         void initState() override;
@@ -160,7 +160,7 @@ namespace X86ISA
 
       public:
         I386Process(const ProcessParams &params,
-                    ::Loader::ObjectFile *objFile);
+                    loader::ObjectFile *objFile);
 
         const VSyscallPage &getVSyscallPage() const { return vsyscallPage; }
 
diff --git a/src/arch/x86/remote_gdb.cc b/src/arch/x86/remote_gdb.cc
index 9f8495d442..7570370a25 100644
--- a/src/arch/x86/remote_gdb.cc
+++ b/src/arch/x86/remote_gdb.cc
@@ -98,13 +98,13 @@ RemoteGDB::gdbRegs()
     // on the architecture reported by the workload.
     if (system()->workload) {
         auto arch = system()->workload->getArch();
-        if (arch == Loader::X86_64) {
+        if (arch == loader::X86_64) {
             return &regCache64;
-        } else if (arch == Loader::I386) {
+        } else if (arch == loader::I386) {
             return &regCache32;
-        } else if (arch != Loader::UnknownArch) {
+        } else if (arch != loader::UnknownArch) {
             panic("Unrecognized workload arch %s.",
-                    Loader::archToString(arch));
+                    loader::archToString(arch));
         }
     }
 
diff --git a/src/base/loader/dtb_file.cc b/src/base/loader/dtb_file.cc
index 7405cfe7b8..db657d30ce 100644
--- a/src/base/loader/dtb_file.cc
+++ b/src/base/loader/dtb_file.cc
@@ -37,7 +37,8 @@
 #include "libfdt.h"
 #include "sim/byteswap.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 DtbFile::DtbFile(const std::string &filename) :
@@ -156,4 +157,4 @@ DtbFile::buildImage() const
         return {{ "data", 0, fileData, length }};
 }
 
-} // namespace Loader
+} // namespace loader
diff --git a/src/base/loader/dtb_file.hh b/src/base/loader/dtb_file.hh
index 3a9d724539..1bc2ccd3de 100644
--- a/src/base/loader/dtb_file.hh
+++ b/src/base/loader/dtb_file.hh
@@ -29,9 +29,11 @@
 #ifndef __BASE_LOADER_DTB_FILE_HH__
 #define __BASE_LOADER_DTB_FILE_HH__
 
+#include "base/compiler.hh"
 #include "base/loader/image_file.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 /** @file
@@ -70,6 +72,6 @@ class DtbFile : public ImageFile
     MemoryImage buildImage() const override;
 };
 
-} // namespace Loader
+} // namespace loader
 
 #endif //__BASE_LOADER_DTB_FILE_HH__
diff --git a/src/base/loader/elf_object.cc b/src/base/loader/elf_object.cc
index b9d8bd5897..489a4c0356 100644
--- a/src/base/loader/elf_object.cc
+++ b/src/base/loader/elf_object.cc
@@ -58,7 +58,8 @@
 #include "gelf.h"
 #include "sim/byteswap.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 ObjectFile *
@@ -174,19 +175,19 @@ ElfObject::ElfObject(ImageFileDataPtr ifd) : ObjectFile(ifd)
                 if (!sym_name || sym_name[0] == '$')
                     continue;
 
-                Loader::Symbol symbol;
+                loader::Symbol symbol;
                 symbol.address = sym.st_value;
                 symbol.name = sym_name;
 
                 switch (GELF_ST_BIND(sym.st_info)) {
                   case STB_GLOBAL:
-                    symbol.binding = Loader::Symbol::Binding::Global;
+                    symbol.binding = loader::Symbol::Binding::Global;
                     break;
                   case STB_LOCAL:
-                    symbol.binding = Loader::Symbol::Binding::Local;
+                    symbol.binding = loader::Symbol::Binding::Local;
                     break;
                   case STB_WEAK:
-                    symbol.binding = Loader::Symbol::Binding::Weak;
+                    symbol.binding = loader::Symbol::Binding::Weak;
                     break;
                   default:
                     continue;
@@ -421,4 +422,4 @@ ElfObject::updateBias(Addr bias_addr)
     image.offset(bias_addr);
 }
 
-} // namespace Loader
+} // namespace loader
diff --git a/src/base/loader/elf_object.hh b/src/base/loader/elf_object.hh
index c262912af5..797ff1f8e3 100644
--- a/src/base/loader/elf_object.hh
+++ b/src/base/loader/elf_object.hh
@@ -44,10 +44,12 @@
 #include <set>
 #include <vector>
 
+#include "base/compiler.hh"
 #include "base/loader/object_file.hh"
 #include "gelf.h"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 class ElfObjectFormat : public ObjectFileFormat
@@ -130,6 +132,6 @@ class ElfObject : public ObjectFile
  */
 void setInterpDir(const std::string &dirname);
 
-} // namespace Loader
+} // namespace loader
 
 #endif // __BASE_LOADER_ELF_OBJECT_HH__
diff --git a/src/base/loader/image_file.hh b/src/base/loader/image_file.hh
index 9894f8212b..0d87c5ebd9 100644
--- a/src/base/loader/image_file.hh
+++ b/src/base/loader/image_file.hh
@@ -32,10 +32,12 @@
 #include <cstdint>
 #include <string>
 
+#include "base/compiler.hh"
 #include "base/loader/image_file_data.hh"
 #include "base/loader/memory_image.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 class ImageFile
@@ -49,6 +51,6 @@ class ImageFile
     virtual MemoryImage buildImage() const = 0;
 };
 
-} // namespace Loader
+} // namespace loader
 
 #endif // __BASE_LOADER_IMAGE_FILE_HH__
diff --git a/src/base/loader/image_file_data.cc b/src/base/loader/image_file_data.cc
index a94d3c6e53..dc6cb9096d 100644
--- a/src/base/loader/image_file_data.cc
+++ b/src/base/loader/image_file_data.cc
@@ -39,7 +39,8 @@
 
 #include "base/logging.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 static bool
@@ -129,4 +130,4 @@ ImageFileData::~ImageFileData()
     munmap((void *)_data, _len);
 }
 
-} // namespace Loader
+} // namespace loader
diff --git a/src/base/loader/image_file_data.hh b/src/base/loader/image_file_data.hh
index 5745348f0c..681dfa6f20 100644
--- a/src/base/loader/image_file_data.hh
+++ b/src/base/loader/image_file_data.hh
@@ -33,7 +33,10 @@
 #include <memory>
 #include <string>
 
-namespace Loader
+#include "base/compiler.hh"
+
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 class ImageFileData
@@ -54,6 +57,6 @@ class ImageFileData
 
 typedef std::shared_ptr<ImageFileData> ImageFileDataPtr;
 
-} // namespace Loader
+} // namespace loader
 
 #endif // __BASE_LOADER_IMAGE_FILE_DATA_HH__
diff --git a/src/base/loader/image_file_data.test.cc b/src/base/loader/image_file_data.test.cc
index 0ca96ee606..2ab4bf1fc3 100644
--- a/src/base/loader/image_file_data.test.cc
+++ b/src/base/loader/image_file_data.test.cc
@@ -35,7 +35,7 @@
 #include "base/loader/image_file_data.hh"
 #include "base/loader/small_image_file.test.hh"
 
-using namespace Loader;
+using namespace loader;
 
 TEST(ImageFileDataTest, SimpleImage)
 {
diff --git a/src/base/loader/memory_image.cc b/src/base/loader/memory_image.cc
index feedac6d01..83b6c91124 100644
--- a/src/base/loader/memory_image.cc
+++ b/src/base/loader/memory_image.cc
@@ -29,7 +29,8 @@
 #include "base/loader/memory_image.hh"
 #include "mem/port_proxy.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 bool
@@ -63,4 +64,4 @@ MemoryImage::move(std::function<Addr(Addr)> mapper)
     return *this;
 }
 
-} // namespace Loader
+} // namespace loader
diff --git a/src/base/loader/memory_image.hh b/src/base/loader/memory_image.hh
index e0e1e630f8..075204528f 100644
--- a/src/base/loader/memory_image.hh
+++ b/src/base/loader/memory_image.hh
@@ -36,13 +36,15 @@
 #include <string>
 #include <vector>
 
+#include "base/compiler.hh"
 #include "base/loader/image_file_data.hh"
 #include "base/logging.hh"
 #include "base/types.hh"
 
 class PortProxy;
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 class MemoryImage
@@ -165,6 +167,6 @@ operator << (std::ostream &os, const MemoryImage::Segment &seg)
     return os;
 }
 
-} // namespace Loader
+} // namespace loader
 
 #endif // __BASE_LOADER_MEMORY_IMAGE_HH__
diff --git a/src/base/loader/object_file.cc b/src/base/loader/object_file.cc
index 6fdf228d4f..3778a8a692 100644
--- a/src/base/loader/object_file.cc
+++ b/src/base/loader/object_file.cc
@@ -33,7 +33,8 @@
 
 #include "base/loader/raw_image.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 ObjectFile::ObjectFile(ImageFileDataPtr ifd) : ImageFile(ifd) {}
@@ -128,4 +129,4 @@ createObjectFile(const std::string &fname, bool raw)
     return nullptr;
 }
 
-} // namespace Loader
+} // namespace loader
diff --git a/src/base/loader/object_file.hh b/src/base/loader/object_file.hh
index c734f9d356..443dfb9274 100644
--- a/src/base/loader/object_file.hh
+++ b/src/base/loader/object_file.hh
@@ -31,6 +31,7 @@
 
 #include <string>
 
+#include "base/compiler.hh"
 #include "base/loader/image_file.hh"
 #include "base/loader/image_file_data.hh"
 #include "base/loader/memory_image.hh"
@@ -38,7 +39,8 @@
 #include "base/logging.hh"
 #include "base/types.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 enum Arch
@@ -128,6 +130,6 @@ class ObjectFileFormat
 
 ObjectFile *createObjectFile(const std::string &fname, bool raw=false);
 
-} // namespace Loader
+} // namespace loader
 
 #endif // __BASE_LOADER_OBJECT_FILE_HH__
diff --git a/src/base/loader/raw_image.hh b/src/base/loader/raw_image.hh
index 40f7685717..7dcbf889cc 100644
--- a/src/base/loader/raw_image.hh
+++ b/src/base/loader/raw_image.hh
@@ -29,9 +29,11 @@
 #ifndef __BASE_LOADER_RAW_IMAGE_HH__
 #define __BASE_LOADER_RAW_IMAGE_HH__
 
+#include "base/compiler.hh"
 #include "base/loader/object_file.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 class RawImage: public ObjectFile
@@ -50,6 +52,6 @@ class RawImage: public ObjectFile
     }
 };
 
-} // namespace Loader
+} // namespace loader
 
 #endif // __BASE_LOADER_RAW_IMAGE_HH__
diff --git a/src/base/loader/symtab.cc b/src/base/loader/symtab.cc
index 0d0e82615e..32b7d00e0a 100644
--- a/src/base/loader/symtab.cc
+++ b/src/base/loader/symtab.cc
@@ -34,7 +34,8 @@
 #include "base/logging.hh"
 #include "base/str.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 SymbolTable debugSymbolTable;
@@ -119,4 +120,4 @@ SymbolTable::unserialize(const std::string &base, CheckpointIn &cp,
     }
 }
 
-} // namespace Loader
+} // namespace loader
diff --git a/src/base/loader/symtab.hh b/src/base/loader/symtab.hh
index 7402a89e37..03fbb8e244 100644
--- a/src/base/loader/symtab.hh
+++ b/src/base/loader/symtab.hh
@@ -36,10 +36,12 @@
 #include <string>
 #include <vector>
 
+#include "base/compiler.hh"
 #include "base/types.hh"
 #include "sim/serialize.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 
 struct Symbol
@@ -251,6 +253,6 @@ class SymbolTable
 /// global one has worked well enough.
 extern SymbolTable debugSymbolTable;
 
-} // namespace Loader
+} // namespace loader
 
 #endif // __BASE_LOADER_SYMTAB_HH__
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 21206719d5..2a715ebae4 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -699,17 +699,17 @@ bool AddressMonitor::doMonitor(PacketPtr pkt) {
 void
 BaseCPU::traceFunctionsInternal(Addr pc)
 {
-    if (Loader::debugSymbolTable.empty())
+    if (loader::debugSymbolTable.empty())
         return;
 
     // if pc enters different function, print new function symbol and
     // update saved range.  Otherwise do nothing.
     if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
-        auto it = Loader::debugSymbolTable.findNearest(
+        auto it = loader::debugSymbolTable.findNearest(
                 pc, currentFunctionEnd);
 
         std::string sym_str;
-        if (it == Loader::debugSymbolTable.end()) {
+        if (it == loader::debugSymbolTable.end()) {
             // no symbol found: use addr as label
             sym_str = csprintf("%#x", pc);
             currentFunctionStart = pc;
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index cd70f1c0cf..9a6b1e7dc8 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -74,11 +74,11 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
         outs << "T" << thread->threadId() << " : ";
 
     Addr cur_pc = pc.instAddr();
-    Loader::SymbolTable::const_iterator it;
+    loader::SymbolTable::const_iterator it;
     ccprintf(outs, "%#x", cur_pc);
     if (Debug::ExecSymbol && (!FullSystem || !in_user_mode) &&
-            (it = Loader::debugSymbolTable.findNearest(cur_pc)) !=
-                Loader::debugSymbolTable.end()) {
+            (it = loader::debugSymbolTable.findNearest(cur_pc)) !=
+                loader::debugSymbolTable.end()) {
         Addr delta = cur_pc - it->address;
         if (delta)
             ccprintf(outs, " @%s+%d", it->name, delta);
@@ -99,7 +99,7 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
     //
 
     outs << std::setw(26) << std::left;
-    outs << inst->disassemble(cur_pc, &Loader::debugSymbolTable);
+    outs << inst->disassemble(cur_pc, &loader::debugSymbolTable);
 
     if (ran) {
         outs << " : ";
diff --git a/src/cpu/nop_static_inst.cc b/src/cpu/nop_static_inst.cc
index bc40227e2a..be761096f6 100644
--- a/src/cpu/nop_static_inst.cc
+++ b/src/cpu/nop_static_inst.cc
@@ -52,7 +52,7 @@ class NopStaticInst : public StaticInst
 
     std::string
     generateDisassembly(Addr pc,
-            const Loader::SymbolTable *symtab) const override
+            const loader::SymbolTable *symtab) const override
     {
         return mnemonic;
     }
diff --git a/src/cpu/profile.cc b/src/cpu/profile.cc
index d132fc1388..cf65160713 100644
--- a/src/cpu/profile.cc
+++ b/src/cpu/profile.cc
@@ -55,7 +55,7 @@ BaseStackTrace::dump()
 
 bool
 BaseStackTrace::tryGetSymbol(std::string &symbol, Addr addr,
-                             const Loader::SymbolTable *symtab)
+                             const loader::SymbolTable *symtab)
 {
     const auto it = symtab->find(addr);
     if (it == symtab->end())
@@ -94,7 +94,7 @@ ProfileNode::clear()
 }
 
 FunctionProfile::FunctionProfile(std::unique_ptr<BaseStackTrace> _trace,
-                                 const Loader::SymbolTable &_symtab) :
+                                 const loader::SymbolTable &_symtab) :
     symtab(_symtab), trace(std::move(_trace))
 {
     Stats::registerResetCallback([this]() { clear(); });
diff --git a/src/cpu/profile.hh b/src/cpu/profile.hh
index f29bdae611..922ac800d6 100644
--- a/src/cpu/profile.hh
+++ b/src/cpu/profile.hh
@@ -40,10 +40,11 @@
 class ThreadContext;
 class FunctionProfile;
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
     class SymbolTable;
-} // Loader
+} // namespace loader
 
 class BaseStackTrace
 {
@@ -96,11 +97,11 @@ class BaseStackTrace
     // It should return whether addr was recognized and symbol has been set to
     // something.
     virtual bool tryGetSymbol(std::string &symbol, Addr addr,
-                              const Loader::SymbolTable *symtab);
+                              const loader::SymbolTable *symtab);
 
     void
     getSymbol(std::string &symbol, Addr addr,
-              const Loader::SymbolTable *symtab)
+              const loader::SymbolTable *symtab)
     {
         panic_if(!tryGetSymbol(symbol, addr, symtab),
                  "Could not find symbol for address %#x\n", addr);
@@ -129,14 +130,14 @@ class FunctionProfile
   private:
     friend class ProfileNode;
 
-    const Loader::SymbolTable &symtab;
+    const loader::SymbolTable &symtab;
     ProfileNode top;
     std::map<Addr, Counter> pc_count;
     std::unique_ptr<BaseStackTrace> trace;
 
   public:
     FunctionProfile(std::unique_ptr<BaseStackTrace> _trace,
-                    const Loader::SymbolTable &symtab);
+                    const loader::SymbolTable &symtab);
 
     ProfileNode *consume(ThreadContext *tc, const StaticInstPtr &inst);
     ProfileNode *consume(const std::vector<Addr> &stack);
diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc
index c389f215fc..4af450bf75 100644
--- a/src/cpu/static_inst.cc
+++ b/src/cpu/static_inst.cc
@@ -69,7 +69,7 @@ StaticInst::branchTarget(ThreadContext *tc) const
 }
 
 const std::string &
-StaticInst::disassemble(Addr pc, const Loader::SymbolTable *symtab) const
+StaticInst::disassemble(Addr pc, const loader::SymbolTable *symtab) const
 {
     if (!cachedDisassembly) {
         cachedDisassembly =
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 49a82431a2..2af6a0b1d9 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -63,10 +63,11 @@ class Packet;
 class ExecContext;
 class ThreadContext;
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 class SymbolTable;
-} // namespace Loader
+} // namespace loader
 
 namespace Trace
 {
@@ -286,7 +287,7 @@ class StaticInst : public RefCounted, public StaticInstFlags
      * Internal function to generate disassembly string.
      */
     virtual std::string generateDisassembly(
-            Addr pc, const Loader::SymbolTable *symtab) const = 0;
+            Addr pc, const loader::SymbolTable *symtab) const = 0;
 
     /// Constructor.
     /// It's important to initialize everything here to a sane
@@ -362,7 +363,7 @@ class StaticInst : public RefCounted, public StaticInstFlags
      * should not be cached, this function should be overridden directly.
      */
     virtual const std::string &disassemble(Addr pc,
-        const Loader::SymbolTable *symtab=nullptr) const;
+        const loader::SymbolTable *symtab=nullptr) const;
 
     /**
      * Print a separator separated list of this instruction's set flag
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index e5365920c8..bcb69147fc 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -74,11 +74,11 @@ AbstractMemory::initState()
     if (file == "")
         return;
 
-    auto *object = Loader::createObjectFile(file, true);
+    auto *object = loader::createObjectFile(file, true);
     fatal_if(!object, "%s: Could not load %s.", name(), file);
 
-    Loader::debugSymbolTable.insert(*object->symtab().globals());
-    Loader::MemoryImage image = object->buildImage();
+    loader::debugSymbolTable.insert(*object->symtab().globals());
+    loader::MemoryImage image = object->buildImage();
 
     AddrRange image_range(image.minAddr(), image.maxAddr());
     if (!range.contains(image_range.start())) {
diff --git a/src/python/pybind11/core.cc b/src/python/pybind11/core.cc
index dbd8a0fbbb..883a7bf60f 100644
--- a/src/python/pybind11/core.cc
+++ b/src/python/pybind11/core.cc
@@ -205,7 +205,7 @@ init_loader(py::module_ &m_native)
 {
     py::module_ m = m_native.def_submodule("loader");
 
-    m.def("setInterpDir", &Loader::setInterpDir);
+    m.def("setInterpDir", &loader::setInterpDir);
 }
 
 void
diff --git a/src/python/pybind11/object_file.cc b/src/python/pybind11/object_file.cc
index 2c7fa65c95..dbbeb9d602 100644
--- a/src/python/pybind11/object_file.cc
+++ b/src/python/pybind11/object_file.cc
@@ -39,18 +39,18 @@ objectfile_pybind(py::module_ &m_internal)
 {
     py::module_ m = m_internal.def_submodule("object_file");
 
-    py::class_<Loader::ObjectFile>(m, "ObjectFile")
-        .def("get_arch", [](const Loader::ObjectFile &obj) {
-                return Loader::archToString(obj.getArch());
+    py::class_<loader::ObjectFile>(m, "ObjectFile")
+        .def("get_arch", [](const loader::ObjectFile &obj) {
+                return loader::archToString(obj.getArch());
                 }, py::return_value_policy::reference)
-        .def("get_op_sys", [](const Loader::ObjectFile &obj) {
-                return Loader::opSysToString(obj.getOpSys());
+        .def("get_op_sys", [](const loader::ObjectFile &obj) {
+                return loader::opSysToString(obj.getOpSys());
                 }, py::return_value_policy::reference)
-        .def("entry_point", &Loader::ObjectFile::entryPoint)
-        .def("get_interpreter", &Loader::ObjectFile::getInterpreter);
+        .def("entry_point", &loader::ObjectFile::entryPoint)
+        .def("get_interpreter", &loader::ObjectFile::getInterpreter);
 
     m.def("create", [](const std::string &fname) {
-            return Loader::createObjectFile(fname); });
+            return loader::createObjectFile(fname); });
 }
 EmbeddedPyBind embed_("object_file", &objectfile_pybind);
 
diff --git a/src/sim/kernel_workload.cc b/src/sim/kernel_workload.cc
index 62e94550d9..cfe4816c3e 100644
--- a/src/sim/kernel_workload.cc
+++ b/src/sim/kernel_workload.cc
@@ -39,7 +39,7 @@ KernelWorkload::KernelWorkload(const Params &p) : Workload(p),
         inform("No kernel set for full system simulation. "
                "Assuming you know what you're doing.");
     } else {
-        kernelObj = Loader::createObjectFile(params().object_file);
+        kernelObj = loader::createObjectFile(params().object_file);
         inform("kernel located at: %s", params().object_file);
 
         fatal_if(!kernelObj,
@@ -67,8 +67,8 @@ KernelWorkload::KernelWorkload(const Params &p) : Workload(p),
                 name = "kernel_init." + name;
             });
 
-        Loader::debugSymbolTable.insert(*initKernelSymtab);
-        Loader::debugSymbolTable.insert(kernelSymtab);
+        loader::debugSymbolTable.insert(*initKernelSymtab);
+        loader::debugSymbolTable.insert(kernelSymtab);
     }
 
     // Loading only needs to happen once and after memory system is
@@ -82,7 +82,7 @@ KernelWorkload::KernelWorkload(const Params &p) : Workload(p),
     for (int ker_idx = 0; ker_idx < p.extras.size(); ker_idx++) {
         const std::string &obj_name = p.extras[ker_idx];
         const bool raw = extras_addrs[ker_idx] != MaxAddr;
-        auto *obj = Loader::createObjectFile(obj_name, raw);
+        auto *obj = loader::createObjectFile(obj_name, raw);
         fatal_if(!obj, "Failed to build additional kernel object '%s'.\n",
                  obj_name);
         extras.push_back(obj);
diff --git a/src/sim/kernel_workload.hh b/src/sim/kernel_workload.hh
index c8e3a53ac6..dfbbcb003d 100644
--- a/src/sim/kernel_workload.hh
+++ b/src/sim/kernel_workload.hh
@@ -42,7 +42,7 @@ class System;
 class KernelWorkload : public Workload
 {
   protected:
-    Loader::MemoryImage image;
+    loader::MemoryImage image;
 
     /** Mask that should be anded for binary/symbol loading.
      * This allows one two different OS requirements for the same ISA to be
@@ -61,12 +61,12 @@ class KernelWorkload : public Workload
 
     Addr _start, _end;
 
-    std::vector<Loader::ObjectFile *> extras;
+    std::vector<loader::ObjectFile *> extras;
 
-    Loader::ObjectFile *kernelObj = nullptr;
+    loader::ObjectFile *kernelObj = nullptr;
     // Keep a separate copy of the kernel's symbol table so we can add things
     // to it.
-    Loader::SymbolTable kernelSymtab;
+    loader::SymbolTable kernelSymtab;
 
     const std::string commandLine;
 
@@ -81,20 +81,20 @@ class KernelWorkload : public Workload
     KernelWorkload(const Params &p);
 
     Addr getEntry() const override { return kernelObj->entryPoint(); }
-    Loader::Arch
+    loader::Arch
     getArch() const override
     {
         return kernelObj->getArch();
     }
 
-    const Loader::SymbolTable &
+    const loader::SymbolTable &
     symtab(ThreadContext *tc) override
     {
         return kernelSymtab;
     }
 
     bool
-    insertSymbol(const Loader::Symbol &symbol) override
+    insertSymbol(const loader::Symbol &symbol) override
     {
         return kernelSymtab.insert(symbol);
     }
diff --git a/src/sim/process.cc b/src/sim/process.cc
index ee7624a8f3..86f84ebc97 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -87,10 +87,10 @@ Process::Loader::Loader()
 
 Process *
 Process::tryLoaders(const ProcessParams &params,
-                    ::Loader::ObjectFile *obj_file)
+                    loader::ObjectFile *obj_file)
 {
-    for (auto &loader: process_loaders()) {
-        Process *p = loader->load(params, obj_file);
+    for (auto &loader_it : process_loaders()) {
+        Process *p = loader_it->load(params, obj_file);
         if (p)
             return p;
     }
@@ -107,7 +107,7 @@ normalize(const std::string& directory)
 }
 
 Process::Process(const ProcessParams &params, EmulationPageTable *pTable,
-                 ::Loader::ObjectFile *obj_file)
+                 loader::ObjectFile *obj_file)
     : SimObject(params), system(params.system),
       useArchPT(params.useArchPT),
       kvmInSE(params.kvmInSE),
@@ -155,8 +155,8 @@ Process::Process(const ProcessParams &params, EmulationPageTable *pTable,
 
     image = objFile->buildImage();
 
-    if (::Loader::debugSymbolTable.empty())
-        ::Loader::debugSymbolTable = objFile->symtab();
+    if (loader::debugSymbolTable.empty())
+        loader::debugSymbolTable = objFile->symtab();
 }
 
 void
@@ -459,7 +459,7 @@ Process::updateBias()
     interp->updateBias(ld_bias);
 }
 
-Loader::ObjectFile *
+loader::ObjectFile *
 Process::getInterpreter()
 {
     return objFile->getInterpreter();
@@ -515,7 +515,7 @@ ProcessParams::create() const
     // simulated system's zeroth command line parameter
     const std::string &exec = (executable == "") ? cmd[0] : executable;
 
-    auto *obj_file = Loader::createObjectFile(exec);
+    auto *obj_file = loader::createObjectFile(exec);
     fatal_if(!obj_file, "Cannot load object file %s.", exec);
 
     Process *process = Process::tryLoaders(*this, obj_file);
diff --git a/src/sim/process.hh b/src/sim/process.hh
index 9dc5f22ff7..44b0bff676 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -46,10 +46,11 @@
 #include "sim/mem_state.hh"
 #include "sim/sim_object.hh"
 
-namespace Loader
+GEM5_DEPRECATED_NAMESPACE(Loader, loader);
+namespace loader
 {
 class ObjectFile;
-} // namespace Loader
+} // namespace loader
 
 struct ProcessParams;
 
@@ -64,7 +65,7 @@ class Process : public SimObject
 {
   public:
     Process(const ProcessParams &params, EmulationPageTable *pTable,
-            ::Loader::ObjectFile *obj_file);
+            loader::ObjectFile *obj_file);
 
     void serialize(CheckpointOut &cp) const override;
     void unserialize(CheckpointIn &cp) override;
@@ -101,7 +102,7 @@ class Process : public SimObject
     void updateBias();
     Addr getBias();
     Addr getStartPC();
-    ::Loader::ObjectFile *getInterpreter();
+    loader::ObjectFile *getInterpreter();
 
     void allocateMem(Addr vaddr, int64_t size, bool clobber = false);
 
@@ -195,17 +196,17 @@ class Process : public SimObject
          * with a panic or fail as normal.
          */
         virtual Process *load(const ProcessParams &params,
-                              ::Loader::ObjectFile *obj_file) = 0;
+                              loader::ObjectFile *obj_file) = 0;
     };
 
     // Try all the Loader instance's "load" methods one by one until one is
     // successful. If none are, complain and fail.
     static Process *tryLoaders(const ProcessParams &params,
-                               ::Loader::ObjectFile *obj_file);
+                               loader::ObjectFile *obj_file);
 
-    ::Loader::ObjectFile *objFile;
-    ::Loader::MemoryImage image;
-    ::Loader::MemoryImage interpImage;
+    loader::ObjectFile *objFile;
+    loader::MemoryImage image;
+    loader::MemoryImage interpImage;
     std::vector<std::string> argv;
     std::vector<std::string> envp;
     std::string executable;
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 8a3ff2a68d..4b8db3e823 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -239,7 +239,7 @@ loadsymbol(ThreadContext *tc)
             continue;
 
         if (!tc->getSystemPtr()->workload->insertSymbol(
-                    { Loader::Symbol::Binding::Global, symbol, addr })) {
+                    { loader::Symbol::Binding::Global, symbol, addr })) {
             continue;
         }
 
@@ -261,9 +261,9 @@ addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
     DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
 
     tc->getSystemPtr()->workload->insertSymbol(
-            { Loader::Symbol::Binding::Global, symbol, addr });
-    Loader::debugSymbolTable.insert(
-            { Loader::Symbol::Binding::Global, symbol, addr });
+            { loader::Symbol::Binding::Global, symbol, addr });
+    loader::debugSymbolTable.insert(
+            { loader::Symbol::Binding::Global, symbol, addr });
 }
 
 uint64_t
diff --git a/src/sim/se_workload.hh b/src/sim/se_workload.hh
index 50c35ddbd4..2edc08612b 100644
--- a/src/sim/se_workload.hh
+++ b/src/sim/se_workload.hh
@@ -46,7 +46,7 @@ class SEWorkload : public Workload
         panic("No workload entry point for syscall emulation mode.");
     }
 
-    Loader::Arch
+    loader::Arch
     getArch() const override
     {
         // ISA specific subclasses should implement this method.
@@ -55,7 +55,7 @@ class SEWorkload : public Workload
         panic("SEWorkload::getArch() not implemented.");
     }
 
-    const Loader::SymbolTable &
+    const loader::SymbolTable &
     symtab(ThreadContext *) override
     {
         // This object represents the OS, not the individual processes running
@@ -64,7 +64,7 @@ class SEWorkload : public Workload
     }
 
     bool
-    insertSymbol(const Loader::Symbol &symbol) override
+    insertSymbol(const loader::Symbol &symbol) override
     {
         // This object represents the OS, not the individual processes running
         // within it.
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index b21d1b68b8..54e92b218b 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1696,14 +1696,14 @@ mmapFunc(SyscallDesc *desc, ThreadContext *tc,
         if (p->interpImage.contains(tc->pcState().instAddr())) {
             std::shared_ptr<FDEntry> fdep = (*p->fds)[tgt_fd];
             auto ffdp = std::dynamic_pointer_cast<FileFDEntry>(fdep);
-            auto *lib = Loader::createObjectFile(p->checkPathRedirect(
+            auto *lib = loader::createObjectFile(p->checkPathRedirect(
                     ffdp->getFileName()));
             DPRINTF_SYSCALL(Verbose, "Loading symbols from %s\n",
                 ffdp->getFileName());
 
             if (lib) {
                 Addr offset = lib->buildImage().minAddr() + start;
-                Loader::debugSymbolTable.insert(*lib->symtab().offset(offset));
+                loader::debugSymbolTable.insert(*lib->symtab().offset(offset));
             }
         }
     }
diff --git a/src/sim/workload.hh b/src/sim/workload.hh
index 5fc0daa4df..bec5aaab4b 100644
--- a/src/sim/workload.hh
+++ b/src/sim/workload.hh
@@ -93,10 +93,10 @@ class Workload : public SimObject
     void startup() override;
 
     virtual Addr getEntry() const = 0;
-    virtual Loader::Arch getArch() const = 0;
+    virtual loader::Arch getArch() const = 0;
 
-    virtual const Loader::SymbolTable &symtab(ThreadContext *tc) = 0;
-    virtual bool insertSymbol(const Loader::Symbol &symbol) = 0;
+    virtual const loader::SymbolTable &symtab(ThreadContext *tc) = 0;
+    virtual bool insertSymbol(const loader::Symbol &symbol) = 0;
 
     virtual void
     syscall(ThreadContext *tc)
@@ -125,7 +125,7 @@ class Workload : public SimObject
      */
     template <class T, typename... Args>
     T *
-    addFuncEvent(const Loader::SymbolTable &symtab, const char *lbl,
+    addFuncEvent(const loader::SymbolTable &symtab, const char *lbl,
                  const std::string &desc, Args... args)
     {
         auto it = symtab.find(lbl);
@@ -138,14 +138,14 @@ class Workload : public SimObject
 
     template <class T>
     T *
-    addFuncEvent(const Loader::SymbolTable &symtab, const char *lbl)
+    addFuncEvent(const loader::SymbolTable &symtab, const char *lbl)
     {
         return addFuncEvent<T>(symtab, lbl, lbl);
     }
 
     template <class T, typename... Args>
     T *
-    addFuncEventOrPanic(const Loader::SymbolTable &symtab, const char *lbl,
+    addFuncEventOrPanic(const loader::SymbolTable &symtab, const char *lbl,
                         Args... args)
     {
         T *e = addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...);