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mem: format address in hex in the memory controller debug trace

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Before it was using the decimal format contrary to
everywhere else in gem5.
This was making it difficult to follow an address in the trace
once going to main memory.

Change-Id: Ia0e7d1624b593d8a21d5b3563893e2c0bcc8ed1c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47043
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Nathanael Premillieu
2021-06-04 16:06:37 +02:00
parent 5269c0931c
commit 40cb501a2f
3 changed files with 15 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/mem/mem_ctrl.cc
View File

@@ -234,7 +234,7 @@ MemCtrl::addToReadQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram)
stats.servicedByWrQ++;
pktsServicedByWrQ++;
DPRINTF(MemCtrl,
"Read to addr %lld with size %d serviced by "
"Read to addr %#x with size %d serviced by "
"write queue\n",
addr, size);
stats.bytesReadWrQ += burst_size;
@@ -250,7 +250,7 @@ MemCtrl::addToReadQueue(PacketPtr pkt, unsigned int pkt_count, bool is_dram)
// Make the burst helper for split packets
if (pkt_count > 1 && burst_helper == NULL) {
DPRINTF(MemCtrl, "Read to addr %lld translates to %d "
DPRINTF(MemCtrl, "Read to addr %#x translates to %d "
"memory requests\n", pkt->getAddr(), pkt_count);
burst_helper = new BurstHelper(pkt_count);
}
@@ -394,19 +394,19 @@ MemCtrl::printQs() const
DPRINTF(MemCtrl, "===READ QUEUE===\n\n");
for (const auto& queue : readQueue) {
for (const auto& packet : queue) {
DPRINTF(MemCtrl, "Read %lu\n", packet->addr);
DPRINTF(MemCtrl, "Read %#x\n", packet->addr);
}
}
DPRINTF(MemCtrl, "\n===RESP QUEUE===\n\n");
for (const auto& packet : respQueue) {
DPRINTF(MemCtrl, "Response %lu\n", packet->addr);
DPRINTF(MemCtrl, "Response %#x\n", packet->addr);
}
DPRINTF(MemCtrl, "\n===WRITE QUEUE===\n\n");
for (const auto& queue : writeQueue) {
for (const auto& packet : queue) {
DPRINTF(MemCtrl, "Write %lu\n", packet->addr);
DPRINTF(MemCtrl, "Write %#x\n", packet->addr);
}
}
#endif // TRACING_ON
@@ -416,7 +416,7 @@ bool
MemCtrl::recvTimingReq(PacketPtr pkt)
{
// This is where we enter from the outside world
DPRINTF(MemCtrl, "recvTimingReq: request %s addr %lld size %d\n",
DPRINTF(MemCtrl, "recvTimingReq: request %s addr %#x size %d\n",
pkt->cmdString(), pkt->getAddr(), pkt->getSize());
panic_if(pkt->cacheResponding(), "Should not see packets where cache "
@@ -631,7 +631,7 @@ MemCtrl::chooseNextFRFCFS(MemPacketQueue& queue, Tick extra_col_delay)
void
MemCtrl::accessAndRespond(PacketPtr pkt, Tick static_latency)
{
DPRINTF(MemCtrl, "Responding to Address %lld.. \n",pkt->getAddr());
DPRINTF(MemCtrl, "Responding to Address %#x.. \n", pkt->getAddr());
bool needsResponse = pkt->needsResponse();
// do the actual memory access which also turns the packet into a
@@ -837,7 +837,7 @@ MemCtrl::doBurstAccess(MemPacket* mem_pkt)
}
DPRINTF(MemCtrl, "Access to %lld, ready at %lld next burst at %lld.\n",
DPRINTF(MemCtrl, "Access to %#x, ready at %lld next burst at %lld.\n",
mem_pkt->addr, mem_pkt->readyTime, nextBurstAt);
// Update the minimum timing between the requests, this is a

8
src/mem/mem_interface.cc
View File

@@ -153,7 +153,7 @@ MemInterface::decodePacket(const PacketPtr pkt, Addr pkt_addr,
assert(row < rowsPerBank);
assert(row < Bank::NO_ROW);
DPRINTF(DRAM, "Address: %lld Rank %d Bank %d Row %d\n",
DPRINTF(DRAM, "Address: %#x Rank %d Bank %d Row %d\n",
pkt_addr, rank, bank, row);
// create the corresponding memory packet with the entry time and
@@ -456,7 +456,7 @@ std::pair<Tick, Tick>
DRAMInterface::doBurstAccess(MemPacket* mem_pkt, Tick next_burst_at,
const std::vector<MemPacketQueue>& queue)
{
DPRINTF(DRAM, "Timing access to addr %lld, rank/bank/row %d %d %d\n",
DPRINTF(DRAM, "Timing access to addr %#x, rank/bank/row %d %d %d\n",
mem_pkt->addr, mem_pkt->rank, mem_pkt->bank, mem_pkt->row);
// get the rank
@@ -2305,7 +2305,7 @@ NVMInterface::burstReady(MemPacket* pkt) const {
std::pair<Tick, Tick>
NVMInterface::doBurstAccess(MemPacket* pkt, Tick next_burst_at)
{
DPRINTF(NVM, "NVM Timing access to addr %lld, rank/bank/row %d %d %d\n",
DPRINTF(NVM, "NVM Timing access to addr %#x, rank/bank/row %d %d %d\n",
pkt->addr, pkt->rank, pkt->bank, pkt->row);
// get the bank
@@ -2358,7 +2358,7 @@ NVMInterface::doBurstAccess(MemPacket* pkt, Tick next_burst_at)
}
}
DPRINTF(NVM, "NVM Access to %lld, ready at %lld.\n",
DPRINTF(NVM, "NVM Access to %#x, ready at %lld.\n",
pkt->addr, pkt->readyTime);
if (pkt->isRead()) {

6
src/mem/qos/mem_ctrl.cc
View File

@@ -91,7 +91,7 @@ MemCtrl::logRequest(BusState dir, RequestorID id, uint8_t _qos,
addRequestor(id);
DPRINTF(QOS,
"qos::MemCtrl::logRequest REQUESTOR %s [id %d] address %d"
"qos::MemCtrl::logRequest REQUESTOR %s [id %d] address %#x"
" prio %d this requestor q packets %d"
" - queue size %d - requested entries %d\n",
requestors[id], id, addr, _qos, packetPriorities[id][_qos],
@@ -147,7 +147,7 @@ MemCtrl::logResponse(BusState dir, RequestorID id, uint8_t _qos,
"Logging response with invalid requestor\n");
DPRINTF(QOS,
"qos::MemCtrl::logResponse REQUESTOR %s [id %d] address %d prio"
"qos::MemCtrl::logResponse REQUESTOR %s [id %d] address %#x prio"
" %d this requestor q packets %d"
" - queue size %d - requested entries %d\n",
requestors[id], id, addr, _qos, packetPriorities[id][_qos],
@@ -172,7 +172,7 @@ MemCtrl::logResponse(BusState dir, RequestorID id, uint8_t _qos,
auto it = requestTimes[id].find(addr);
panic_if(it == requestTimes[id].end(),
"qos::MemCtrl::logResponse requestor %s unmatched response "
"for address %d received", requestors[id], addr);
"for address %#x received", requestors[id], addr);
// Load request time
uint64_t requestTime = it->second.front();