Commit Graph

16925 Commits

Author SHA1 Message Date
Michael LeBeane
25e8a14a6b gpu-compute: Support dynamic scratch allocations
dGPUs in all versions of ROCm and APUs starting with ROCM 2.2 can
under-allocate scratch resources.  This patch adds support for
the CP to trigger a recoverable error so that the host can attempt to
re-allocate scratch to satisfy the currently stalled kernel.

Note that this patch does not include a mechanism to handle dynamic
scratch allocation for queues with in-flight kernels, as these queues
would first need to be drained and descheduled, which would require some
additional effort in the hsaPP and HW queue scheduler.  If the CP
encounters this scenerio it will assert.  I suspect this is not a
particularly common occurence in most of our applications so it is left
as a TODO.

This patch also fixes a few memory leaks and updates the old DMA callback
object interface to use a much cleaner c++11 lambda interface.

Change-Id: Ica8a5fc88888283415507544d6cc49fa748fe84d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42201
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-03-25 17:21:08 +00:00
Ayaz Akram
cc1bb34827 arch-riscv,util: fix the default cross compiler for riscv
Change-Id: I44b5f10fd9d0f3b7ac25a1adad16d5acaa44ddc3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43607
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-25 17:00:56 +00:00
Kyle Roarty
8f577e6e23 dev-hsa: Fix size of HSA Queue
In the HSAQueueDescriptor ptr function, we mod the index by numElts, but
numElts was previously just set to size, which was the raw size of the
queue. This lead to indexing past the queue. We fix this by dividing by
the size by the AQL packet size to get the actual number of elements the
queue can hold.

We also add an assert for indexing into the queue, as there is a
scenario where the queue reports a larger size than it actually is.

Change-Id: Ie5e699379f303255305c279e58a34dc783df86a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42423
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-25 16:34:16 +00:00
Giacomo Travaglini
47a278c0ad configs: RubySimpleSystem and simple ruby_fs.py script
This patch is providing a minimal ruby powered script
for Arm simulations

Change-Id: Ifb2d827362e2d5de5d15c70b200598f9f714f7f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43288
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-03-25 09:37:13 +00:00
Giacomo Travaglini
918a01f42e configs, tests: Ruby.create_system cpus option
This patch is adding an extra parameter to the Ruby.create_system
function. The idea is to remove any assumption about cpu configuration
in the ruby scripts.

At the moment the scripts are assuming a flat list of cpu assigned
to the system object. Unfortunately this is not standardized, as
some systems might empoloy a different layout of cpus, like grouping
them in cluster objects.

With this patch we are allowing client scripts to provide the cpu list
as an extra argument

This has the extra benefit of removing the indexing hack

if len(system.cpu) == 1:

which was present in most scripts

Change-Id: Ibc06b920273cde4f7c394d61c0ca664a7143cd27
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43287
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-03-25 09:37:13 +00:00
Giacomo Travaglini
51c17ac398 configs: Add a BaseSimpleSystem
This is a preparing patch, disentangling common platform
configurations from the memory setup (which is classic
oriented)

Change-Id: I395bfcfb15e666efdbf2f010bea7973f1658b6a3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43286
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2021-03-25 09:37:13 +00:00
Gabe Black
e0039d1eab arch: Eliminate the GuestByteOrder constant.
Most ISAs used that constant exactly once, when setting up a Process.
This change just propogates the constant to the one place it's used. In
MIPS, the endianness is hard coded as little. There were some checks
which would change the behavior if the endianness was big. This change
removes that dead code. If someone wants to add support for big endian
MIPS, they can go back and add in the small bits of code that would be
required. It's likely the existing big endian support was incomplete and
not tested, so it's probably best for someone interested in it to start
fresh anyway.

Change-Id: Ife6ffcf4bca40001d5d9126f7d795f954f66bb22
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40178
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-03-24 23:18:47 +00:00
Gabe Black
773368d68d arch-arm: Consolidate register related files into a directory.
Create a directory called "regs" which holds files, primarily headers,
related to registers, with the exception of registers.hh. Hopefully
registers.hh will go away in the not too distant future, removing this
exception.

Change-Id: I631423c2b09bbcd14b20001380270718aeca619e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41737
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-24 23:10:38 +00:00
Daecheol You
b42482a3d7 mem-garnet: Added packet distribution stats
Trace data and control traffic between all source-destination pairs.
This is for identifying packet distribution and bottleneck of the
interconnect network.

Change-Id: Iffc9c16fd1e02ab8f7c5382cec822bf57a43a057
JIRA: https://gem5.atlassian.net/browse/GEM5-861
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40275
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-24 04:39:40 +00:00
Daniel R. Carvalho
d7c9636237 util: Add verifier for opening braces of unions
Make sure that opening braces of unions are not declared
in the same line of the union name.

This does not work for multi-line unions.

Change-Id: Ieed6f974aec4b435b76195b1a05453da912f7450
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43329
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-23 23:41:54 +00:00
Daniel R. Carvalho
219003c575 base-stats: Make Rate's compilation smarter
A Rate should be supplied units of different types.
Rates between units of the same type are Ratios,
and should be declared as such.

An exception is applied to Count and Unspecified,
since those units represent unknown underlying units.

Change-Id: I36ab7c73b239ccc86d866c5b38e14fd765bbbd0f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43008
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-03-23 18:17:27 +00:00
Daniel R. Carvalho
aa07dbfba9 base-stats: Add unit test for Stats::Units
Add a unit test for base/stats/unit.hh.

Change-Id: I87f729928bb99c7f4d657bca0307955be933d3ed
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43007
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
2021-03-23 17:09:13 +00:00
Daniel R. Carvalho
b2c0b191e1 misc: Fix coding style for union's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation, using:

    grep -nrE --exclude-dir=systemc \
        "^ *union [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>union X ... {

by:

    <indent level>union X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^union [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^union ([A-Za-z].*) \{$/union \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    union [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    union ([A-Za-z].*) \{$/    union \1\n    \{/g'

and so on.

Change-Id: I066854eb27a8acd2cc2dfa41596bb1b1f66c71b1
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43328
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-03-23 16:26:04 +00:00
Daniel R. Carvalho
df8ef51d61 util: Add verifier for opening braces of enums
Make sure that opening braces of enums are not declared
in the same line of the enum name.

This does not work for multi-line enums.

Change-Id: I5fbdc317f954946127e6e79dbcaf46674abccb41
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43327
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-03-23 16:26:04 +00:00
Daniel R. Carvalho
7f1de4e686 misc: Fix coding style for enum's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation (and 2 of 2 spaces,
1 of 3 spaces and 2 of 12 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *enum [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>enum X ... {

by:

    <indent level>enum X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^enum ([A-Za-z].*) \{$/enum \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    enum ([A-Za-z].*) \{$/    enum \1\n    \{/g'

and so on.

Change-Id: Ib186cf379049098ceaec20dfe4d1edcedd5f940d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-23 16:26:04 +00:00
Gabe Black
08913caec2 arch,cpu,kern,sim: Eliminate the utility.hh switching header.
This header is no longer used. Remove the places where it's included,
and stop generating it. Also eliminate the now empty SPARC and Power
versions of the header.

Change-Id: I6ee66d39bc0218d1d9b9b7db3b350134ef03251d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39337
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-03-22 21:01:58 +00:00
Gabe Black
5ffd619d38 arch,cpu: Move TheISA::copyRegs to TheISA::ISA::copyRegsFrom.
This eliminates the last externally used function in arch/utility.hh.

Change-Id: I7f402b0303e2758762e19d69f3bed37262cc9289
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39336
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-03-22 21:01:33 +00:00
Gabe Black
2cb09e4042 arch,cpu: Collapse away TheISA::advancePC.
In most ISAs except MIPS and Power, this was implemented as
inst->advancePC(). It works just fine to call this function all the
time, but the idea had originally been that for ISAs which could simply
advance the PC using the PC itself, they could save the virtual function
call. Since the only ISAs which could skip the call were MIPS and Power,
and neither is at the point where that level of performance tuning
matters, this function can be collapsed with little downside.

If this turns out to be a performance bottleneck in the future, the way
the PC is managed could be revisited to see if we can factor out this
trip to the instruction object in the first place.

Change-Id: I533d1ad316e5c936466c529b7f1238a9ab87bd1c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39335
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Alex Dutu <alexandru.dutu@amd.com>
2021-03-22 21:01:07 +00:00
Gabe Black
7ac67eaf1b mem: Fix style in addr_mapper.hh.
Change-Id: I3fd0bee6ac79e34034fbcc25e5da505cc3fc7181
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43345
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-21 02:49:45 +00:00
Daniel R. Carvalho
96c202f819 util: Add verifier for opening braces of structs
Make sure that opening braces of structs are not declared
in the same line of the struct name.

This does not work for multi-line structs.

Change-Id: Ie9d5ccc8f7252ad37a90704ea09231a308fc6700
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43325
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-20 18:12:33 +00:00
Giacomo Travaglini
0296e308ac configs: Remove simpleSystem factory function
The function had been introduced in the past when we needed to
instantiate either an ArmSystem or a LinuxArmSystem depending on the
workload. Now that the workload object has been introduced in gem5, we
always instantiate an ArmSystem in FS mode, hence we don't need a
function to generate the System object

Change-Id: I79ccf31087b84521cce32da71bc835ff202dc432
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43285
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 21:24:20 +00:00
Bobby R. Bruce
af81ec9041 Merge "misc: Merge branch 'release-staging-v21-0' into develop" into develop 2021-03-19 21:13:58 +00:00
Daniel R. Carvalho
2922f763e1 misc: Fix coding style for struct's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation (and a single
occurrence of 2 and 3 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *struct [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>struct X ... {

by:

<indent level>struct X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^struct ([A-Za-z].*) \{$/struct \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    struct ([A-Za-z].*) \{$/    struct \1\n    \{/g'

and so on.

Change-Id: I362ef58c86912dabdd272c7debb8d25d587cd455
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39017
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 20:57:24 +00:00
Daniel R. Carvalho
f96de41fcf util: Add verifier for opening braces of classes
Make sure that opening braces of classes are not declared
in the same line of the class name.

This does not work for multi-line classes.

Change-Id: I232df1a9ebd974b9f4f66e1d96d03b12513bd49f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39016
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-03-19 20:57:24 +00:00
Daniel R. Carvalho
469f0671d1 misc: Fix coding style for class-opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation, using:

    grep -nrE --exclude-dir=systemc \
        "^ *class [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>class X ... {

by:

<indent level>class X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^class [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^class ([A-Za-z].*) \{$/class \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    class [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    class ([A-Za-z].*) \{$/    class \1\n    \{/g'

and so on.

Change-Id: I17615ce16a333d69867b27c7bae0f4fdafd8b2eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39015
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 20:57:24 +00:00
Giacomo Travaglini
588df4be85 configs, mem: MemInterface generating its own controller
We are adding a controller method to MemInterface objects making
them able to generate the appropriate memory controller.

This will bring the following benefits

a) Semplification: It will simplify MemConfig.config_mem
b) Reusability: Scripts not using config_mem
won't have to duplicate the if...else checks
c) Modularity: Users will be able to define their own
dram interfaces without needing to handle the mem_ctrl
mapping in the shared MemConfig.py module

Change-Id: I4b836fd7c91675cf7aacc644f25989484d5be3ec
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42074
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 13:34:37 +00:00
Gabe Black
1c35c00c4f arch,cpu: Get rid of the RenameMode template class.
There is no way to make this sort of template work with more than one
ISA at a time, and it's also more complex than it needs to be,
particularly since the methods within it are never used in performance
critical code. Using virtual functions is also simpler and uses less
code.

Change-Id: I0baa1a651fa656420f6f90776572f8700a6d7cab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40106
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 00:56:21 +00:00
Daniel R. Carvalho
54f5270949 base: Add unit test for base/logging
Add unit test for base/logging. logging.cc had to be split
in a file containing the mock functionality, and the gtest
logging functionality.

Change-Id: Ia890c06b44134b70eada7a9deadef882f00a5c27
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41398
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 22:25:17 +00:00
Daniel R. Carvalho
8deb205ea1 base: Add LOC to Loggers
Printing the line and the file that triggered a log
is useful for debugging.

Change-Id: I74e0637b2943049134bd3e9a4bc6cab3766591a9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42141
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 22:24:51 +00:00
Bobby R. Bruce
68064d8043 misc: Merge branch 'release-staging-v21-0' into develop
Change-Id: I0ad043ded56fb848e045057a1e7a56ea39797906
2021-03-18 11:13:14 -07:00
Daniel R. Carvalho
6a7403f1a2 sim: Move SimObjectResolver dependency to SimObject
Move SimObjectResolver dependency from CheckpointIn to
SimObject to reduce serialization tangling.

Change-Id: I9973bea0e3c6cabb0051a55dbf9aebef8a50fba8
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38739
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 17:34:30 +00:00
Daniel R. Carvalho
6bbee0fbce base: Add default log functionality to Logger
The only difference between the NormalLogger and Logger is
a simple implementation for log(), which is then called by
the other loggers. Since this is common to everybody, move
this implementation to Logger and remove NormalLogger.

This makes it possible to test the NormalLoggers using the
current gtest logging framework.

Change-Id: I6805fa14f58ddc7d37b00fcd7fcacb32e0b5d456
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41395
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-03-18 17:32:22 +00:00
Daniel R. Carvalho
763239ac32 base: Fix incorrect use of Logger::print
Previously when a formatted message was printed in a
Logger it would use the wrong function, and thus skip
the warning triggered by ccprintf. Fix this by merging
two prints to avoid ambiguity.

Change-Id: Idc51d2ef28ab4721d2be16f3e5fce19c494a0d47
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41399
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 17:32:22 +00:00
Yu-hsin Wang
a70dc125d1 sim: Add a copied symbol table for the kernel on physical address
In fs simulation, the kernel is loaded to physical address first and
then it would relocate itself to virtual address. The address which
using by kernel symbol table is virtual address. To debug the process
before kernel relocated to virutal memory, we need another copy of
symbol table for physical address.

Change-Id: I38107ff94b301df1a5170dd98774df88cfb02298
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43104
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 13:44:18 +00:00
Yu-hsin Wang
397b10957c base: Add a rename helper to SymbolTable
In some cases, we want to move and copy the symbol table to another
address. However, the name of symbol table should be unique. This rename
helper provides a way to modify the name of symbol. Developers can use
it to solve the conflict with this helper.

Change-Id: I4627e06da3a03da57009d613188be117c75750a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43105
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-18 08:05:24 +00:00
Bobby R. Bruce
377a96644e misc: Merge branch v20.1.0.5 hotfix into release-staging-v21-0
Change-Id: I7383ae1c9870b2f4929601305158030ec3423302
2021-03-17 13:14:26 -07:00
Bobby R. Bruce
31cd81fdec misc: Updated the RELEASE-NOTES and version number
Updated the RELEASE-NOTES.md and version number for the v20.1.0.5 hotfix
release.

Change-Id: I137a12325137799b9b1f98fe67ac55bfab49cd91
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43145
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-17 19:58:48 +00:00
Giacomo Travaglini
eb3554e0e9 configs: Use integer division in MESI_Three_Level_HTM.py
num_cpus_per_cluster and num_l2caches_per_cluster need to be integer
as we are iterating over those variables

Cherry-picked from:
https://gem5-review.googlesource.com/c/public/gem5/+/42883

Change-Id: Ifc1f9cf06b36044289a0ba5e54666f1af2587fca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43144
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-17 19:58:48 +00:00
Giacomo Travaglini
1479ad9ef0 arch-arm: Fix atomics permission checks in TLB
For stage 2 translations, atomic accesses were not checking the
access permission bits in the page table descriptors, and were
instead wrongly using the nature of the request itself
(r/w booleans).

Cherry-picked from:
https://gem5-review.googlesource.com/c/public/gem5/+/42073

Change-Id: I919a08b690287b03426d9124a61887e521f47823
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43143
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-17 19:58:48 +00:00
Andreas Sandberg
9ea38f7147 python: Fix incorrect prefixes is m5.utils.convert
The conversion functions incorrectly assumed that kibibytes are 'kiB'
rather than 'KiB' (correct).

Cherry-picked from:
https://gem5-review.googlesource.com/c/public/gem5/+/39375

Change-Id: Ia9409218c37284514fc4fabdabf327641db8cefc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43146
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-17 19:58:48 +00:00
Daniel R. Carvalho
68d612c330 base-stats: Fix Watt Unit
Watt had two implementations. Since having the unit
printed as Watt is more relevant than as Joule/Second,
keep the class.

Change-Id: Ic9ae755115e2eca94492f3d5b11245db9fe42bb6
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43006
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-17 13:53:15 +00:00
Gabe Black
07505a30af scons: Get rid of some unused cruft from Ruby/yacc.
These variables are never used, and so don't need to be set.

Change-Id: Ia345e3aa12b4437638943a436d28686b6e60acda
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40868
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2021-03-16 23:28:02 +00:00
Tiago Mück
b13b485095 configs,mem-ruby: CHI-based Ruby protocol
This patch add a new Ruby cache coherence protocol based on Arm' AMBA5
CHI specification. The CHI protocol defines and implements two state
machine types:

- Cache_Controller: generic cache controller that can be configured as:
    - Top-level L1 I/D cache
    - A intermediate level (L2, L3, ...) private or shared cache
    - A CHI home node (i.e. the point of coherence of the system and
        has the global directory)
    - A DMA requester

- Memory_Controller: implements a CHI slave node and interfaces with
    gem5 memory controller. This controller has the functionality of a
    Directory_Controller on the other Ruby protocols, except it doesn't
    have a directory.

The Cache_Controller has multiple cache allocation/deallocation
parameters to control the clusivity with respect to upstream caches.
Allocation can be completely disabled to use Cache_Controller as a
DMA requester or as a home node without a shared LLC.

The standard configuration file configs/ruby/CHI.py provides a
'create_system' compatible with configs/example/fs.py and
configs/example/se.py and creates a system with private L1/L2 caches
per core and a shared LLC at the home nodes. Different cache topologies
can be defined by modifying 'create_system' or by creating custom
scripts using the structures defined in configs/ruby/CHI.py.

This patch also includes the 'CustomMesh' topology script to be used
with CHI. CustomMesh generates a 2D mesh topology with the placement
of components manually defined in a separate configuration file using
the --noc-config parameter.
The example in configs/example/noc_config/2x4.yaml creates a simple 2x4
mesh. For example, to run a SE mode simulation, with 4 cores,
4 mem ctnrls, and 4 home nodes (L3 caches):

build/ARM/gem5.opt configs/example/se.py \
--cmd 'tests/test-progs/hello/bin/arm/linux/hello' \
--ruby --num-cpus=4 --num-dirs=4 --num-l3caches=4 \
--topology=CustomMesh --noc-config=configs/example/noc_config/2x4.yaml

If one doesn't care about the component placement on the interconnect,
the 'Crossbar' and 'Pt2Pt' may be used and they do not require the
--noc-config option.

Additional authors:
    Joshua Randall <joshua.randall@arm.com>
    Pedro Benedicte <pedro.benedicteillescas@arm.com>
    Tuan Ta <tuan.ta2@arm.com>

JIRA: https://gem5.atlassian.net/browse/GEM5-908

Change-Id: I856524b0afd30842194190f5bd69e7e6ded906b0
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42563
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 15:28:44 +00:00
Tiago Mück
dcc2f4caaf scons,mem-ruby: export need_partial_func_reads in SConstruct
need_partial_func_reads should now be modified from protocol specific
files (e.g. src/learning_gem5/part3/SConsopts)

Change-Id: I38039aab6178a019d063d6124200050f2ed7b446
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43043
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 15:28:44 +00:00
Giacomo Travaglini
a7a83e2581 configs: Use integer division in MESI_Three_Level_HTM.py
num_cpus_per_cluster and num_l2caches_per_cluster need to be integer
as we are iterating over those variables

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Iaad1ce9b4058421ff83ba9d2419eb5c36c772c35
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42883
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 13:49:48 +00:00
Gabe Black
d79d8498a4 cpu: Use a unique_ptr to manage cached disassembly.
This is a fairly minor improvement, but avoids having to manually keep
track of that string pointer.

Change-Id: Ic3d4ddd9445920a110b36ab0cd64ff2289cf0139
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42967
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-03-16 11:04:39 +00:00
Gabe Black
c0317722ec dev: Clean up the VirtIO9PDiod::startDiod method.
Rather than print the errno, print the result of strerror so the user
doesn't have to look up what each error code does. Don't duplicate
descriptors needlessly which have been returned by pipe(). Use panic_if
instead of if () panic. Check each call to a standard library function
instead of calling multiple and then only knowing that one of them
failed (but not which one). Close the far side of our pipes for both
the gem5 process, and the process that will become diod. Remove some
stray #undef-s which undefine macros that were never defined. Don't
try to force the descriptors going to diod to be particular numbers.
Slightly reduce nesting in the if which checks the results of fork.
Drop unnecessary \n-s in calls to panic, inform, etc. Minor spacing
related style fixes. Use nullptr instead of NULL.

Change-Id: I48d93778a1e139ef624876a0b316486aac774d7f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43083
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 10:46:53 +00:00
Giacomo Travaglini
f20d5070b1 configs: Unnecessary iteration on baremetal.py and starter_fs.py
The code is actually wrong and at the moment it works simply because
those scripts are instantiating a single cluster only

Change-Id: Ie756320707f6fdb2039567afd53b966a9386715b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42863
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 10:26:13 +00:00
Giacomo Travaglini
9ffcf15471 dev-arm: Remove unused SMMUv3 WalkCache variables
Those were grouped within the stats data structures but were
not actually stats

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I01bbbada423825ded04a033c0709108e2980ec70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42985
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 10:25:57 +00:00
Giacomo Travaglini
d8b172917a dev-arm: Fix WalkCache stats
The WalkCache stats are wrongly using the legacy framework.
With this patch we are registering those to the hierarchical structure.

As we need to pass the Stats::Group parent at construction time,
we are replacing 2d arrays with Vector2d for count stats and using a flat
vector of pointers for the Formula stats

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I8992bc262a376e4e81a4d608c11dff6902e0a01d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42984
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-16 10:25:57 +00:00