arch-arm: Fix atomics permission checks in TLB

For stage 2 translations, atomic accesses were not checking the
access permission bits in the page table descriptors, and were
instead wrongly using the nature of the request itself
(r/w booleans).

Cherry-picked from:
https://gem5-review.googlesource.com/c/public/gem5/+/42073

Change-Id: I919a08b690287b03426d9124a61887e521f47823
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43143
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/tlb.cc

@@ -772,8 +772,7 @@ TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
             // sctlr.wxn overrides the xn bit
             grant = !wxn && !xn;
         } else if (is_atomic) {
-            grant = r && w;
-            grant_read = r;
+            grant = hap;
         } else if (is_write) {
             grant = hap & 0x2;
         } else { // is_read