derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

configs: Add a BaseSimpleSystem

Browse Source 
This is a preparing patch, disentangling common platform
configurations from the memory setup (which is classic
oriented)

Change-Id: I395bfcfb15e666efdbf2f010bea7973f1658b6a3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43286
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Giacomo Travaglini
2021-03-12 20:36:15 +00:00
parent e0039d1eab
commit 51c17ac398
1 changed files with 41 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

75
configs/example/arm/devices.py
View File

@@ -277,11 +277,11 @@ class FastmodelCluster(SubSystem):
def connectMemSide(self, bus):
pass
class SimpleSystem(ArmSystem):
class BaseSimpleSystem(ArmSystem):
cache_line_size = 64
def __init__(self, caches, mem_size, platform=None, **kwargs):
super(SimpleSystem, self).__init__(**kwargs)
def __init__(self, mem_size, platform, **kwargs):
super(BaseSimpleSystem, self).__init__(**kwargs)
self.voltage_domain = VoltageDomain(voltage="1.0V")
self.clk_domain = SrcClockDomain(
@@ -296,51 +296,20 @@ class SimpleSystem(ArmSystem):
if hasattr(self.realview.gic, 'cpu_addr'):
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.membus = MemBus()
self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()
self.iobus = IOXBar()
# CPUs->PIO
self.iobridge = Bridge(delay='50ns')
# Device DMA -> MEM
mem_range = self.realview._mem_regions[0]
assert int(mem_range.size()) >= int(Addr(mem_size))
self.mem_ranges = [
AddrRange(start=mem_range.start, size=mem_size) ]
self._caches = caches
if self._caches:
self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
else:
self.dmabridge = Bridge(delay='50ns',
ranges=[self.mem_ranges[0]])
self._clusters = []
self._num_cpus = 0
def attach_pci(self, dev):
self.realview.attachPciDevice(dev, self.iobus)
def connect(self):
self.iobridge.mem_side_port = self.iobus.cpu_side_ports
self.iobridge.cpu_side_port = self.membus.mem_side_ports
if self._caches:
self.iocache.mem_side = self.membus.cpu_side_ports
self.iocache.cpu_side = self.iobus.mem_side_ports
else:
self.dmabridge.mem_side_port = self.membus.cpu_side_ports
self.dmabridge.cpu_side_port = self.iobus.mem_side_ports
if hasattr(self.realview.gic, 'cpu_addr'):
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.realview.attachOnChipIO(self.membus, self.iobridge)
self.realview.attachIO(self.iobus)
self.system_port = self.membus.cpu_side_ports
def numCpuClusters(self):
return len(self._clusters)
@@ -379,3 +348,41 @@ class SimpleSystem(ArmSystem):
# connect each cluster to the memory hierarchy
for cluster in self._clusters:
cluster.connectMemSide(cluster_mem_bus)
class SimpleSystem(BaseSimpleSystem):
"""
Meant to be used with the classic memory model
"""
def __init__(self, caches, mem_size, platform=None, **kwargs):
super(SimpleSystem, self).__init__(mem_size, platform, **kwargs)
self.membus = MemBus()
# CPUs->PIO
self.iobridge = Bridge(delay='50ns')
self._caches = caches
if self._caches:
self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
else:
self.dmabridge = Bridge(delay='50ns',
ranges=[self.mem_ranges[0]])
def connect(self):
self.iobridge.mem_side_port = self.iobus.cpu_side_ports
self.iobridge.cpu_side_port = self.membus.mem_side_ports
if self._caches:
self.iocache.mem_side = self.membus.cpu_side_ports
self.iocache.cpu_side = self.iobus.mem_side_ports
else:
self.dmabridge.mem_side_port = self.membus.cpu_side_ports
self.dmabridge.cpu_side_port = self.iobus.mem_side_ports
if hasattr(self.realview.gic, 'cpu_addr'):
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.realview.attachOnChipIO(self.membus, self.iobridge)
self.realview.attachIO(self.iobus)
self.system_port = self.membus.cpu_side_ports
def attach_pci(self, dev):
self.realview.attachPciDevice(dev, self.iobus)