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98 Commits

Author SHA1 Message Date
Giacomo Travaglini
cc3c15f1e0 configs, tests: Use proper releases in KVM simulations 
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I071f3d9c4eb5e4c7df3052bb8db93fece30cd069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64073
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-10-04 09:45:20 +00:00
Bobby R. Bruce
2bc5a8b71a misc: Run pre-commit run on all files in repo 
The following command was run:

```
pre-commit run --all-files
```

This ensures all the files in the repository are formatted to pass our
checks.

Change-Id: Ia2fe3529a50ad925d1076a612d60a4280adc40de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62572
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-08-24 21:47:07 +00:00
Wei-Han Chen
e046342f4f configs: fix fastmodel configs to run with kernel 5.x 
The original config can't run under kernel 5.x. Since atomic operation
on fastmodel doesn't work well, I decide to disable related configs
(BROADCASTATOMIC and BROADCASTOUTER) to unblock the boot process.

Change-Id: Ibe622e22ee918446ae4f5a4b7fc8bcacd280ba6f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62211
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-08-10 06:40:45 +00:00
Bobby R. Bruce
787204c92d python: Apply Black formatter to Python files 
The command executed was `black src configs tests util`.

Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-08-03 09:10:41 +00:00
Wei-Han Chen
71e3ff0b7c configs: move cpu a2t, t2g from gic_hub to cpu_hub 
Connections between cpu and gem5 lies in gic_hub now, but these are not
related to gic. So I create a subsystem in fastmodel cluster named
cpu_hub, and put those connections (a2t, t2g) there.

Change-Id: I18d9f80ce6f7f7f4a8290d1db5e48962294f43e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61851
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-08-02 01:52:14 +00:00
Giacomo Travaglini
1455ac0e0c arch-arm: Turn on EL2/EL3 support by default in ArmSystem 
In order to turn them off a user needs to explicitly do so
by providing a different ArmRelease objec

Change-Id: I227cee80c5517cdd50cf07c62d9a131ce261310f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51011
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-05-11 13:00:42 +00:00
Giacomo Travaglini
2fcb7ae87e configs: Add O3 option in starter_fs.py and ruby_fs.py 
Change-Id: I2d59d15cb8acdd7b2675653335af879e35b0d6b3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57273
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-03-07 09:06:23 +00:00
Giacomo Travaglini
9e8d397411 configs: Remove unused caches in ruby_fs.py 
The script is using the ruby memory subsystem, therefore the instantiated
classic cache models are left unbound

Change-Id: Ic083ef20a3fff63238a64f1478f25fe501e6d8e8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57272
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-03-03 15:41:46 +00:00
Yu-hsin Wang
dc48de5e62 configs: Fix parameters change when WalkCache is removed 
Change-Id: I3e8d2ae60e64d18462f6782484be500c5c514003
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55303
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-01-11 02:11:56 +00:00
Alistair Delva
791da53cf8 configs: Add support for initrd/initramfs 
Allow the user to specify the path to an initrd/initramfs file which
will be loaded in memory after the DTB. The load address for this data
will be passed to Linux via DeviceTree.

Change-Id: I52e12b9b88ab415fe3b318a6359026651667f3c6
Signed-off-by: Alistair Delva <adelva@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54186
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-01-05 23:07:07 +00:00
Giacomo Travaglini
3fba052f3f configs: Remove unused WalkCache models 
Change-Id: Iebda966e72b484ee15cbc7cd62256a950b2a90f1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54244
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-16 09:00:53 +00:00
Giacomo Travaglini
d1d90c529c configs: Stop using a PTW cache before L2 in Arm configs 
This implementation of a walk cache does not allow to skip walks as it
is a simple cache placed in front of the table walker.
It was meant to provide a faster retrieval of page table descriptors
than fetching them from L2 or memory.

This is not needed anymore for Arm as from [1] we implement
partial translation caching in Arm TLBs.

[1]: JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: I00d44a4e3961e15602bf4352f2f42ddccf2b746b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54243
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-12-16 09:00:53 +00:00
Giacomo Travaglini
de7337a32a misc: Replace master/slave terminology from BaseCPU.py 
In order to fix several regression failures [1] the master/slave
terminology in src/cpu/BaseCPU.py was reintroduced [2].

This patch is addressing the issue by providing 2 different
ways of connecting cpu ports:

*) connectBus: The method assumes an object with a bus interface is
passed as an argument, therefore it tries to bind cpu ports to the
bus.mem_side_ports and bus.cpu_side_ports

*) connectAllPorts: No assumption on the port owning device is made.
The method simply accepts ports as arguments which will be directly
connected to the peer cpu ports
This will be used for example by ruby Sequencers

[1]: https://gem5.atlassian.net/browse/GEM5-775
[2]: https://gem5-review.googlesource.com/c/public/gem5/+/34495

Change-Id: I715ab8471621d6e5eb36731d7eaefbedf9663a71
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52584
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2021-11-16 18:17:47 +00:00
Giacomo Travaglini
1a72fc6c85 configs: Replace connectAllPorts with connectCachedPorts 
Uncached ports are not used in Arm configs (X86 only [1])

[1]: https://github.com/gem5/gem5/blob/stable/src/cpu/BaseCPU.py#L181

Change-Id: I0f71f605ef73d9adc418414c891569bc475b2587
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52583
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-11-10 10:24:01 +00:00
Giacomo Travaglini
a680b98eaf configs: Assign the host gid to the Process.gid in SE configs 
Some syscalls (like chown) can make use of the current process group id
(gid) to setup file ownership. If we just provide the default fake gid
([1]) we will encounter some problems when executing the syscall on the
host.

Example (guest) program:

gid_t prc_gid = getgid();
int res = chown(..., prc_gid);

By assigning the host gid to the guest we are sure we can successfully
execute syscalls from the gem5 process

[1]: https://github.com/gem5/gem5/blob/v21.1.0.2/src/sim/Process.py#L52

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ia09f44916def03f68f7605d72f323f03ec71bbe1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51767
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-10-20 09:27:34 +00:00
Giacomo Travaglini
152760ee51 arch-arm: Define an ArmRelease class to handle ISA extensions 
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I3240853bd2123a6f24b2bb64c90ad457696f0d93
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51010
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-09-29 22:16:03 +00:00
Giacomo Travaglini
a2c9213a31 configs, tests: Replace optparse with argparse 
JIRA: https://gem5.atlassian.net/browse/GEM5-543

Change-Id: I997d6a4e45319a74e21bd0d61d4af6118474c849
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44513
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-04-21 20:42:37 +00:00
Hoa Nguyen
503b60ed56 configs: Fix stats name in arm/fs_power.py 
In the config, there are stats having name changed:
- overall_misses -> overallMisses
- sim_seconds -> simSeconds
- overall_accesses -> overallAccesses

JIRA: https://gem5.atlassian.net/browse/GEM5-957

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I35faa72b12320e6b41833f601eb23604358b3d42
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44626
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-04-21 09:36:07 +00:00
Giacomo Travaglini
e30378e2d2 configs: Add --kvm-userspace-gic to fs_bigLITTLE.py 
This will allow a user to select gem5 simulation of the GIC via
command line; Necessary option when the simulated GIC != than the
host GIC

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I30e151b774ddfa7f4e91054a375254e15007af3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44006
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-04-07 08:21:28 +00:00
Giacomo Travaglini
5e24869079 configs: Do not assume single mem range in RealView 
The SimpleSystem was assuming a single memory range for RealView
platforms by selecting the first element of the list only:

mem_range = self.realview._mem_regions[0]

This patch is fixing this by evaluating the entire list of platform
ranges.

Change-Id: I453fff7857966076c1419b95ddb9177e51d9f8d5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39636
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-04-06 08:48:50 +00:00
Gabe Black
5f95d7a89a dev,cpu,configs: Get rid of the IntrControl device. 
This vestigial device provides a thin layer of indirection between
devices and the CPUs in a system. It's basically a collection of helper
functions, but since it's a SimObject it needs to be instantiated in
python and added to configurations.

Change-Id: I029d2314ae0bb890678e1e68dafcdab4bfe49beb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43347
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-03-29 20:54:16 +00:00
Giacomo Travaglini
47a278c0ad configs: RubySimpleSystem and simple ruby_fs.py script 
This patch is providing a minimal ruby powered script
for Arm simulations

Change-Id: Ifb2d827362e2d5de5d15c70b200598f9f714f7f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43288
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2021-03-25 09:37:13 +00:00
Giacomo Travaglini
51c17ac398 configs: Add a BaseSimpleSystem 
This is a preparing patch, disentangling common platform
configurations from the memory setup (which is classic
oriented)

Change-Id: I395bfcfb15e666efdbf2f010bea7973f1658b6a3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43286
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2021-03-25 09:37:13 +00:00
Giacomo Travaglini
0296e308ac configs: Remove simpleSystem factory function 
The function had been introduced in the past when we needed to
instantiate either an ArmSystem or a LinuxArmSystem depending on the
workload. Now that the workload object has been introduced in gem5, we
always instantiate an ArmSystem in FS mode, hence we don't need a
function to generate the System object

Change-Id: I79ccf31087b84521cce32da71bc835ff202dc432
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43285
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-03-19 21:24:20 +00:00
Giacomo Travaglini
f20d5070b1 configs: Unnecessary iteration on baremetal.py and starter_fs.py 
The code is actually wrong and at the moment it works simply because
those scripts are instantiating a single cluster only

Change-Id: Ie756320707f6fdb2039567afd53b966a9386715b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42863
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-03-16 10:26:13 +00:00
Giacomo Travaglini
85c1fdac29 configs: Use MmioVirtIO for disk image in baremetal.py 
The baremetal platform is the platform we use for running
user supplied binaries on baremetal hardware.
(simply put, it runs provided binaries without adding
a gem5 bootloader)

Some layers of this software stack might not have a pci driver.
This might be the case for firmware images like edkII
which needs to use a block device to extract the bootloader
and/or the kernel image. Those can use the memory mapped
(in host domain) virtio block device which is already
part of the VExpress_GEM5 platforms

Change-Id: I9c6ba7e1b4566a3999fd9ba20a2bebe191dc3ef8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39995
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-01-29 22:41:24 +00:00
Andreas Sandberg
4d1a6fffd9 configs: Weed out old port terminology in Arm examples 
Stop using the deprecated port names in Arm example scripts.

Change-Id: I11fea3e0df945ac64075b647766570604b70cad8
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39582
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-01-22 11:05:01 +00:00
Andreas Sandberg
206038912c configs: Remove Python 2 compatibility code in Arm configs 
Remove uses of six and imports from __future__ and use native Python 3
functionality instead.

Change-Id: If37718ba99def2d6f176604e20d4ebeda75474ad
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39581
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-01-22 11:05:01 +00:00
Ciro Santilli
6ecf110b06 arch-arm: inform bootloader of kernel position with a register 
Before the commit, the bootloader had a hardcoded entry point that it
would jump to.

However, the Linux kernel arm64 v5.8 forced us to change the kernel
entry point because the required memory alignment has changed at:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/
commit/?h=v5.8&id=cfa7ede20f133cc81cef01dc3a516dda3a9721ee

Therefore the only way to have a single bootloader that boots both
pre-v5.8 and post-v5.8 kernels is to pass that information from gem5
to the bootloader, which we do in this patch via registers.

This approach was already used by the 32-bit bootloader, which passed
that value via r3, and we try to use the same register x3 in 64-bit.

Since we are now passing this information, the this patch also removes
the hardcoding of DTB and cpu-release-addr, and also passes those
values via registers.

We store the cpu-release-addr in x5 as that value appears to have a
function similar to flags_addr, which is used only in 32-bit arm and
gets stored in r5.

This commit renames atags_addr to dtb_addr, since both are mutually
exclusive, and serve a similar purpose, DTB being the newer recommended
approach.

Similarly, flags_addr is renamed to cpu_release_addr, and it is moved
from ArmSystem into ArmFsWorkload, since it is not an intrinsic system
property, and should be together with dtb_addr instead.

Before this commit, flags_addr was being set from FSConfig.py and
configs/example/arm/devices.py to self.realview.realview_io.pio_addr
+ 0x30. This commit moves that logic into RealView.py instead, and
sets the flags address 8 bytes before the start of the DTB address.

JIRA: https://gem5.atlassian.net/browse/GEM5-787
Change-Id: If70bea9690be04b84e6040e256a9b03e46710e10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35076
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-01-13 11:32:19 +00:00
Giacomo Travaglini
3c0769bd25 configs: Remove default bootscript option for fs_bigLITTLE.py 
Since the beginning fs_bigLITTLE has been pointing to a default

default_rcs = 'bootscript.rcS'

as a System.readfile parameter. That script is not present in
the gem5 repo and all the other fs scripts (starter_fs.py, fs.py
through Options.py) are using an emptry string as default
readfile param value.

We are hence aligning to the other scripts by removing this
default value

Change-Id: I20dc7714deae890d61706459c8d13bd8f5aac7a0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38815
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2021-01-07 09:37:40 +00:00
Yu-hsin Wang
3d20460c22 configs: Add dtb-gen to fs_bigLITTLE.py 
Change-Id: I1956e98d0fa507cc342e926b61d69fb967a64556
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36955
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-11-04 01:02:22 +00:00
Yu-hsin Wang
c70b4e28c4 configs: Fix FastmodelCluster cpu initialization 
We should create the thread and the interrupt controller of fastmodel by
calling the create function explicitly.

Change-Id: I269440e144e83fa0a31d8cdf285fed31642f4f73
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36380
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-22 00:49:06 +00:00
Giacomo Travaglini
330a5f7bad misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB 
With this commit we replace every TLB pointer stored in the
cpu model with a BaseMMU pointer.

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I4932a32f68582b25cd252b5420b54d6a40ee15b8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34976
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-21 09:33:39 +00:00
Giacomo Travaglini
41958f4afe configs: Remove dangling reference to bus port in devices.py 
Change-Id: I3f7b65a9e6d4ae88acc474bb0e3a55f28c3cd09b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35755
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-15 13:36:47 +00:00
Gabe Black
b489e49c68 configs,tests: Update configs to use compatible SE workloads. 
If there's no more compatible workload than the base SEWorkload class it
will fall back to that for now.

Change-Id: Id27172c3074a7976823a891878ab9eecf6246c47
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33901
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-10-13 04:59:04 +00:00
Gabe Black
3293926413 sim: Create a Workload object for SE mode. 
The workload object is still optional for the sake of compatibility,
even though it probably shouldn't be in the long term. If a simulation
is just a collection of components with nothing in particular running on
it, for instance driven by a traffic generator, should it even have a
System object in the first place?

Change-Id: I8bcda72bdfa3730248226fb62f0bba9a83243d95
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33278
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-09-20 07:26:22 +00:00
Richard Cooper
229f955f6f configs: Update starter_fs.py for latest Arm FS binaries. 
Updated the default kernel and root device names to match the latest
Arm full-system binaries available for download on the gem5 website.

Also added a command line option to allow the root device to be
specified as an optional command line argument.

Change-Id: I27f90ffaf0f4b35c5dcc4c22ac2fbd34f8a040a4
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30814
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-08-28 18:58:08 +00:00
Chris January
98ce167176 configs: Add earlycon to default kernel_cmd. 
The earlyprintk kernel command line argument does not take a value on Arm.
Rather pass early console name using the earlycon command line argument.

Change-Id: Ie14fc425e87c50a0b59fa4270a3743ed4fe97589
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31074
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-07-09 07:25:57 +00:00
Jason Lowe-Power
e2a510acef configs: Updates for python3 
Change-Id: Iab2f83716ea2cb19f06282f037314f2db843327a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29047
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2020-05-18 20:10:35 +00:00
Anouk Van Laer
818961969a sim-power: Creation of PowerState class 
This commit does not make any functional changes but just rearranges
the existing code with regard to the power states. Previously, all
code regarding power states was in the ClockedObjects. However, it
seems more logical and cleaner to move this code into a separate
class, called PowerState. The PowerState is a now SimObject. Every
ClockedObject has a PowerState but this patch also allows for objects
with PowerState which are not ClockedObjects.

Change-Id: Id2db86dc14f140dc9d0912a8a7de237b9df9120d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28049
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-04-29 21:03:31 +00:00
Nikos Nikoleris
84003b7cc7 configs: Change fs_power.py to use absolute paths for stats 
fs_power.py is an example script that demonstrates how power models
can be used with gem5. Previously, the formulas used to calculate the
dynamic and static power of the cores and the L2 cache were using
stats in equations as determined by their path relative to the
SimObject where the power model is attached to or full paths. This CL
changes these formulas to refer to the stats only by their full paths.

Change-Id: I91ea16c88c6a884fce90fd4cd2dfabcba4a1326c
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27893
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-04-29 21:03:31 +00:00
Giacomo Travaglini
eabd4f3a9b configs: Do not require args.kernel to be set in baremetal.py 
This is allowing to us run baremetal.py with the --dtb-gen option
without needing to specify a --kernel argument

Change-Id: I98f1bc865d2f4e2230b1a85453efe83d95ec8a55
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28148
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-04-28 09:51:36 +00:00
Giacomo Travaglini
701d16c1b3 configs: Use workloads.py in baremetal.py 
Change-Id: I806b771df448241a7a61f496ac22c29d5bc6b84c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27971
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-04-23 09:23:08 +00:00
Giacomo Travaglini
43d6bbc38c configs: Produce list of workload types in workloads.py 
Change-Id: I3f585e006704e671775af8d66d241e555d34cb08
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27970
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-04-23 09:23:08 +00:00
Giacomo Travaglini
6d90ccd7d6 configs: Add an example workloads module 
This will be a collection of Workload types.
At the moment we provide the following:

* ArmBaremetal: modelling a simple baremetal workload
* ArmTrustedFirmware: modelling the arm trusted firmware workload

Change-Id: Ib46286c03a1c952f981b172c1ea6aa4a6668757e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27969
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-04-23 09:23:08 +00:00
Giacomo Travaglini
b1d434363b configs: Add --machine-type option to baremetal.py 
Change-Id: Ie5d81b455b86f456a49ba91aa231169be319fa73
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27952
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-04-21 15:34:01 +00:00
Giacomo Travaglini
235209a3ed configs: Add --semi-path option to baremetal.py 
This is to make it possible to configure the semihosting
root directory via commandline.

Change-Id: If5167abc19eb8d78db37ebc854c336fe778a8a6f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27951
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-04-21 15:34:01 +00:00
Giacomo Travaglini
303663d5c9 configs: Enabling SimObj CLI for baremetal platform 
Change-Id: I0d4059976c8fb6a1d796998af302eaa764609f86
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27347
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2020-04-01 16:06:54 +00:00
Giacomo Travaglini
252560f03a configs: Initialize atags_addr in baremetal.py 
Change-Id: Iec797d4be607526d68a2813e188a32759418dbcc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27023
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2020-03-25 09:37:26 +00:00
Giacomo Travaglini
ad9f73eb73 configs: Enable Semihosting for baremetal.py 
This is enabled via the --semihosting option

Change-Id: If6961cba8ec4a3aa22e788db6fe0ae54e169bb9c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26993
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2020-03-25 09:37:26 +00:00