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misc: Replace master/slave terminology from BaseCPU.py

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In order to fix several regression failures [1] the master/slave
terminology in src/cpu/BaseCPU.py was reintroduced [2].

This patch is addressing the issue by providing 2 different
ways of connecting cpu ports:

*) connectBus: The method assumes an object with a bus interface is
passed as an argument, therefore it tries to bind cpu ports to the
bus.mem_side_ports and bus.cpu_side_ports

*) connectAllPorts: No assumption on the port owning device is made.
The method simply accepts ports as arguments which will be directly
connected to the peer cpu ports
This will be used for example by ruby Sequencers

[1]: https://gem5.atlassian.net/browse/GEM5-775
[2]: https://gem5-review.googlesource.com/c/public/gem5/+/34495

Change-Id: I715ab8471621d6e5eb36731d7eaefbedf9663a71
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52584
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Giacomo Travaglini
2021-11-09 10:21:58 +00:00
parent 404077e8ff
commit de7337a32a
16 changed files with 60 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
configs/common/CacheConfig.py
View File

@@ -187,11 +187,14 @@ def config_cache(options, system):
system.cpu[i].createInterruptController()
if options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
system.cpu[i].connectAllPorts(
system.tol2bus.cpu_side_ports,
system.membus.cpu_side_ports, system.membus.mem_side_ports)
elif options.external_memory_system:
system.cpu[i].connectUncachedPorts(system.membus)
system.cpu[i].connectUncachedPorts(
system.membus.cpu_side_ports, system.membus.mem_side_ports)
else:
system.cpu[i].connectAllPorts(system.membus)
system.cpu[i].connectBus(system.membus)
return system

4
configs/example/arm/devices.py
View File

@@ -150,7 +150,7 @@ class CpuCluster(SubSystem):
self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
self.l2 = self._l2_type()
for cpu in self.cpus:
cpu.connectCachedPorts(self.toL2Bus)
cpu.connectCachedPorts(self.toL2Bus.cpu_side_ports)
self.toL2Bus.mem_side_ports = self.l2.cpu_side
def addPMUs(self, ints, events=[]):
@@ -184,7 +184,7 @@ class CpuCluster(SubSystem):
self.l2.mem_side = bus.cpu_side_ports
except AttributeError:
for cpu in self.cpus:
cpu.connectCachedPorts(bus)
cpu.connectCachedPorts(bus.cpu_side_ports)
class AtomicCluster(CpuCluster):

2
configs/example/fs.py
View File

@@ -263,7 +263,7 @@ def build_drive_system(np):
cpu_id=0)
drive_sys.cpu.createThreads()
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
drive_sys.cpu.connectBus(drive_sys.membus)
if args.kernel is not None:
drive_sys.workload.object_file = binary(args.kernel)

3
configs/ruby/CHI_config.py
View File

@@ -360,7 +360,8 @@ class CPUSequencerWrapper:
for p in cpu._cached_ports:
if str(p) != 'icache_port':
exec('cpu.%s = self.data_seq.in_ports' % p)
cpu.connectUncachedPorts(self.data_seq)
cpu.connectUncachedPorts(
self.data_seq.in_ports, self.data_seq.out_ports)
def connectIOPorts(self, piobus):
self.data_seq.connectIOPorts(piobus)

5
configs/splash2/run.py
View File

@@ -210,7 +210,10 @@ for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = args.l1size, assoc = 1),
L1(size = args.l1size, assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2bus, system.membus)
cpu.connectAllPorts(
system.toL2bus.cpu_side_ports,
system.membus.cpu_side_ports,
system.membus.mem_side_ports)
# ----------------------

24
src/cpu/BaseCPU.py
View File

@@ -186,21 +186,23 @@ class BaseCPU(ClockedObject):
def createInterruptController(self):
self.interrupts = [ArchInterrupts() for i in range(self.numThreads)]
def connectCachedPorts(self, bus):
def connectCachedPorts(self, in_ports):
for p in self._cached_ports:
exec('self.%s = bus.slave' % p)
exec('self.%s = in_ports' % p)
def connectUncachedPorts(self, bus):
def connectUncachedPorts(self, in_ports, out_ports):
for p in self._uncached_interrupt_response_ports:
exec('self.%s = bus.master' % p)
exec('self.%s = out_ports' % p)
for p in self._uncached_interrupt_request_ports:
exec('self.%s = bus.slave' % p)
exec('self.%s = in_ports' % p)
def connectAllPorts(self, cached_bus, uncached_bus = None):
self.connectCachedPorts(cached_bus)
if not uncached_bus:
uncached_bus = cached_bus
self.connectUncachedPorts(uncached_bus)
def connectAllPorts(self, cached_in, uncached_in, uncached_out):
self.connectCachedPorts(cached_in)
self.connectUncachedPorts(uncached_in, uncached_out)
def connectBus(self, bus):
self.connectAllPorts(bus.cpu_side_ports,
bus.cpu_side_ports, bus.mem_side_ports)
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
self.icache = ic
@@ -229,7 +231,7 @@ class BaseCPU(ClockedObject):
xbar=None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
self.toL2Bus = xbar if xbar else L2XBar()
self.connectCachedPorts(self.toL2Bus)
self.connectCachedPorts(self.toL2Bus.cpu_side_ports)
self.l2cache = l2c
self.toL2Bus.mem_side_ports = self.l2cache.cpu_side
self._cached_ports = ['l2cache.mem_side']

14
src/cpu/testers/traffic_gen/BaseTrafficGen.py
View File

@@ -108,15 +108,19 @@ class BaseTrafficGen(ClockedObject):
def createInterruptController(self):
pass
def connectCachedPorts(self, bus):
def connectCachedPorts(self, in_ports):
if hasattr(self, '_cached_ports') and (len(self._cached_ports) > 0):
for p in self._cached_ports:
exec('self.%s = bus.cpu_side_ports' % p)
exec('self.%s = in_ports' % p)
else:
self.port = bus.cpu_side_ports
self.port = in_ports
def connectAllPorts(self, cached_bus, uncached_bus = None):
self.connectCachedPorts(cached_bus)
def connectAllPorts(self, cached_in, uncached_in, uncached_out):
self.connectCachedPorts(cached_in)
def connectBus(self, bus):
self.connectAllPorts(bus.cpu_side_ports,
bus.cpu_side_ports, bus.mem_side_ports)
def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
self.dcache = dc

3
src/mem/ruby/system/Sequencer.py
View File

@@ -112,7 +112,8 @@ class RubySequencer(RubyPort):
import m5.objects
assert(isinstance(cpu, m5.objects.BaseCPU))
# this connects all cpu mem-side ports to self.in_ports
cpu.connectAllPorts(self)
cpu.connectAllPorts(
self.in_ports, self.in_ports, self.interrupt_out_port)
def connectIOPorts(self, piobus):
"""

5
tests/configs/gpu-ruby.py
View File

@@ -301,7 +301,10 @@ cpu.createInterruptController()
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
cpu.connectAllPorts(system.ruby._cpu_ports[0])
cpu.connectAllPorts(
system.ruby._cpu_ports[0].in_ports,
system.ruby._cpu_ports[0].in_ports,
system.ruby._cpu_ports[0].interrupt_out_port)
system.ruby._cpu_ports[0].mem_master_port = system.piobus.slave
# attach CU ports to Ruby

2
tests/configs/o3-timing-mp-ruby.py
View File

@@ -45,7 +45,7 @@ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
for cpu in cpus:
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
cpu.connectBus(system.membus)
# All cpus are associated with cpu_clk_domain
cpu.clk_domain = system.cpu_clk_domain

2
tests/configs/o3-timing-ruby.py
View File

@@ -45,7 +45,7 @@ system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
cpu.connectBus(system.membus)
# Connect the system port for loading of binaries etc
system.system_port = system.membus.slave

2
tests/configs/simple-atomic-mp-ruby.py
View File

@@ -43,7 +43,7 @@ system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
# add L1 caches
for cpu in cpus:
cpu.connectAllPorts(system.membus)
cpu.connectBus(system.membus)
# All cpus are associated with cpu_clk_domain
cpu.clk_domain = system.cpu_clk_domain

5
tests/configs/simple-timing-mp-ruby.py
View File

@@ -83,7 +83,10 @@ for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the ruby cpu ports
#
cpu.connectAllPorts(system.ruby._cpu_ports[i])
cpu.connectAllPorts(
system.ruby._cpu_ports[i].in_ports,
system.ruby._cpu_ports[i].in_ports,
system.ruby._cpu_ports[i].interrupt_out_port)
# -----------------------
# run simulation

5
tests/configs/simple-timing-ruby.py
View File

@@ -87,7 +87,10 @@ cpu.createInterruptController()
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
cpu.connectAllPorts(system.ruby._cpu_ports[0])
cpu.connectAllPorts(
system.ruby._cpu_ports[0].in_ports,
system.ruby._cpu_ports[0].in_ports,
system.ruby._cpu_ports[0].interrupt_out_port)
# -----------------------
# run simulation

2
tests/configs/t1000-simple-atomic.py
View File

@@ -43,7 +43,7 @@ cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain)
system.cpu = cpu
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
cpu.connectBus(system.membus)
# create the memory controllers and connect them, stick with
# the physmem name to avoid bumping all the reference stats

8
tests/gem5/configs/base_config.py
View File

@@ -122,8 +122,10 @@ class BaseSystem(object, metaclass=ABCMeta):
if not cpu.switched_out:
self.create_caches_private(cpu)
cpu.createInterruptController()
cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
system.membus)
cached_bus = sha_bus if sha_bus != None else system.membus
cpu.connectAllPorts(cached_bus.cpu_side_ports,
system.membus.cpu_side_ports,
system.membus.mem_side_ports)
def init_kvm_cpus(self, cpus):
"""
@@ -191,7 +193,7 @@ class BaseSystem(object, metaclass=ABCMeta):
for i, cpu in enumerate(system.cpu):
if not cpu.switched_out:
cpu.createInterruptController()
cpu.connectCachedPorts(system.ruby._cpu_ports[i])
cpu.connectCachedPorts(system.ruby._cpu_ports[i].in_ports)
else:
sha_bus = self.create_caches_shared(system)
for cpu in system.cpu: