configs: Replace connectAllPorts with connectCachedPorts

Uncached ports are not used in Arm configs (X86 only [1])

[1]: https://github.com/gem5/gem5/blob/stable/src/cpu/BaseCPU.py#L181

Change-Id: I0f71f605ef73d9adc418414c891569bc475b2587
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52583
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs/example/arm/devices.py

@@ -150,7 +150,7 @@ class CpuCluster(SubSystem):
         self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
         self.l2 = self._l2_type()
         for cpu in self.cpus:
-            cpu.connectAllPorts(self.toL2Bus)
+            cpu.connectCachedPorts(self.toL2Bus)
         self.toL2Bus.mem_side_ports = self.l2.cpu_side
 
     def addPMUs(self, ints, events=[]):
@@ -184,7 +184,7 @@ class CpuCluster(SubSystem):
             self.l2.mem_side = bus.cpu_side_ports
         except AttributeError:
             for cpu in self.cpus:
-                cpu.connectAllPorts(bus)
+                cpu.connectCachedPorts(bus)
 
 
 class AtomicCluster(CpuCluster):