arch-arm: inform bootloader of kernel position with a register
Before the commit, the bootloader had a hardcoded entry point that it would jump to. However, the Linux kernel arm64 v5.8 forced us to change the kernel entry point because the required memory alignment has changed at: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ commit/?h=v5.8&id=cfa7ede20f133cc81cef01dc3a516dda3a9721ee Therefore the only way to have a single bootloader that boots both pre-v5.8 and post-v5.8 kernels is to pass that information from gem5 to the bootloader, which we do in this patch via registers. This approach was already used by the 32-bit bootloader, which passed that value via r3, and we try to use the same register x3 in 64-bit. Since we are now passing this information, the this patch also removes the hardcoding of DTB and cpu-release-addr, and also passes those values via registers. We store the cpu-release-addr in x5 as that value appears to have a function similar to flags_addr, which is used only in 32-bit arm and gets stored in r5. This commit renames atags_addr to dtb_addr, since both are mutually exclusive, and serve a similar purpose, DTB being the newer recommended approach. Similarly, flags_addr is renamed to cpu_release_addr, and it is moved from ArmSystem into ArmFsWorkload, since it is not an intrinsic system property, and should be together with dtb_addr instead. Before this commit, flags_addr was being set from FSConfig.py and configs/example/arm/devices.py to self.realview.realview_io.pio_addr + 0x30. This commit moves that logic into RealView.py instead, and sets the flags address 8 bytes before the start of the DTB address. JIRA: https://gem5.atlassian.net/browse/GEM5-787 Change-Id: If70bea9690be04b84e6040e256a9b03e46710e10 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35076 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
@@ -250,7 +250,7 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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if bare_metal:
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# EOT character on UART will end the simulation
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self.realview.uart[0].end_on_eot = True
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self.workload = ArmFsWorkload(atags_addr=0)
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self.workload = ArmFsWorkload(dtb_addr=0)
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else:
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workload = ArmFsLinux()
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@@ -269,8 +269,6 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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if hasattr(self.realview.gic, 'cpu_addr'):
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.flags_addr = self.realview.realview_io.pio_addr + 0x30
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# This check is for users who have previously put 'android' in
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# the disk image filename to tell the config scripts to
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# prepare the kernel with android-specific boot options. That
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@@ -308,7 +308,6 @@ def simpleSystem(BaseSystem, caches, mem_size, platform=None, **kwargs):
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if hasattr(self.realview.gic, 'cpu_addr'):
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.flags_addr = self.realview.realview_io.pio_addr + 0x30
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self.membus = MemBus()
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@@ -47,7 +47,7 @@ from common.SysPaths import binary, disk
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class ArmBaremetal(ArmFsWorkload):
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""" Baremetal workload """
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atags_addr = 0
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dtb_addr = 0
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def __init__(self, obj, system, **kwargs):
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super(ArmBaremetal, self).__init__(**kwargs)
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@@ -72,7 +72,7 @@ class ArmTrustedFirmware(ArmFsWorkload):
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https://github.com/ARM-software/arm-trusted-firmware
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"""
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atags_addr = 0
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dtb_addr = 0
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def __init__(self, obj, system, **kwargs):
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super(ArmTrustedFirmware, self).__init__(**kwargs)
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@@ -1,4 +1,4 @@
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# Copyright (c) 2009, 2012-2013, 2015-2019 ARM Limited
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# Copyright (c) 2009, 2012-2013, 2015-2020 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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@@ -57,11 +57,11 @@ class ArmFsWorkload(KernelWorkload):
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dtb_filename = Param.String("",
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"File that contains the Device Tree Blob. Don't use DTB if empty.")
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dtb_addr = Param.Addr(0, "DTB or ATAGS address")
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cpu_release_addr = Param.Addr(0, "cpu-release-addr property")
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machine_type = Param.ArmMachineType('DTOnly',
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"Machine id from http://www.arm.linux.org.uk/developer/machines/")
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atags_addr = Param.Addr("Address where default atags structure should " \
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"be written")
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early_kernel_symbols = Param.Bool(False,
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"enable early kernel symbol tables before MMU")
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enable_context_switch_stats_dump = Param.Bool(False,
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@@ -48,7 +48,6 @@ class ArmSystem(System):
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cxx_header = "arch/arm/system.hh"
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multi_proc = Param.Bool(True, "Multiprocessor system?")
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gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
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flags_addr = Param.Addr(0, "Address of the flags register for MP booting")
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have_security = Param.Bool(False,
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"True if Security Extensions are implemented")
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have_virtualization = Param.Bool(False,
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@@ -95,7 +95,7 @@ FsFreebsd::initState()
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// Kernel supports flattened device tree and dtb file specified.
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// Using Device Tree Blob to describe system configuration.
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inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
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params().atags_addr + _loadAddrOffset);
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params().dtb_addr + _loadAddrOffset);
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auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);
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@@ -108,7 +108,7 @@ FsFreebsd::initState()
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bootReleaseAddr = ra & ~ULL(0x7F);
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dtb_file->buildImage().
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offset(params().atags_addr + _loadAddrOffset).
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offset(params().dtb_addr + _loadAddrOffset).
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write(system->physProxy);
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delete dtb_file;
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@@ -116,7 +116,7 @@ FsFreebsd::initState()
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for (auto *tc: system->threads) {
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tc->setIntReg(0, 0);
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tc->setIntReg(1, params().machine_type);
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tc->setIntReg(2, params().atags_addr + _loadAddrOffset);
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tc->setIntReg(2, params().dtb_addr + _loadAddrOffset);
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}
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}
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010, 2012-2013, 2015,2017-2019 ARM Limited
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* Copyright (c) 2010, 2012-2013, 2015,2017-2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@@ -117,21 +117,21 @@ FsWorkload::initState()
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inform("Using bootloader at address %#x", bootldr->entryPoint());
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// Put the address of the boot loader into r7 so we know
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// The address of the boot loader so we know
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// where to branch to after the reset fault
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// All other values needed by the boot loader to know what to do
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fatal_if(!arm_sys->params().flags_addr,
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"flags_addr must be set with bootloader");
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fatal_if(!params().cpu_release_addr,
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"cpu_release_addr must be set with bootloader");
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fatal_if(!arm_sys->params().gic_cpu_addr && is_gic_v2,
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"gic_cpu_addr must be set with bootloader");
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for (auto *tc: arm_sys->threads) {
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if (!arm_sys->highestELIs64())
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tc->setIntReg(3, kernelEntry);
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tc->setIntReg(3, kernelEntry);
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if (is_gic_v2)
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tc->setIntReg(4, arm_sys->params().gic_cpu_addr);
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tc->setIntReg(5, arm_sys->params().flags_addr);
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if (getArch() == Loader::Arm)
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tc->setIntReg(5, params().cpu_release_addr);
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}
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inform("Using kernel entry physical address at %#x\n", kernelEntry);
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} else {
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2010-2013, 2016 ARM Limited
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* Copyright (c) 2010-2013, 2016, 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@@ -92,7 +92,7 @@ FsLinux::initState()
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// Kernel supports flattened device tree and dtb file specified.
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// Using Device Tree Blob to describe system configuration.
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inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
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params().atags_addr + _loadAddrOffset);
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params().dtb_addr);
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auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);
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@@ -102,9 +102,8 @@ FsLinux::initState()
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params().dtb_filename);
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}
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dtb_file->buildImage().
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offset(params().atags_addr + _loadAddrOffset).
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write(system->physProxy);
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dtb_file->buildImage().offset(params().dtb_addr)
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.write(system->physProxy);
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delete dtb_file;
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} else {
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// Using ATAGS
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@@ -152,17 +151,27 @@ FsLinux::initState()
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DPRINTF(Loader, "Boot atags was %d bytes in total\n", size << 2);
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DDUMP(Loader, boot_data, size << 2);
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system->physProxy.writeBlob(params().atags_addr + _loadAddrOffset,
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system->physProxy.writeBlob(params().dtb_addr + _loadAddrOffset,
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boot_data, size << 2);
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delete[] boot_data;
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}
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// Kernel boot requirements to set up r0, r1 and r2 in ARMv7
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for (auto *tc: system->threads) {
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tc->setIntReg(0, 0);
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tc->setIntReg(1, params().machine_type);
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tc->setIntReg(2, params().atags_addr + _loadAddrOffset);
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if (getArch() == Loader::Arm64) {
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// We inform the bootloader of the kernel entry point. This was added
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// originally done because the entry offset changed in kernel v5.8.
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// Previously the bootloader just used a hardcoded address.
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for (auto *tc: system->threads) {
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tc->setIntReg(0, params().dtb_addr);
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tc->setIntReg(5, params().cpu_release_addr);
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}
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} else {
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// Kernel boot requirements to set up r0, r1 and r2 in ARMv7
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for (auto *tc: system->threads) {
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tc->setIntReg(0, 0);
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tc->setIntReg(1, params().machine_type);
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tc->setIntReg(2, params().dtb_addr + _loadAddrOffset);
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}
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}
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}
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@@ -713,10 +713,11 @@ class RealView(Platform):
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self._attach_mem(self._off_chip_memory(), bus, mem_ports)
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self._attach_io(self._off_chip_devices(), bus, dma_ports)
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def setupBootLoader(self, cur_sys, boot_loader, atags_addr, load_offset):
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def setupBootLoader(self, cur_sys, boot_loader, dtb_addr, load_offset):
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cur_sys.workload.boot_loader = boot_loader
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cur_sys.workload.atags_addr = atags_addr
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cur_sys.workload.load_addr_offset = load_offset
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cur_sys.workload.dtb_addr = load_offset + dtb_addr
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cur_sys.workload.cpu_release_addr = cur_sys.workload.dtb_addr - 8
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def generateDeviceTree(self, state):
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node = FdtNode("/") # Things in this module need to end up in the root
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@@ -734,8 +735,11 @@ class RealView(Platform):
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cpu.append(FdtPropertyStrings('enable-method', 'psci'))
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else:
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cpu.append(FdtPropertyStrings("enable-method", "spin-table"))
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# The kernel writes the entry addres of secondary CPUs to this
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# address before waking up secondary CPUs.
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# The gem5 bootloader then makes secondary CPUs jump to it.
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cpu.append(FdtPropertyWords("cpu-release-addr", \
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state.addrCells(0x8000fff8)))
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state.addrCells(system.workload.cpu_release_addr)))
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class VExpress_EMM(RealView):
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_mem_regions = [ AddrRange('2GB', size='2GB') ]
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2012 ARM Limited
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* Copyright (c) 2012, 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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@@ -40,6 +40,14 @@
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.globl _start
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_start:
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/* Save some values initialized by gem5. */
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/* DTB address. */
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mov x21, x0
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/* Kernel entry point. */
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mov x20, x3
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/* cpu-release-addr. */
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mov x22, x5
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/*
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* EL3 initialisation
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*/
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@@ -153,8 +161,19 @@ start_ns:
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* Secondary CPUs
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*/
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1: wfe
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ldr x4, =PHYS_OFFSET + 0xfff8
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ldr x4, [x4]
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/* The Linux kernel v5.8 and older writes the entry point address
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* of the secondary CPUs to this address, and does a SEV, waking up
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* the secondary CPUs.
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*
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* gem5 informs the kernel the desired address via cpu-release-addr
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* of the DTB.
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*
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* When this is first reached immediately after the bootloader starts,
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* the value at that address must be 0, which is the default memory
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* value set by gem5 for otherwise uninitialized memory, leading to
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* WFE.
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*/
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ldr x4, [x22]
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cbz x4, 1b
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br x4 // branch to the given address
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@@ -180,9 +199,13 @@ start_ns:
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/*
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* Primary CPU
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*/
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ldr x0, =PHYS_OFFSET + 0x8000000 // device tree blob
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ldr x6, =PHYS_OFFSET + 0x80000 // kernel start address
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br x6
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// The kernel boot protocol specifies that the DTB address is placed
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// in x0.
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// https://github.com/torvalds/linux/blob/v5.7/Documentation/arm64/
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// booting.rst#4-call-the-kernel-image
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mov x0, x21
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// Jump into the kernel entry point.
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br x20
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.ltorg
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@@ -34,11 +34,7 @@ BUILDDIR = .
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DESTDIR = $(error Please set DESTDIR to wanted installation directory)
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CFLAGS = -march=armv8-a
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CPPFLAGS = -DPHYS_OFFSET=0x80000000 \
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-DUART_BASE=0x1c090000 -DSYSREGS_BASE=0x1c010000 \
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-Dkernel=0x80080000 \
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-Dmbox=0x8000fff8 -Ddtb=0x80000100
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CPPFLAGS = -DUART_BASE=0x1c090000 -DSYSREGS_BASE=0x1c010000
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LDFLAGS = -N -Ttext 0x00000010 -static
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.PHONY: all clean install mkdir
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