derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
19,110 Commits 2 Branches 0 Tags
0fa9bc0780d402e2f35b2d5d354ea97d7cfc89e2
Commit Graph

19110 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Gabe Black
0fa9bc0780 arch-riscv: Revamp int regs. 
Change-Id: Ie4773178843757acede4fe9e77ca327f7b024270
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49772
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2022-06-20 04:03:52 +00:00
Gabe Black
6a73a3a2d0 arch: Switch the generic register ABI over to use RegId. 
Change-Id: I4bbe884fe01fe14d7f18574f494a831dee2996d3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49774
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-19 07:48:14 +00:00
Gabe Black
644ab97727 arch-sparc: Revamp the float registers. 
Change-Id: Iec52e15f1529319345795496a82a37e1f0aeebae
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49769
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2022-06-19 07:21:37 +00:00
Gabe Black
0de5b1f173 arch-sparc: Revamp the int regs. 
Change-Id: Ifa968e42e55f78cea9eb92e9fc6fc906e0784594
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49768
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-19 07:21:14 +00:00
Gabe Black
a0e278863f arch-sparc: Remove unused fixed register operands. 
These had been used to manually feed arguments to pseudoInsts (I think)
which is now handled automatically. Regardless, these are not used and
can be eliminated.

Change-Id: I1aeeb00627bbbfaaf550c878ee88b0b2f7f6b61d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49807
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-19 07:21:00 +00:00
Gabe Black
93fa99041d arch-mips: Convert float, int, and misc regs. 
Convert them to use namespaces, style guide compliant names, and (except
for misc regs) the new accessors.

Change-Id: I6f190658447d40b9933e498ce766ac6c629b6cbb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49761
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-19 07:20:34 +00:00
Yu-hsin Wang
72290f00fd systemc: align the style in sc_ext 
Change-Id: I0a45ad9d9e3a2603878ee9bcdc1d416bb241deeb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59650
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-17 07:08:16 +00:00
Charles Jamieson
7170c365be arch-vega: implement S_GETREG_B32 instruction 
This commit adds support for the Vega GPU ISA's S_GETREG_B32
instruction.

This work was done by Charles Jamieson but I am committing.

Change-Id: Ic2e24f667ed1aec7b8b1404a06e17e7ffb192fba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60589
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-17 02:24:05 +00:00
Bobby R. Bruce
508c1cf69a util-docker: Fix the gpu-fs docker image. 
This was broken, it was actually building he gcn-gpu image, not the
gpu-fs image. This patch fixes this error.

Change-Id: I2d8ca0ea6584d059ddb6c9084de2b3075fb59723
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60511
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2022-06-16 18:44:04 +00:00
Mingyuan Xiang
928c5807db mem-ruby: Add RubyHitMiss debug flags to print hit and miss information 
Add RubyHitMiss debug flags to print hit and miss information. This can be
used to test the replacement policies by the traffic generator.

Change-Id: If9fe42c37e09be0534077fbf912d8699debd80fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21719
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2022-06-15 20:51:16 +00:00
Bobby R. Bruce
f4f40f44f1 tests: Fix the download test 
Weekly tests were failing: https://jenkins.gem5.org/job/weekly/56

This was due to the test passing the wrong parameter to the script.

Change-Id: Ief810d6b39859129a95fe8a2914e47d21bf879aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60410
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-06-15 18:42:34 +00:00
Yu-hsin Wang
d4456b3ee0 systemc: define control extension 
There are some flags in gem5 Packet class to specifying the control
signals, like priv bit, secure bit, etc. For now we don't have the
corresponding way to bridge the information in gem5 and SystemC. The
control extension would be responsible for control signals.

Change-Id: I35ba8610210e0750917a78fa0adb321991968f6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59649
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
 2022-06-15 08:02:21 +00:00
Gabe Black
9e821b3233 cpu: Switch to the (get|set)Reg API in the checker CPU. 
Change-Id: I7ab1319ae6fc6d0d5bc62322fbe92c7131ce6403
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49777
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 22:11:36 +00:00
Giacomo Travaglini
87c2f36fa8 cpu: Fix InvalidRegClass access in CheckerCPU 
This is fixing long regressions:

https://jenkins.gem5.org/job/nightly/252/console

Change-Id: Ica56b950e5091d3357060f566e02195cc8136924
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60449
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-06-08 21:58:27 +00:00
Hoa Nguyen
02ed53ff6b stdlib,configs,tests: Examples of saving/restoring checkpoints 
This change consists of two scripts,
- riscv-hello-save-checkpoint.py: runs the first million ticks of the
simulation and save a checkpoint.
- riscv-hello-load-checkpoint.py: loads the above checkpoint, and runs
the rest of the simulation.

This change also adds the two scripts as part of quick tests.

Change-Id: I7bd97ba953fab52f298cbbcf213f2ea5c185cc38
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58829
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2022-06-08 21:51:52 +00:00
Gabe Black
179e4ad070 cpu: Fix style in cpu/timing_expr.cc. 
Change-Id: Ic3d9d870b2f7648fd8b215692c33580f05cdb364
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49775
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-08 20:36:07 +00:00
Gabe Black
0d18112f0f arch-power: Revamp float regs. 
Change-Id: I77a5a021da82c8528d092f7363a927dec224d5ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49771
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 20:35:16 +00:00
Gabe Black
23087f124a arch-power: Revamp int registers. 
Change-Id: I2e11601a6bf37d6ca161d0ce99d7bfff1ee2f0eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49770
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2022-06-08 20:35:01 +00:00
Gabe Black
112f4104b9 arch-arm: Fix up code related to the float reg file? 
ARM no longer uses it's primitive FloatRegClass register file, but the
code in tarmac_record.cc still seems to access it? Should this code be
deleted, or rewritten to use the vector register file?

This code was used in the 32 bit ARM KVM code as well.

Change-Id: I6ed2ed9ae853fa4313294fdde4ce08d134fc12da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49767
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-08 20:34:38 +00:00
Gabe Black
7f61db0f2e arch-arm: Switch from (set|read)Vec* to (get|set)Reg* accessors. 
Change-Id: I9e9b51b965402b3c8c94cce1593d62aa2118cd0c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49766
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 20:34:19 +00:00
Gabe Black
8f180369fd arch-arm: Rework the condition code regs. 
Change-Id: I0cfaaecb4da27cecc3dc6464b094fe2cf03b407a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49765
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-08 20:34:01 +00:00
Gabe Black
5efe4d4a3a arch-arm: Rework the int regs. 
Change-Id: I352e12d4742f0771859bdbf9634ac87e2c153427
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49764
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-08 20:33:42 +00:00
Matthias Jung
a52274a075 systemc: gem5 initiator TLM target example 
This example shows how to connect a simple TLM target to a gem5 traffic
generator. It uses the systemc_within_gem5 feature.

Change-Id: I9755cc662c5c034cffe03d99dcbe6bed23176b16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60269
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 17:33:12 +00:00
Bobby R. Bruce
f6ca466d09 tests: Add ISA test for stdlib 'requires' function 
Change-Id: I94192fa7f026abc8bc48c6de06ce0471a0515f32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60429
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 17:24:13 +00:00
Bobby R. Bruce
74942dc08e tests: Add tests for 'gem5.runtime.get_supported_isas' 
Change-Id: I4224cca9384af48c1e090d9b34627cae8ce00715
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60094
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-06-08 17:24:13 +00:00
Bobby R. Bruce
fda4137780 stdlib: Refactor multi-isa stdlib incorporation 
The previous version of this requires the user to set the `main-isa` at
runtime, as inplemented via
https://gem5-review.googlesource.com/c/public/gem5/+/55423. In order to
keep this work in-sync with how the multi-protocol approach will work
(see here: https://gem5-review.googlesource.com/c/public/gem5/+/59193),
it's been decided this should be set at compile time. With this we are
keeping the `TARGET_ISA` parameter. If this is set, this is the de
facto "main-isa". The `main-isa` parameter has been removed from the
gem5 command-line.

If the `TARGET_ISA` parameter is not set, but only one ISA is compiled,
then this single ISA is assumed to be the `main-isa` for simulation. If
neither `TARGET_ISA` is set or the binary is compiled to a single ISA,
an exception is thrown when `get_runtime_isa` is called.

At the time of writing this change is moot as the multi-isa work has
yet to be merged into the gem5 develop branch. It exists here:
https://gem5.googlesource.com/public/gem5/+/refs/heads/multi-isa and
will need refactored to work with this patch.

The multi-isa tests have been updated. As we no longer pass the
`main-isa` as a run-time parameter, we remove many tests which validated
this use-case.

Change-Id: If3366212fe1dacbae389efa43d79349deb907537
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59949
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2022-06-08 17:24:13 +00:00
Gabe Black
7e6fd8423e arch-x86: Rework float regs for getReg and setReg. 
Change-Id: I9ef7493225678923964721bf91f2fd2c43d4d1e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49760
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
 2022-06-08 07:09:32 +00:00
Gabe Black
d40bedc019 arch-x86: Rework CCRegs for getReg, setReg. 
Put them in a namespace, make them match the style guide, turn them into
RegIds, and replace readCCReg and setCCReg with getReg and setReg.

Change-Id: I46f766a544696caf3dcfc6b34b50f02b86766da4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49759
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:09:18 +00:00
Gabe Black
84ae0afa59 arch-x86: Put misc reg indexes into a name space. 
Also make them match the style guide.

Change-Id: I845f141f85d4499a5acf56c2161240764906a232
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49758
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
 2022-06-08 07:09:05 +00:00
Gabe Black
c4ea43f462 arch-x86: De-indent arch/x86/regs/misc.hh. 
Namespaces are not supposed to increase indentation.

Change-Id: I6736c5049ea8d853dc67f319192b9eaa97d27cb1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49757
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:08:50 +00:00
Gabe Black
88143c940b arch-x86: Convert segment indices to fit the style guide. 
Capitalize only their first letter, and use a namespace to namespace
them instead of a SEGMENT_REG_ prefix.

Change-Id: I69778c8d052ad6cc0ffd9e74dd1c643e9d28048d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49756
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
 2022-06-08 07:08:37 +00:00
Gabe Black
b836e6a495 arch-x86: Stop using (read|set)IntReg. 
These accessors just translate a RegIndex x into a RegId(IntRegClass, x)
and then does (get|set)Reg. Instead, we can just do (get|set)Reg
directly, since all the integer register named constants are just RegIds
now.

Change-Id: I9e7551ed66a6979e83c745f2891c452ded1eff0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49755
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:08:23 +00:00
Gabe Black
16f7b17fc5 arch-x86: Convert the int register constants from RegIndex to RegId. 
This will let them be used in APIs which expect either, and will help
transition between the two.

Change-Id: I73fc9e55418ad3ab9e08406f0928aa4b1ef30a49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49754
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:08:10 +00:00
Gabe Black
ee1262ae40 cpu: constexpr most of RegId's methods, and add a RegIndex operator. 
That will let a RegId be used where a RegId is required, but also let it
be downconverted into a scalar RegIndex if using an older API. Note that
this does *not* let you automatically upconvert from a RegIndex into a
RegId, since there would be no way to know what class of register to
use.

Change-Id: I5fff224dce5e02959d5fc3e717014bf7eaa9c022
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49753
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-08 07:07:53 +00:00
Gabe Black
9b2328d637 arch-x86: Use a namespace for integer registers. 
Also reformat the integer register index constants to fit with the style
guide, ie remove the INTREG_ prefix (replaced by the namespace) and
captialize only the first letter.

Change-Id: I682a337944f64a1b96b971a1beb895289b9d299e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49752
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:07:44 +00:00
Gabe Black
a52f92dccb arch: Remove plumbing for an op_idx value in ISA operands. 
Now that op_idx is trivial to calculate (just src_reg_idx or
dest_reg_idx), there's no need to have the indirection and extra
mechanism to funnel a precalculated value around.

Change-Id: I37daeb646b85e050c4b832af28d054ecc3c338b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49750
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2022-06-08 07:07:35 +00:00
Gabe Black
a1b439f91c arch: Remove plumbing for operand predication. 
The operand predication mechanism has been replaced by mapping
predicate-false register reads/writes to InvalidRegClass.

Change-Id: I57e7aadb7a0d682c225f6a5fe673cba8ddf1c4f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49749
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:07:15 +00:00
Gabe Black
7216ff214f arch-x86: Turn predicate-false CC regs into InvalidRegClass. 
This makes the (somewhat faulty) predicated register mechanism
unnecessary.

Change-Id: Id053760defd6ac9aaec95c165df5403e7fcb354f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49748
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 07:07:02 +00:00
Earl Ou
0260fe7da9 fastmodel: follow .sgproj SIMGEN_COMMAND_LINE 
ARM's .sgproj has SIMGEN_COMMAND_LINE to be fed into simgen when
running. However, simgen itself doesn't parse that option and apply. We
need to parse it by ourself and pass the arg to simgen when invoking.

Change-Id: I43b131a1ca9f98891ab390de583589a710e7c812
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60369
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-08 00:30:16 +00:00
Hoa Nguyen
c088af945e stdlib: Add checkpoint to Simulator 
This change modifies the Simulator constructor to optionally
take a checkpoint directory as an input so that the m5 can
instantiate from the saved checkpoint.

A new method is also added to the Simulator class. The function
will save the checkpoint to the specified directory.

Change-Id: I58b686b6b4f69260ab45709c6ef0bddf4539f0c4
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58789
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-07 21:18:12 +00:00
Gabe Black
851c86af6d arch: Improve the regular expression that finds operands. 
This regular expression currently has a negative lookbehind assertion
that the operand name isn't preceded by any numbers or letters. Expand
that to also include the : character, since no operand should have a
namespace specifier in front of it.

Change-Id: I0bd84b69b9dad278191831d82db762ae75ce4bf1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49751
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-07 19:00:12 +00:00
Gabe Black
a40950a5c9 arch,cpu: Remove the idea of a zero register. 
This is now handled by using the InvalidRegClass.

Change-Id: If43d8f27cfebc249ec6600847bcfd98c9e94cf40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49746
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-07 18:26:33 +00:00
Gabe Black
caffb4e1ff arch: Detect and convert zero registers to InvalidRegClass. 
Change-Id: Ic5e070d303bf05ed1640b441e498d879764b8778
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49745
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-07 18:26:22 +00:00
Gabe Black
8d11bc31b5 arch-arm: Fix dangling pointer to unnamed temporary in nativetrace.cc. 
Name the temporary.

Change-Id: I51d0eaa4a6759c3f288b4215db880af6135e9107
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60409
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-07 06:37:04 +00:00
Kaustav Goswami
c64f296695 stdlib: AbstractCore calls ArmV8KvmCPU class for aarch64 
This change calls the stdlib's correct ArmKvmCPU class (ArmKvmCPU or
ArmV8KVMCPU) depending upon the host machine's architecture when
using KVM cores with ARM ISA.

Change-Id: I2ba8070825503659cd93da15da8507528d7f12ad
Signed-off-by: Kaustav Goswami <kggoswami@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60329
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
 2022-06-06 18:56:06 +00:00
Bobby R. Bruce
f2a7a46db0 tests: Disable max_tick for asmtests 
These tests are very short and do not need to be limited by a set number
of ticks. They should be ran to completion.

Change-Id: I0ea2193efe01e5ed01afd10d8e5934512a4027c6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60251
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-06 18:46:52 +00:00
ntampouratzis
f3e9484969 arch-riscv,dev: Add PCI Host to RISCV Board 
Add GenericRiscvPciHost to RISCV Board. In addition, we connect the IGbE_e1000
ethernet card to PCI in order to verify the correct functionality.

To be noticed that we build a new Linux kernel v5.10 (with Bootloader) according to these steps (
https://github.com/gem5/gem5-resources/tree/stable/src/riscv-fs) adding the the PCI and e1000 drivers:

CONFIG_PCI_SYSCALL=y
CONFIG_PCI_STUB=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_NET_VENDOR_INTEL=y
CONFIG_E1000=y
CONFIG_E1000E=y
CONFIG_IGB=y
CONFIG_NET_VENDOR_I825XX=y

Here you can find the kernel.config and our prebuild kernel to verify the correct behaviour:
https://www.dropbox.com/scl/fo/sz9s37vybpfecbfilxqzz/h?dl=0&rlkey=klkxh33anjqnzwj3sopucqqzx

You can verify it with the following command:
build/RISCV/gem5.fast configs/example/gem5_library/riscv-fs.py

Dear Jason Lowe-Power,

Thank you for your comments! We have addressed all of them.

Best regards,
Nikolaos Tampouratzis

Dear Jason,

I think that it is ok now! :)

Thanks!

Best regards,
Nikolaos Tampouratzis

Change-Id: Id27d84a5588648b82cbfd5c88471927157ae6759
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59969
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-06 18:42:12 +00:00
Ayaz Akram
c685cfcb7e mem: Add support for min reads per switch 
Similar to minimum writes per switch, this change adds support
for minimum reads per switch. This helps to reduce the read to
write transitions, which helps mixed read/write traffic patterns.

Change-Id: I1f9619c984ba14d2cca09f43bc16863283ea64a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59735
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Wendy Elsasser <welsasser@rambus.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2022-06-06 18:31:06 +00:00
Ayaz Akram
84949089a1 mem: Add HBM2 pseudo channel interface configuration 
Change-Id: I5826e50a35ee9dda054a164cfda616ca0ffe82e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59734
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Wendy Elsasser <welsasser@rambus.com>
 2022-06-06 18:31:06 +00:00
Ayaz Akram
feceff7723 mem: Support for separate tRCD and tCL for reads/writes 
HBM2 has asynchronous read/write timings (tRCD, tCL). This change
updates dram interface in gem5 to allow using separate values of
tRCD and tCL for reads and writes.

Change-Id: I56bfa9519cedad89cc2d4c163efc7126f609f15a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59733
Reviewed-by: Wendy Elsasser <welsasser@rambus.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2022-06-06 18:31:06 +00:00