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cpu: Switch to the (get|set)Reg API in the checker CPU.

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Change-Id: I7ab1319ae6fc6d0d5bc62322fbe92c7131ce6403
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49777
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-29 00:43:39 -07:00
parent 87c2f36fa8
commit 9e821b3233
1 changed files with 14 additions and 20 deletions
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34
src/cpu/checker/cpu_impl.hh
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@@ -584,19 +584,16 @@ Checker<DynInstPtr>::copyResult(
case InvalidRegClass:
break;
case IntRegClass:
thread->setIntReg(idx.index(), mismatch_val.as<RegVal>());
break;
case FloatRegClass:
thread->setFloatReg(idx.index(), mismatch_val.as<RegVal>());
case VecElemClass:
case CCRegClass:
thread->setReg(idx, mismatch_val.as<RegVal>());
break;
case VecRegClass:
thread->setVecReg(idx, mismatch_val.as<TheISA::VecRegContainer>());
break;
case VecElemClass:
thread->setVecElem(idx, mismatch_val.as<RegVal>());
break;
case CCRegClass:
thread->setCCReg(idx.index(), mismatch_val.as<RegVal>());
{
auto val = mismatch_val.as<TheISA::VecRegContainer>();
thread->setReg(idx, &val);
}
break;
case MiscRegClass:
thread->setMiscReg(idx.index(), mismatch_val.as<RegVal>());
@@ -614,19 +611,16 @@ Checker<DynInstPtr>::copyResult(
case InvalidRegClass:
break;
case IntRegClass:
thread->setIntReg(idx.index(), res.as<RegVal>());
break;
case FloatRegClass:
thread->setFloatReg(idx.index(), res.as<RegVal>());
case VecElemClass:
case CCRegClass:
thread->setReg(idx, res.as<RegVal>());
break;
case VecRegClass:
thread->setVecReg(idx, res.as<TheISA::VecRegContainer>());
break;
case VecElemClass:
thread->setVecElem(idx, res.as<RegVal>());
break;
case CCRegClass:
thread->setCCReg(idx.index(), res.as<RegVal>());
{
auto val = res.as<TheISA::VecRegContainer>();
thread->setReg(idx, &val);
}
break;
case MiscRegClass:
// Try to get the proper misc register index for ARM here...