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88f604b7bff3d7e327ea72d38010cf82204298db
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Author SHA1 Message Date
Éder F. Zulian
88f604b7bf Doc improved 2018-07-02 12:11:14 +02:00
Éder F. Zulian
6b8a123675 coding style 2018-07-02 07:59:22 +02:00
Éder F. Zulian
81914bc25f Improvement 2018-07-02 07:58:03 +02:00
Éder F. Zulian
8f9751f30f Refresh modes 1X, 2X and 4X. 2018-07-02 07:50:28 +02:00
Éder F. Zulian
af6d1d1439 Default simulation properly set 2018-06-28 15:12:22 +02:00
Éder F. Zulian
0a992391d2 Following changes: 
Show rgr related config during initialization.
ORGR in traceAnalyzer.
Submodule drampower set properly (point to rgr branch).
New config for row increment (selective ref.).
Specific simulations NO REF. and AR with close page policy.
Simulation files ddr4 1, 2, 4 x mode open, close page policy, no ref, ar, rgr, orgr.
New config for number of auto-ref. cmds in 64 ms.
New traces for ddr4.
New spec for dd4 16Gb after Christian's corrections.
Initial offset for bankwise logic (if zeroed, for research).
ORGR/RGR.
Flex. ORGR/RGR.
Bankwise flex. refresh.
Small schanges.
RGR flex test files.
Doc updated.
 2018-06-28 14:35:14 +02:00
fzeder
0fceb87619 Merge pull request #203 from gorodeck/vdd 
Fixed Power Values for DDR3
 2018-06-25 15:00:17 +02:00
Doris Gulai
564e9895c0 Fixed Power Values for DDR3 2018-06-25 13:40:10 +02:00
Éder F. Zulian
93c8421d95 pack script 2018-06-25 09:14:25 +02:00
Éder F. Zulian
024bad03bb fix 2018-06-22 10:14:23 +02:00
Éder F. Zulian
5342c07976 scripts and doc updated 2018-06-20 12:45:08 +02:00
Matthias Jung
f09d6d3cfc Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 2018-06-08 20:18:49 +02:00
Matthias Jung
412630122c Added Information about Windows Compiling 2018-06-08 14:30:53 +02:00
Matthias Jung
e75dbcd098 Add README.md to DRAMSys.pro 2018-06-08 14:28:42 +02:00
Éder F. Zulian
b59dd058ca Trace list made optional in DRAMSylva 2018-06-04 18:38:12 +02:00
Éder F. Zulian
8d6b605419 Doc updated 2018-06-04 17:03:34 +02:00
Éder F. Zulian
8a787ad14f Simulation ID (optional) 
If a simulation file is passed as argument to DRAMSys the simulation ID is
prepended to the simulation name if found.

E.g.:
<simulation>
    <!-- Simulation file identifier -->
    <simulationid id="ddr3-example"></simulationid>

    ...

</simulation>
 2018-06-04 16:54:14 +02:00
Éder F. Zulian
457dce57b2 Some warnings eliminated. 
9 warnings to go, all from external code (e.g., systemc lib).
 2018-06-04 16:44:36 +02:00
Éder F. Zulian
136da88b74 Fix bug introduced in pr#191 2018-06-04 16:38:21 +02:00
Éder F. Zulian
9945db4f4b doc updated 2018-05-30 10:12:40 +02:00
Éder F. Zulian
bf6558a231 doc updated 2018-05-29 19:17:19 +02:00
Éder F. Zulian
7aa8983051 PEP8 2018-05-29 19:09:30 +02:00
Éder F. Zulian
5b67f2b268 Coding-style applied the project. 
$ cd util
$ ./make_pretty.sh
 2018-05-29 11:38:54 +02:00
Éder F. Zulian
5a6aa137fa Reference to coding-style document on README.md 2018-05-28 17:48:25 +02:00
Éder F. Zulian
2b3c268093 trace_gen.py added to qt creator 2018-05-28 17:40:27 +02:00
Éder F. Zulian
ac95b6233b README updated 2018-05-25 17:29:59 +02:00
Éder F. Zulian
20428ec2f2 readme updated 2018-05-25 17:27:38 +02:00
Éder F. Zulian
f522eb417d README updated 2018-05-25 17:22:20 +02:00
Éder F. Zulian
c665ea166b README updated 
Trace generator script that for simple tests. The script can be easily changed
and provides a way to quickly generate accesses to all channels, all bank
groups, all banks, all rows and all columns of the memory.

Be aware that a trace which covers all rows and all columns may be huge
(several giga bytes) depending on your memory.
 2018-05-25 17:08:21 +02:00
fzeder
a881d1b7e6 Merge pull request #197 from sprado/feature 
TlmRecorder destructor fixed
 2018-05-25 16:25:07 +02:00
Eder F. Zulian
953902166e Using python3 print style 
Other changes:
- double increment in the clock cycle removed.
- bank_group --> bgroup
 2018-05-24 15:21:36 +02:00
Éder F. Zulian
e53945f873 Added support to bank groups 2018-05-24 14:49:22 +02:00
Éder F. Zulian
9891f0f77f Trace generator script. 
Trace generator script for a given address mapping. This script can be easily
modified for your needs.
 2018-05-24 12:17:50 +02:00
Eder F. Zulian
2c0e6ece30 Changes to get build working again after merging pr190 
See also:
Pull request #190
Issue #198
 2018-05-18 14:44:50 +02:00
Éder F. Zulian
7038b9211b PEP8 2018-05-18 13:36:42 +02:00
Éder F. Zulian
2d91748340 Fix: single quote 2018-05-18 13:33:29 +02:00
sprado
747dcbb777 TlmRecorder destructor fixed 2018-05-15 15:36:31 +02:00
Éder F. Zulian
db2b31ae4b Coding style script improved and doc updated 2018-04-12 23:25:26 +02:00
Éder F. Zulian
da565df24d Coding-style script improved 2018-04-12 23:20:10 +02:00
Éder F. Zulian
ad51dcfdb1 Script to apply coding-style rules. 2018-04-12 23:16:59 +02:00
fzeder
4b0681b31c Merge pull request #190 from jfeldman/develop 
JSON Address Decoder (the file extension is used to choose the decoder)
 2018-04-12 15:52:37 +02:00
Matthias Jung
5654496e85 Merge branch 'master' of git.rhrk.uni-kl.de:EIT-Wehn/dram.vp.system 2018-04-12 13:48:12 +02:00
Matthias Jung
41dad5ce00 Some more features for NN DRAM modeling 2018-04-12 13:47:48 +02:00
Éder F. Zulian
61fabe7d19 Coding-style doc updated 2018-04-11 20:10:35 +02:00
Éder F. Zulian
73c95f8f8f Coding-style doc updated 2018-04-11 19:55:14 +02:00
Johannes Feldmann
7a715d171f Fixed a bug in the XOR mapping 2018-04-10 16:36:57 +02:00
Éder F. Zulian
2fc774eece DRAMSys.astylerc, doc and install script updated 2018-04-09 08:34:47 +02:00
Éder F. Zulian
d02e380994 dramsys.astylerc --> DRAMSys.astylerc 2018-04-06 14:27:47 +02:00
Éder F. Zulian
f851de136c Doc improved, added astyle to the install list 2018-04-06 11:49:24 +02:00
fzeder
367f3eb9fd Merge pull request #192 from jfeldman/master 
Added astyle file and changed all project files accordingly.
 2018-04-06 10:58:23 +02:00