README updated

README.md

@@ -793,10 +793,11 @@ For more information check the documentation in [DRAMSylva folder](DRAMSys/libra
 
 #### Trace Generator Script
 
-A python script for generating simple traces for tests is provided.
+A python script for generating input traces for simple tests is provided.
 [trace_gen.py](DRAMSys/library/resources/scripts/trace_gen.py).
 
 Example on how to run the script:
+
 ``` bash
 $ cd DRAMSys/library/resources/scripts
 $ ./trace_gen.py > trace.stl
@@ -805,12 +806,32 @@ $ ./trace_gen.py > trace.stl
 Now change your configuration file to use the new generated trace file and run
 your simulation.
 
+The script can be easily changed and provides a way to quickly generate
+accesses to all channels, all bank groups, all banks, all rows and all columns
+of a memory.
+    
+**Be aware that a trace which covers all rows and all columns may be huge
+(several gigabytes) depending on your memory.**
+
+The defaul values in the script serve as an example. They consider the address
+mapping that follows.
 
-You can open the script with a text editor and change some parameters to fit your needs.
 ```
-# Transaction type (read or write)
-transaction = 'read'
+DDR3-SDRAM DIMM Characteristics:
+Byte Offset (Y): 8    [0:2]   (8-byte-wide memory module, i.e., 64-bit-wide data bus) -> 3 bit
+Cols        (C): 1K   [3:12]  (A0 - A9)   -> 10 bit
+Rows        (R): 128K [13:29] (A0 - A16)  -> 17 bit
+Bank        (B): 8    [30:32] (BA0 - BA2) -> 3  bit
 
+3 3 3 | 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 | 1 1 1
+2 1 0 | 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 | 2 1 0 9 8 7 6 5 4 3 | 2 1 0
+B B B | R R R R R R R R R R R R R R R R R | C C C C C C C C C C | Y Y Y
+```
+
+The parameters for the DDR3-SDRAM DIMM with address mapping presented above
+the configuration are presented below. 
+
+```
 # Channel information.
 num_ch = 1              # Number of channels
 ch_shift = 34           # Shift to reach the frist bit reserved for channels in the address
@@ -838,14 +859,11 @@ col_mask = 0x3ff        # Mask for all column bits in the address
 
 # Burst length
 burst_len = 8
-
-# Initial clock cycle
-clock_cycle = 0
-
-# Clock cycle increment between two accesses
-clock_increment = 10
 ```
 
+Open the script with a text editor and change some parameters to fit your
+needs.
+
 #### DRAMsys Diagrams
 
 - **TLM Approximately Timed (AT)**