README updated

Trace generator script that for simple tests. The script can be easily changed
and provides a way to quickly generate accesses to all channels, all bank
groups, all banks, all rows and all columns of the memory.

Be aware that a trace which covers all rows and all columns may be huge
(several giga bytes) depending on your memory.

README.md

@@ -791,6 +791,61 @@ The script runs one instance of DRAMSys for each of the files in the list. **The
 
 For more information check the documentation in [DRAMSylva folder](DRAMSys/library/resources/scripts/DRAMSylva).
 
+#### Trace Generator Script
+
+A python script for generating simple traces for tests is provided.
+[trace_gen.py](DRAMSys/library/resources/scripts/trace_gen.py).
+
+Example on how to run the script:
+``` bash
+$ cd DRAMSys/library/resources/scripts
+$ ./trace_gen.py > trace.stl
+```
+
+Now change your configuration file to use the new generated trace file and run
+your simulation.
+
+
+You can open the script with a text editor and change some parameters to fit your needs.
+```
+# Transaction type (read or write)
+transaction = 'read'
+
+# Channel information.
+num_ch = 1              # Number of channels
+ch_shift = 34           # Shift to reach the frist bit reserved for channels in the address
+ch_mask = 0x1           # Mask for all channel bits in the address
+
+# Bank group information.
+num_bank_groups = 1     # Number of bank groups
+bgroup_shift = 33   	# Shift to reach the frist bit reserved for bank groups in the address
+bgroup_mask = 0x1   	# Mask for all bits in the address related to bank groups
+
+# Bank information
+num_banks = 8           # Number of banks
+bank_shift = 30         # Shift to reach the frist bit reserved for banks in the address
+bank_mask = 0x7         # Mask for all bank bits in the address
+
+# Row information
+num_rows = 128 * 1024   # Number of rows
+row_shift = 13          # Shift to reach the frist bit reserved for rows in the address
+row_mask = 0x1ffff      # Mask for all row bits in the address
+
+# Column information
+num_col = 1 * 1024      # Number of columns
+col_shift = 3           # Shift to reach the frist bit reserved for columns in the address
+col_mask = 0x3ff        # Mask for all column bits in the address
+
+# Burst length
+burst_len = 8
+
+# Initial clock cycle
+clock_cycle = 0
+
+# Clock cycle increment between two accesses
+clock_increment = 10
+```
+
 #### DRAMsys Diagrams
 
 - **TLM Approximately Timed (AT)**