Added support to bank groups
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@@ -73,11 +73,17 @@ import ctypes
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# Transaction type (read or write)
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transaction = 'read'
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# Channel information. This is DRAMSys specific. The channel bits come after
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# the last regular address bit.
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# Channel information. If your address mapping does not have bank groups keep
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# it equal to 1 and set the shift to the extreme left of the address.
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num_ch = 1 # Number of channels
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ch_shift = 33 # Shift to reach the frist bit reserved for channels in the address
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ch_mask = 0x3 # Mask for all channel bits in the address
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ch_shift = 34 # Shift to reach the frist bit reserved for channels in the address
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ch_mask = 0x1 # Mask for all channel bits in the address
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# Bank group information. If your address mapping does not have bank groups
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# keep it equal to 1 and set the shift to the extreme left of the address.
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num_bank_groups = 1 # Number of bank groups
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bank_group_shift = 33 # Shift to reach the frist bit reserved for bank groups in the address
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bank_group_mask = 0x1 # Mask for all bits in the address related to bank groups
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# Bank information
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num_banks = 8 # Number of banks
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@@ -118,13 +124,15 @@ def set_bits(mask, shift, val, v):
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address = 0
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for ch in range(0, num_ch):
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address = set_bits(ch_mask, ch_shift, address, ch)
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for b in range(0, num_banks):
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address = set_bits(bank_mask, bank_shift, address, b)
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for row in range(0, num_rows):
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address = set_bits(row_mask, row_shift, address, row)
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clock_cycle = clock_cycle + clock_increment
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for col in range(0, num_col, burst_len):
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address = set_bits(col_mask, col_shift, address, col)
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print "# clock cycle: {0:d} | {1} | address: 0x{2:010X} | channel: {3} | bank: {4} | row: {5} | column: {6}".format(clock_cycle, transaction, address, ch, b, row, col)
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print "{0:d}:\t{1}\t0x{2:010X}".format(clock_cycle, transaction, address)
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clock_cycle = clock_cycle + clock_increment
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for bg in range(0, num_bank_groups):
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address = set_bits(bank_group_mask, bank_group_shift, address, bg)
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for b in range(0, num_banks):
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address = set_bits(bank_mask, bank_shift, address, b)
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for row in range(0, num_rows):
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address = set_bits(row_mask, row_shift, address, row)
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clock_cycle = clock_cycle + clock_increment
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for col in range(0, num_col, burst_len):
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address = set_bits(col_mask, col_shift, address, col)
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print "# clock cycle: {0:d} | {1} | address: 0x{2:010X} | channel: {3} | bank group: {4} | bank: {5} | row: {6} | column: {7}".format(clock_cycle, transaction, address, ch, bg, b, row, col)
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print "{0:d}:\t{1}\t0x{2:010X}".format(clock_cycle, transaction, address)
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clock_cycle = clock_cycle + clock_increment
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