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PEP8

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Éder F. Zulian
2018-05-29 19:09:30 +02:00
parent 5b67f2b268
commit 7aa8983051
1 changed files with 4 additions and 4 deletions
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8
DRAMSys/library/resources/scripts/trace_gen.py
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@@ -131,7 +131,7 @@ for ch in range(0, num_ch):
for row in range(0, num_rows):
address = set_bits(row_mask, row_shift, address, row)
for col in range(0, num_col, burst_len):
address = set_bits(col_mask, col_shift, address, col)
print('# clock cycle: {0:d} | {1} | address: 0x{2:010X} | channel: {3} | bank group: {4} | bank: {5} | row: {6} | column: {7}'.format(clock_cycle, transaction, address, ch, bg, b, row, col))
print('{0:d}:\t{1}\t0x{2:010X}'.format(clock_cycle, transaction, address))
clock_cycle = clock_cycle + clock_increment
address = set_bits(col_mask, col_shift, address, col)
print('# clock cycle: {0:d} | {1} | address: 0x{2:010X} | channel: {3} | bank group: {4} | bank: {5} | row: {6} | column: {7}'.format(clock_cycle, transaction, address, ch, bg, b, row, col))
print('{0:d}:\t{1}\t0x{2:010X}'.format(clock_cycle, transaction, address))
clock_cycle = clock_cycle + clock_increment