diff --git a/DRAMSys/library/resources/scripts/trace_gen.py b/DRAMSys/library/resources/scripts/trace_gen.py
index cbbff5a2..2efb4012 100755
--- a/DRAMSys/library/resources/scripts/trace_gen.py
+++ b/DRAMSys/library/resources/scripts/trace_gen.py
@@ -131,7 +131,7 @@ for ch in range(0, num_ch):
             for row in range(0, num_rows):
                 address = set_bits(row_mask, row_shift, address, row)
                 for col in range(0, num_col, burst_len):
-                        address = set_bits(col_mask, col_shift, address, col)
-                        print('# clock cycle: {0:d} | {1} | address: 0x{2:010X} | channel: {3} | bank group: {4} | bank: {5} | row: {6} | column: {7}'.format(clock_cycle, transaction, address, ch, bg, b, row, col))
-                        print('{0:d}:\t{1}\t0x{2:010X}'.format(clock_cycle, transaction, address))
-                        clock_cycle = clock_cycle + clock_increment
+                    address = set_bits(col_mask, col_shift, address, col)
+                    print('# clock cycle: {0:d} | {1} | address: 0x{2:010X} | channel: {3} | bank group: {4} | bank: {5} | row: {6} | column: {7}'.format(clock_cycle, transaction, address, ch, bg, b, row, col))
+                    print('{0:d}:\t{1}\t0x{2:010X}'.format(clock_cycle, transaction, address))
+                    clock_cycle = clock_cycle + clock_increment