Lukas Steiner
|
3be2d9f56b
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Include average bandwidth windowing.
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2020-11-11 09:51:31 +01:00 |
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Lukas Steiner
|
ed8ee0ec06
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Merge branch 'rambus_scheduler' into DDR5
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2020-11-04 16:50:06 +01:00 |
|
Lukas Steiner
|
ccf686baf6
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Merge branch 'traceAnalyzer_LatencyAnalysis' into rambus_scheduler
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2020-11-04 16:48:31 +01:00 |
|
Lukas Steiner
|
fe53143f64
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Merge branch 'rambus_scheduler' into DDR5
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2020-11-04 16:04:25 +01:00 |
|
Lukas Steiner
|
7d7dba4c68
|
Reset simulator config.
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2020-11-04 16:03:49 +01:00 |
|
Lukas Steiner
|
cc3a7a617b
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Merge branch 'traceAnalyzer_LatencyAnalysis' into rambus_scheduler
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2020-11-04 15:58:55 +01:00 |
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Lukas Steiner
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d723306130
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Merge branch 'rambus_scheduler' into DDR5
# Conflicts:
# DRAMSys/library/src/common/TlmRecorder.cpp
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2020-11-04 15:56:26 +01:00 |
|
Lukas Steiner
|
6108c6ca93
|
Add max buffer depth to general info table.
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2020-11-04 15:46:08 +01:00 |
|
Matthias Jung
|
5b4f5e0c74
|
Added Queue Analysis Plot
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2020-11-04 15:36:13 +01:00 |
|
Lukas Steiner
|
d7409542a1
|
Add simple arbiter.
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2020-11-04 15:26:51 +01:00 |
|
Lukas Steiner
|
d85790ad63
|
Add shared scheduler buffer counter.
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2020-11-04 13:26:28 +01:00 |
|
Lukas Steiner
|
0fec34240d
|
Add scheduler buffer depth recording.
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2020-11-04 11:15:22 +01:00 |
|
Lukas Steiner
|
e5d340a603
|
Merge branch 'rambus_scheduler' into DDR5.
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2020-11-03 15:13:19 +01:00 |
|
Matthias Jung
|
11bfed8b6a
|
Finished Latency Analysis Tool in TA
|
2020-11-02 19:53:53 +01:00 |
|
Lukas Steiner
|
9315cd1345
|
Set payload IDs at correct time.
|
2020-10-28 11:59:09 +01:00 |
|
Lukas Steiner
|
d2878c62f2
|
Add reorder arbiter.
|
2020-10-28 11:18:13 +01:00 |
|
Matthias Jung
|
c744c43ab2
|
Added first latency analysis
|
2020-10-27 21:29:39 +01:00 |
|
Lukas Steiner
|
fe1d8eafdd
|
Code cleanup.
|
2020-10-27 16:41:00 +01:00 |
|
Lukas Steiner
|
2d507fb327
|
Decrement active transactions after BEGIN_RESP.
|
2020-10-27 16:16:48 +01:00 |
|
Lukas Steiner
|
f6752cb09a
|
Improved arbiter with thread and channel queues.
|
2020-10-27 16:02:11 +01:00 |
|
Lukas Steiner
|
ac670f2ea7
|
Merge branch 'rambus_scheduler' into DDR5
|
2020-10-27 10:04:15 +01:00 |
|
Lukas Steiner
|
5d6042a16a
|
Renaming of payload IDs in arbiter.
|
2020-10-27 09:57:48 +01:00 |
|
Lukas Steiner
|
2c7f555172
|
Add threadPayloadID.
|
2020-10-26 14:36:35 +01:00 |
|
Lukas Steiner
|
baf2440a4d
|
Change payloadID to channelPayloadID.
|
2020-10-26 14:15:06 +01:00 |
|
Lukas Steiner
|
b70c3351d3
|
Prepare arbiter for reorder buffer.
|
2020-10-26 13:54:11 +01:00 |
|
Lukas Steiner
|
3af9159b44
|
Missing cmake changes.
|
2020-10-26 09:10:35 +01:00 |
|
Lukas Steiner
|
ffca62be70
|
Renaming scheduler buffer to buffer counter.
|
2020-10-26 09:05:50 +01:00 |
|
Lukas Steiner
|
11ec4036ee
|
Merge branch 'rambus_scheduler' into DDR5
# Conflicts:
# DRAMSys/library/src/configuration/memspec/MemSpec.h
# DRAMSys/library/src/controller/Controller.cpp
# DRAMSys/library/src/simulation/DRAMSys.cpp
# DRAMSys/library/src/simulation/DRAMSysRecordable.cpp
|
2020-10-26 08:37:59 +01:00 |
|
Lukas Steiner
|
e26a438d06
|
Code formatting.
|
2020-10-23 15:04:40 +02:00 |
|
Lukas Steiner
|
7bab23f80e
|
Move methods from config to memspec.
|
2020-10-23 15:00:49 +02:00 |
|
Lukas Steiner
|
bfb5f16563
|
Move getSimMemSizeInBytes to memspec.
|
2020-10-23 14:24:32 +02:00 |
|
Lukas Steiner
|
65d148b7a7
|
Improved configuration process.
|
2020-10-23 12:07:30 +02:00 |
|
Lukas Steiner
|
472c810f89
|
Add separate scheduler buffers (bankwise, separate read/write).
|
2020-10-22 16:41:49 +02:00 |
|
Lukas Steiner
|
f95a35e9e8
|
Merge branch 'develop' into DDR5
|
2020-10-22 14:10:24 +02:00 |
|
Lukas Steiner
|
27819b4a7b
|
Merge branch 'cpp_speedups' into 'develop'
Source code level speedups.
See merge request ems/astdm/dram.sys!269
|
2020-10-22 14:05:38 +02:00 |
|
Lukas Steiner
|
32c7148dd9
|
Set correct time of generation in arbiter.
|
2020-10-22 13:43:00 +02:00 |
|
Lukas Steiner
|
24b46811c0
|
Bugfix rank-to-rank dependencies.
|
2020-10-20 14:29:28 +02:00 |
|
Lukas Steiner
|
328a371843
|
Make controller easier to understand.
|
2020-10-20 09:32:28 +02:00 |
|
Lukas Steiner
|
0501bbd2c8
|
Add trace generator cpp file.
|
2020-10-08 16:00:52 +02:00 |
|
Lukas Steiner
|
e90df2174c
|
Directly call arbiter PEQ from trace player.
|
2020-10-08 14:42:00 +02:00 |
|
Lukas Steiner
|
432d37a9d7
|
File cleanup.
|
2020-10-06 15:51:24 +02:00 |
|
Lukas Steiner
|
d40462dcf7
|
Split up StlPlayer into source and header file.
|
2020-10-06 13:33:50 +02:00 |
|
Lukas Steiner
|
c79de8ac03
|
Fix wrong DDR5 timing dependencies.
|
2020-10-05 16:06:06 +02:00 |
|
Lukas Steiner
|
0e06c54917
|
Add more DDR5 memspecs.
|
2020-10-05 14:11:56 +02:00 |
|
Lukas Steiner
|
280a0b5f66
|
Set ddr5 example as default.
|
2020-10-02 16:28:05 +02:00 |
|
Lukas Steiner
|
6a8ce57d08
|
Add selection of fine granularity refresh mode.
|
2020-10-02 16:12:14 +02:00 |
|
Lukas Steiner
|
7f049645ca
|
Add DDR5 memspecs for different speed grades.
|
2020-10-02 15:16:42 +02:00 |
|
Lukas Steiner
|
af52d963b9
|
Merge branch 'cpp_speedups' into DDR5
|
2020-09-25 15:40:06 +02:00 |
|
Lukas Steiner
|
f0f9687ff4
|
Revert TLM_IGNORE_COMMAND.
|
2020-09-25 15:39:44 +02:00 |
|
Lukas Steiner
|
9d15d90a48
|
Merge branch 'cpp_speedups' into DDR5
|
2020-09-25 15:32:19 +02:00 |
|