Lukas Steiner
1863987af3
Merge branch 'feat/remove_resource_directory' into 'develop'
...
Remove the concept of a resource directory
See merge request ems/astdm/modeling.dram/dram.sys.5!115
2025-04-24 14:12:23 +00:00
Lukas Steiner
0f2be6ece5
Merge branch 'fix/lpddr5_ref' into 'develop'
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Fix LPDDR5 AllBank and Per2Bank Refresh
See merge request ems/astdm/modeling.dram/dram.sys.5!114
2025-04-24 14:07:59 +00:00
939fc90f98
Remove hard-coded subdirectory paths for configs
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Previously, the subdirectories in which the sub-json files were searched
in were hardcoded. Now, DRAMSys simply searches in the directory of the
base config, making this approach more flexible.
2025-04-15 14:56:35 +02:00
a97b676b92
Remove the concept of a resource directory
...
The concept of a resource directory was confusing, error-prone and
was only used to specify the directory of the base config json anyway.
Therefore, remove the concept of the resource directory and use the
parent directory of the base config directly.
2025-04-15 14:56:35 +02:00
330d5c77b6
Fix LPDDR5 regression test
2025-04-08 17:42:30 +02:00
Jonathan Hager
d773abc7ce
Updated unit tests for HBM2
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This is necessary, as recording the phases with tlmRecorders on the bus
changed the internal call order in the SystemC kernel. This leads to
different IDs in the database
2025-03-26 13:53:23 +01:00
dbb6636c5a
Fix LPDDR4 and LPDDR5 regression tests
2025-02-26 17:10:11 +01:00
6861576550
Implement tCCDR for HBM2 and fix bug with SID
2025-02-21 14:18:30 +01:00
Lukas Steiner
f223e6c500
Merge branch 'feat/hbm3_sid' into 'develop'
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Feat/hbm3 sid
See merge request ems/astdm/modeling.dram/dram.sys.5!96
2025-01-28 09:04:16 +00:00
581794b970
Allow responses to be sent back-to-back
2025-01-24 14:58:06 +01:00
ba94d9fd84
Have a one cycle END_RESP delay in the standard initiator
2025-01-24 14:43:06 +01:00
1225f6b044
Fix tests after ThinkDelayFw
2025-01-24 14:19:53 +01:00
7a8633d36e
Implement stack ID for HBM3
2025-01-13 15:36:05 +01:00
a82efdbb3a
Fix HBM3 regression test
2025-01-13 10:24:09 +01:00
aba5ba6e2e
Switch to Open page policy for HBM3 regression test
2025-01-10 16:42:42 +01:00
ca9ef16d0d
Remove unnecessary project() calls
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project() should only be called if the subdirectory, in fact, can be
built standalone.
2024-12-20 17:40:15 +01:00
5dd7c22a74
Refactor CMakeLists and GitLab CI/CD pipeline
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- Remove nested minimum required to supress warnings.
- Declare SystemC as system library to supress warnings in headers.
- Add a BUILD_SHARED_LIBS option
- Remove hardcoded STATIC in various add_library calls to honor the
BUILD_SHARED_LIBS option
- Remove _deps/ directory from the build directory in GitLab pipeline
- Remove *.tdb files after test stage in pipeline
- Set Ninja as the default generator for the dev preset and re-enable
colored diagnostics
2024-06-28 11:07:56 +02:00
539a525f3d
Fix DDR3 regression
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Using the new tCK entry in the memspecs, there was a small power deviation in the database
2024-02-23 12:04:29 +01:00
0ec6ea79ad
Migrate from clkMhz to tCK entry in memspecs
2024-02-23 12:04:22 +01:00
1ba63bd1f7
Add support for more than two XOR bits
2023-12-13 10:32:03 +01:00
b30df49d67
Use tCCDMW for masked write in LPDDR4
2023-08-21 09:26:05 +02:00
c5f1320399
Implement Partial Write for DDR5
2023-08-16 09:38:57 +02:00
a4342f7104
Update expected traces for DDR5 and HBM3
2023-08-15 11:28:03 +02:00
c352ca4372
Remove compare.sh scripts and invoke sqldiff directly from CMake
2023-08-15 10:58:10 +02:00
b988544be2
Enable PerBank refresh in HBM2,HBM3 regression test
2023-08-15 10:58:10 +02:00
0fc74e93c4
Add LPDDR5 regression test
2023-08-15 10:58:10 +02:00
81eaccf3d6
Add lastCommandOn{C,R}asBus != scMaxTime check for HBM2 and HBM3
2023-08-15 10:58:10 +02:00
599761c341
Add regression test for DDR5
2023-08-15 10:58:10 +02:00
42d1caa372
Add HBM3 regression test
2023-08-15 10:58:10 +02:00
Lukas Steiner
b3955d6d02
Update TUK to RPTU.
2023-05-25 15:15:52 +02:00
Lukas Steiner
e389474139
Remove deprecated gem5 files.
2023-05-23 14:53:06 +02:00
e040e087a2
Fix sporadic CI/CD failures due to race condition
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When running tests in parallel, there was a case where two tests
accessed the same generated resource. This is resolved by moving
all regression tests into their own subdirectory.
2023-04-26 15:25:05 +02:00
3d4f73361f
Fix timings in new StlPlayer
2023-04-13 11:21:36 +02:00
bd899a2104
Integrate regression tests with CTest
2023-03-10 13:32:55 +01:00
Lukas Steiner
823d473d97
Fix path in CI script.
2023-02-23 17:09:33 +01:00
Lukas Steiner
c4ca3d71d7
Reorganize config files, remove unused config.
2023-02-23 17:02:21 +01:00
Lukas Steiner
39b456d837
Use one stage for all tests.
2023-02-23 14:09:16 +01:00
Lukas Steiner
ac04ae66ce
Retry CI needs with coverage.
2023-02-23 13:56:15 +01:00
Lukas Steiner
661819f381
Path fix for DDR3 test.
2023-02-23 11:36:17 +01:00
Lukas Steiner
d736a2d25e
Fix regression tests, add DRAMPower.
2023-02-23 10:38:59 +01:00
Lukas Steiner
9760ffe5cc
Add regression test files.
2023-01-30 15:45:10 +01:00
