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Remove deprecated gem5 files.

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This commit is contained in:
Lukas Steiner
2023-05-23 14:53:06 +02:00
parent b2fd6f2a84
commit e389474139
14 changed files with 2 additions and 1704 deletions
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8
CMakeLists.txt
View File

@@ -84,7 +84,6 @@ set(DRAMSYS_EXTENSIONS_DIR "${CMAKE_CURRENT_SOURCE_DIR}/extensions")
option(DRAMSYS_BUILD_TESTS "Build DRAMSys unit tests" OFF)
option(DRAMSYS_VERBOSE_CMAKE_OUTPUT "Show detailed CMake output" OFF)
option(DRAMSYS_BUILD_CLI "Build DRAMSys Command Line Tool" ON)
option(DRAMSYS_WITH_GEM5 "Build DRAMSys with gem5 coupling" OFF)
option(DRAMSYS_WITH_DRAMPOWER "Build with DRAMPower support enabled." OFF)
option(DRAMSYS_ENABLE_EXTENSIONS "Enable proprietary DRAMSys extensions." OFF)
@@ -177,10 +176,3 @@ if(DRAMSYS_BUILD_TESTS)
include( CTest )
add_subdirectory(tests)
endif()
# Add DRAMSysgem5
#if(DEFINED ENV{GEM5} AND DRAMSYS_WITH_GEM5)
# message("== gem5 coupling included")
# add_subdirectory(gem5)
#endif()

6
README.md
View File

@@ -96,10 +96,8 @@ More information on the configuration can be found [here](configs/README.md).
## gem5 Coupling
There are two ways to couple DRAMSys with **gem5**:
- Use the official integration of DRAMSys in gem5.
- Compile gem5 as a shared library and link it with DRAMSys, which is described in more detail [here](src/gem5/README.md).
More information on how to use the DRAMSys integration in gem5 can be found in `ext/dramsys` of the gem5 repository.
- Use the official integration of DRAMSys in gem5. More information can be found in `ext/dramsys` of the gem5 repository.
- (Deprecated) Compile gem5 as a shared library and link it with DRAMSys, which is only supported in older versions of DRAMSys (tag v4.0).
## Acknowledgements

4
configs/README.md
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@@ -141,10 +141,6 @@ Syntax example:
10: read 0x400180
```
### Elastic Traces
More information about elastic traces can be found in the [gem5 readme](../src/gem5/README.md).
## Trace Player
A trace player is equivalent to a bus master device (processor, FPGA, etc.). It reads an input trace file and translates each line into a new memory request. By adding a new device element into the trace setup section one can specify a new trace player, its operating frequency and its trace file.

448
configs/gem5/gem5_etrace/config.ini
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@@ -1,448 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler membus physmem tlm voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
kernel_extras=
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=timing
mem_ranges=0:536870911:0:0:0:0
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TraceCPU
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer
checker=Null
clk_domain=system.clk_domain
cpu_id=0
dataTraceFile=../../DRAMSys/gem5/gem5_etrace/system.cpu.traceListener.data.gz
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
enableEarlyExit=false
eventq_index=0
freqMultiplier=1.0
function_trace=false
function_trace_start=0
instTraceFile=../../DRAMSys/gem5/gem5_etrace/system.cpu.traceListener.inst.gz
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_gating_on_idle=false
power_model=
profile=0
progressMsgInterval=0
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
sizeLoadBuffer=16
sizeROB=40
sizeStoreBuffer=16
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.dcache.replacement_policy
response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.membus.slave[2]
[system.cpu.dcache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.dcache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.dcache.replacement_policy
sequential_access=false
size=32768
tag_latency=2
warmup_percentage=0
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.icache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.icache.replacement_policy
response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.membus.slave[1]
[system.cpu.icache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.icache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.icache.replacement_policy
sequential_access=false
size=32768
tag_latency=2
warmup_percentage=0
[system.cpu.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
impdef_nop=false
midr=1091551472
pmu=Null
system=system
vecRegRenameMode=Full
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu_clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain
[system.cpu_voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
point_of_unification=true
power_model=
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.tlm.port
slave=system.system_port system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
range=0:134217727:0:0:0:0
[system.tlm]
type=ExternalSlave
addr_ranges=0:536870911:0:0:0:0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_data=transactor
port_type=tlm_slave
power_model=
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

BIN
configs/gem5/gem5_etrace/system.cpu.traceListener.data.gz LFS
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configs/gem5/gem5_etrace/system.cpu.traceListener.inst.gz LFS
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553
configs/gem5/gem5_se/hello-ARM/config.ini
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@@ -1,553 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler external_memory l2 membus physmem tol2bus voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=false
kernel_extras=
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=timing
mem_ranges=0:536870911:0:0:0:0
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dstage2_mmu=system.cpu.dstage2_mmu
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
istage2_mmu=system.cpu.istage2_mmu
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_gating_on_idle=false
power_model=
profile=0
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.dcache.replacement_policy
response_latency=2
sequential_access=false
size=65536
system=system
tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=false
cpu_side=system.cpu.dcache_port
mem_side=system.tol2bus.slave[1]
[system.cpu.dcache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.dcache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.dcache.replacement_policy
sequential_access=false
size=65536
tag_latency=2
warmup_percentage=0
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.dtb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
port=system.tol2bus.slave[3]
[system.cpu.icache]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=true
max_miss_count=0
mshrs=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.cpu.icache.replacement_policy
response_latency=2
sequential_access=false
size=32768
system=system
tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
warmup_percentage=0
write_buffers=8
writeback_clean=true
cpu_side=system.cpu.icache_port
mem_side=system.tol2bus.slave[0]
[system.cpu.icache.replacement_policy]
type=LRURP
eventq_index=0
[system.cpu.icache.tags]
type=BaseSetAssoc
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=2
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.cpu.icache.replacement_policy
sequential_access=false
size=32768
tag_latency=2
warmup_percentage=0
[system.cpu.interrupts]
type=ArmInterrupts
eventq_index=0
[system.cpu.isa]
type=ArmISA
decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
id_aa64afr1_el1=0
id_aa64dfr0_el1=1052678
id_aa64dfr1_el1=0
id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
id_isar3=17899825
id_isar4=268501314
id_isar5=0
id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
impdef_nop=false
midr=1091551472
pmu=Null
system=system
vecRegRenameMode=Full
[system.cpu.istage2_mmu]
type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=true
size=32
sys=system
walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
[system.cpu.itb]
type=ArmTLB
children=walker
eventq_index=0
is_stage2=false
size=64
sys=system
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
sys=system
port=system.tol2bus.slave[2]
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=../../DRAMSys/gem5/gem5_se/hello-ARM/hello
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=../../DRAMSys/gem5/gem5_se/hello-ARM/hello
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain
[system.cpu_voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.external_memory]
type=ExternalSlave
addr_ranges=0:536870911:0:0:0:0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_data=transactor
port_type=tlm_slave
power_model=
port=system.membus.master[0]
[system.l2]
type=Cache
children=replacement_policy tags
addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
is_read_only=false
max_miss_count=0
mshrs=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
prefetch_on_access=false
prefetcher=Null
replacement_policy=system.l2.replacement_policy
response_latency=20
sequential_access=false
size=2097152
system=system
tag_latency=20
tags=system.l2.tags
tgts_per_mshr=12
warmup_percentage=0
write_buffers=8
writeback_clean=false
cpu_side=system.tol2bus.master[0]
mem_side=system.membus.slave[1]
[system.l2.replacement_policy]
type=LRURP
eventq_index=0
[system.l2.tags]
type=BaseSetAssoc
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
data_latency=20
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
replacement_policy=system.l2.replacement_policy
sequential_access=false
size=2097152
tag_latency=20
warmup_percentage=0
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
point_of_unification=true
power_model=
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.external_memory.port
slave=system.system_port system.l2.mem_side
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
range=0:134217727:0:0:0:0
[system.tol2bus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=false
point_of_unification=true
power_model=
response_latency=1
snoop_filter=system.tol2bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.l2.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.tol2bus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=0
max_capacity=8388608
system=system
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

BIN
configs/gem5/gem5_se/hello-ARM/hello
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282
configs/gem5/gem5_se/hello-X86/config.ini
View File

@@ -1,282 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain cpu_voltage_domain dvfs_handler external_memory membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=false
kernel_extras=
kvm_vm=Null
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=timing
mem_ranges=0:536870911:0:0:0:0
memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
readfile=
symbolfile=
thermal_components=
thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=TimingSimpleCPU
children=apic_clk_domain dtb interrupts isa itb tracer workload
branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_gating_on_idle=false
power_model=
profile=0
progress_interval=0
pwr_gating_latency=300
simpoint_start_insts=
socket_id=0
switched_out=false
syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
wait_for_remote_gdb=false
workload=system.cpu.workload
dcache_port=system.membus.slave[2]
icache_port=system.membus.slave[1]
[system.cpu.apic_clk_domain]
type=DerivedClockDomain
clk_divider=16
clk_domain=system.cpu_clk_domain
eventq_index=0
[system.cpu.dtb]
type=X86TLB
children=walker
eventq_index=0
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
num_squash_per_cycle=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
system=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=X86LocalApic
clk_domain=system.cpu.apic_clk_domain
default_p_state=UNDEFINED
eventq_index=0
int_latency=1000
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
pio_addr=2305843009213693952
pio_latency=100000
power_model=
system=system
int_master=system.membus.slave[5]
int_slave=system.membus.master[1]
pio=system.membus.master[0]
[system.cpu.isa]
type=X86ISA
eventq_index=0
[system.cpu.itb]
type=X86TLB
children=walker
eventq_index=0
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
clk_domain=system.cpu_clk_domain
default_p_state=UNDEFINED
eventq_index=0
num_squash_per_cycle=4
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
system=system
port=system.membus.slave[3]
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=Process
cmd=../../DRAMSys/gem5/gem5_se/hello-X86/hello
cwd=
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=../../DRAMSys/gem5/gem5_se/hello-X86/hello
gid=100
input=cin
kvmInSE=false
maxStackSize=67108864
output=cout
pgid=100
pid=100
ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.cpu_voltage_domain
[system.cpu_voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.external_memory]
type=ExternalSlave
addr_ranges=0:536870911:0:0:0:0
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
port_data=transactor
port_type=tlm_slave
power_model=
port=system.membus.master[2]
[system.membus]
type=CoherentXBar
children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
point_of_coherency=true
point_of_unification=true
power_model=
response_latency=2
snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
width=16
master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.external_memory.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
lookup_latency=1
max_capacity=8388608
system=system
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
kvm_map=true
latency=30000
latency_var=0
null=false
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=
range=0:134217727:0:0:0:0
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.0

BIN
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70
src/gem5/CMakeLists.txt
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@@ -1,70 +0,0 @@
# Copyright (c) 2020, Technische Universität Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors:
# Lukas Steiner
cmake_minimum_required(VERSION 3.10)
set(GEM5_VARIANT opt) # opt, fast
set(GEM5_ISA ARM) # ARM, X86
# Configuration:
set(CMAKE_CXX_STANDARD 17 CACHE STRING "C++ Version")
set(DCMAKE_SH="CMAKE_SH-NOTFOUND")
find_library(GEM5_LIBRARY gem5_${GEM5_VARIANT} PATHS $ENV{GEM5}/build/${GEM5_ISA}/)
add_executable(DRAMSys_gem5
main.cpp
$ENV{GEM5}/util/systemc/gem5_within_systemc/sc_logger.cc
$ENV{GEM5}/util/systemc/gem5_within_systemc/sc_module.cc
$ENV{GEM5}/util/systemc/gem5_within_systemc/stats.cc
$ENV{GEM5}/util/tlm/src/sc_master_port.cc
$ENV{GEM5}/util/tlm/src/sc_slave_port.cc
$ENV{GEM5}/util/tlm/src/slave_transactor.cc
$ENV{GEM5}/util/tlm/src/sc_ext.cc
$ENV{GEM5}/util/tlm/src/sc_mm.cc
$ENV{GEM5}/util/tlm/src/sim_control.cc
)
target_include_directories(DRAMSys_gem5
PRIVATE $ENV{GEM5}/build/${GEM5_ISA}/
PRIVATE $ENV{GEM5}/util/tlm/examples/slave_port/
PRIVATE $ENV{GEM5}/util/tlm/examples/common/
PRIVATE $ENV{GEM5}/util/tlm/src/
PRIVATE $ENV{GEM5}/util/systemc/gem5_within_systemc/
PRIVATE ../library/src/
)
target_link_libraries(DRAMSys_gem5
PRIVATE DRAMSysLibrary
PRIVATE ${GEM5_LIBRARY}
)

60
src/gem5/README.md
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@@ -1,60 +0,0 @@
> **Warning**
> It is recommended to use the official integration of DRAMSys in gem5 instead.
## DRAMSys with gem5 SE Mode
Install gem5 by following the instructions in the [gem5 documentation](https://www.gem5.org/documentation/general_docs/building). In order to allow a coupling without running into problems we recommend using the **develop** branch. Optionally, use the scripts from [gem5.TnT](https://github.com/tukl-msd/gem5.TnT) to install gem5, build it, get some benchmark programs and learn more about gem5.
In order to understand the SystemC coupling with gem5 it is recommended to read the documentation in the gem5 repository *util/tlm/README* and [1].
First, select your gem5 variant and gem5 ISA in *DRAMSys/gem5/CMakeLists.txt*. Afterwards, follow the steps to build the gem5 executable and shared library.
```bash
$ cd gem5
$ scons build/<ARM/X86>/gem5.opt
$ scons --with-cxx-config --without-python --without-tcmalloc USE_SYSTEMC=False build/<ARM/X86>/libgem5_opt.so
```
In order to use gem5 with DRAMSys export the root directory as `GEM5` environment variable. Run CMake with the additional variable `-DDRAMSYS_WITH_GEM5=ON` and Make.
```bash
$ export GEM5=/path/to/gem5
$ cd DRAMSys/build
$ cmake ../DRAMSys/ -DDRAMSYS_WITH_GEM5=ON
$ make
```
Adjust the *path/to/gem5/configs/example/se.py* as shown below:
```bash
...
if options.tlm_memory:
system.physmem = SimpleMemory()
MemConfig.config_mem(options, system)
...
```
Next, a gem5 configuration file has to be generated. A "Hello world!" example is provided in the gem5 repository. To run the example execute the following commands:
```bash
$ cd DRAMSys/build/gem5
$ ./path/to/gem5/build/<ARM/X86>/gem5.opt path/to/gem5/configs/example/se.py \
-c path/to/gem5/tests/test-progs/hello/bin/<arm/x86>/linux/hello \
--mem-size=512MB --mem-channels=1 --caches --l2cache --mem-type=SimpleMemory \
--cpu-type=TimingSimpleCPU --num-cpu=1 \
--tlm-memory=transactor
```
The error message `fatal: Can't find port handler type 'tlm_slave'` is printed because a TLM memory is not yet connected to gem5. However, a configuration file that corresponds to the simulation will already be created inside the *m5out* directory. This configuration file can now be used to run the same simulation with gem5 coupled to DRAMSys:
```bash
$ ./DRAMSys_gem5 ../../DRAMSys/library/resources/simulations/ddr3-gem5-se.json m5out/config.ini 1
```
`Hello world!` should be printed to the standard output.
## References
[1] System Simulation with gem5 and SystemC: The Keystone for Full Interoperability
C. Menard, M. Jung, J. Castrillon, N. Wehn. IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2017, Samos Island, Greece.

234
src/gem5/main.cpp
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@@ -1,234 +0,0 @@
/*
* Copyright (c) 2015, Technische Universität Kaiserslautern
* Copyright (c) 2016, Dresden University of Technology (TU Dresden)
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Matthias Jung
* Christian Menard
* Abdul Mutaal Ahmad
*/
#include <iostream>
#include <string>
#include <cstdlib>
#include <systemc>
#include <tlm>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>
#include "report_handler.hh"
#include "sc_target.hh"
#include "sim_control.hh"
#include "slave_transactor.hh"
#include "stats.hh"
#include "Configuration.h"
#include "simulation/DRAMSys.h"
#include "simulation/DRAMSysRecordable.h"
using namespace sc_core;
using namespace tlm;
class Gem5SimControlDRAMsys : public Gem5SystemC::Gem5SimControl
{
public:
Gem5SimControlDRAMsys(std::string configFile) :
Gem5SystemC::Gem5SimControl("gem5", configFile, 0, "MemoryAccess")
{}
virtual void afterSimulate() override
{
sc_stop();
}
};
class AddressOffset : sc_module
{
private:
unsigned long long int offset;
public:
tlm_utils::simple_target_socket<AddressOffset> t_socket;
tlm_utils::simple_initiator_socket<AddressOffset> i_socket;
AddressOffset(sc_module_name, unsigned long long int o) : offset(o),
t_socket("t_socket"), i_socket("i_socket")
{
t_socket.register_nb_transport_fw(this, &AddressOffset::nb_transport_fw);
t_socket.register_transport_dbg(this, &AddressOffset::transport_dbg);
t_socket.register_b_transport(this, &AddressOffset::b_transport);
i_socket.register_nb_transport_bw(this, &AddressOffset::nb_transport_bw);
}
//Forward Interface
tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase,
sc_time &delay)
{
//std::cout << "NB "<< this->name() <<": " << trans.get_address() << " -" << offset;
trans.set_address(trans.get_address() - offset);
//std::cout << " = " << trans.get_address() << std::endl;
return i_socket->nb_transport_fw(trans, phase, delay);
}
unsigned int transport_dbg(tlm_generic_payload &trans)
{
// adjust address offset:
//std::cout << "Debug "<< this->name() <<": " << trans.get_address() << " -" << offset;
trans.set_address(trans.get_address() - offset);
//std::cout << " = " << trans.get_address() << std::endl;
return i_socket->transport_dbg(trans);
}
void b_transport(tlm_generic_payload &trans, sc_time &delay)
{
// adjust address offset:
//std::cout << "B "<< this->name() <<": " << trans.get_address() << " -" << offset;
trans.set_address(trans.get_address() - offset);
//std::cout << " = " << trans.get_address() << std::endl;
i_socket->b_transport(trans, delay);
}
//Backward Interface
tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase,
sc_time &delay)
{
//trans.set_address(trans.get_address()+offset);
return t_socket->nb_transport_bw(trans, phase, delay);
}
};
std::string pathOfFile(std::string file)
{
return file.substr(0, file.find_last_of('/'));
}
int sc_main(int argc, char **argv)
{
SC_REPORT_INFO("sc_main", "Simulation Setup");
std::string simulationJson;
std::string gem5ConfigFile;
std::string resources;
unsigned int numTransactors;
std::vector<std::unique_ptr<Gem5SystemC::Gem5SlaveTransactor>> transactors;
if (argc == 4)
{
// Get path of resources:
resources = pathOfFile(argv[0])
+ std::string("/../../DRAMSys/library/resources/");
simulationJson = argv[1];
gem5ConfigFile = argv[2];
numTransactors = static_cast<unsigned>(std::stoul(argv[3]));
}
else
{
SC_REPORT_FATAL("sc_main", "Please provide configuration files and number of ports");
return EXIT_FAILURE;
}
DRAMSysConfiguration::Configuration configLib = DRAMSysConfiguration::from_path(simulationJson, resources);
// Instantiate DRAMSys:
std::unique_ptr<DRAMSys> dramSys;
if (configLib.simConfig.databaseRecording.value_or(false))
dramSys = std::make_unique<DRAMSysRecordable>("DRAMSys", configLib);
else
dramSys = std::make_unique<DRAMSys>("DRAMSys", configLib);
// Instantiate gem5:
Gem5SimControlDRAMsys sim_control(gem5ConfigFile);
// XXX: this code assumes:
// - for a single port the port name is "transactor"
// - for multiple ports names are transactor1, transactor2, ..., transactorN
// Names generated here must match port names used by the gem5 config file, e.g., config.ini
if (numTransactors == 1)
{
transactors.emplace_back(std::make_unique<Gem5SystemC::Gem5SlaveTransactor>("transactor", "transactor"));
transactors.back().get()->socket.bind(dramSys->tSocket);
transactors.back().get()->sim_control.bind(sim_control);
}
else
{
for (unsigned i = 0; i < numTransactors; i++)
{
// If there are two or more ports
unsigned index = i + 1;
std::string name = "transactor" + std::to_string(index);
std::string portName = "transactor" + std::to_string(index);
transactors.emplace_back(std::make_unique<Gem5SystemC::Gem5SlaveTransactor>(name.c_str(), portName.c_str()));
transactors.back().get()->socket.bind(dramSys->tSocket);
transactors.back().get()->sim_control.bind(sim_control);
}
}
#ifdef CHOICE3
// If for example two gem5 ports are used (NVM and DRAM) with
// crazy address offsets:
Gem5SystemC::Gem5SlaveTransactor dramInterface("transactor1", "transactor1");
Gem5SystemC::Gem5SlaveTransactor nvmInterface("transactor2", "transactor2");
AddressOffset nvmOffset("nvmOffset", 0);
AddressOffset dramOffset("dramOffset", (2147483648 - 67108863)); //+67108863);
dramInterface.socket.bind(dramOffset.t_socket);
dramOffset.i_socket.bind(dramSys->tSocket); // ID0
nvmInterface.socket.bind(nvmOffset.t_socket);
nvmOffset.i_socket.bind(dramSys->tSocket);
dramInterface.sim_control.bind(sim_control);
nvmInterface.sim_control.bind(sim_control);
#endif
SC_REPORT_INFO("sc_main", "Start of Simulation");
sc_core::sc_set_stop_mode(SC_STOP_FINISH_DELTA);
sc_core::sc_start();
if (!sc_core::sc_end_of_simulation_invoked())
{
SC_REPORT_INFO("sc_main", "Simulation stopped without explicit sc_stop()");
sc_core::sc_stop();
}
//for (auto t : transactors)
// delete t;
SC_REPORT_INFO("sc_main", "End of Simulation");
return EXIT_SUCCESS;
}

35
tests/tests_regression/dramsys-gem5/ci.yml
View File

@@ -1,35 +0,0 @@
# vim: set ts=4 sw=4 expandtab:
dramsys-gem5-build:
stage: dramsys-gem5-build
script:
- git submodule sync
- git submodule update --init --recursive
- cd DRAMSys/tests/dramsys-gem5
- git clone https://github.com/tukl-msd/gem5.TnT.git
- cd gem5.TnT
- ./get_essential_repos.sh
- ./build_gem5.sh
- export GEM5=${HOME}/gem5_tnt/gem5
- export LD_LIBRARY_PATH=${LD_LIBRARY_PATH}:${GEM5}/build/ARM
- cd ../../../..
- rm -rf build-dramsys-gem5
- mkdir -p build-dramsys-gem5
- cd build-dramsys-gem5
- qmake ../DRAMSys/DRAMSys.pro
- make -j$(cat /proc/cpuinfo | grep processor | wc -l) > build.log 2>&1
cache:
key: build
paths:
- build-dramsys-gem5/
- DRAMSys/tests/dramsys-gem5/gem5.TnT
policy: push
# TODO: "allow_failure" should be removed as soon the server has
# dependencies properly installed
allow_failure: true
artifacts:
paths:
- build-dramsys-gem5/build.log
expire_in: 2 days