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DRAMSys
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581794b970978883eef432383144296fed82b07b
DRAMSys
/
tests
/
tests_regression
History
Derek Christ
581794b970
Allow responses to be sent back-to-back
2025-01-24 14:58:06 +01:00
..
DDR3
Have a one cycle END_RESP delay in the standard initiator
2025-01-24 14:43:06 +01:00
DDR4
Have a one cycle END_RESP delay in the standard initiator
2025-01-24 14:43:06 +01:00
DDR5
Have a one cycle END_RESP delay in the standard initiator
2025-01-24 14:43:06 +01:00
HBM2
Have a one cycle END_RESP delay in the standard initiator
2025-01-24 14:43:06 +01:00
HBM3
Allow responses to be sent back-to-back
2025-01-24 14:58:06 +01:00
LPDDR4
Have a one cycle END_RESP delay in the standard initiator
2025-01-24 14:43:06 +01:00
LPDDR5
Have a one cycle END_RESP delay in the standard initiator
2025-01-24 14:43:06 +01:00
CMakeLists.txt
Remove unnecessary project() calls
2024-12-20 17:40:15 +01:00
