1225f6b044
Fix tests after ThinkDelayFw
2025-01-24 14:19:53 +01:00
a82efdbb3a
Fix HBM3 regression test
2025-01-13 10:24:09 +01:00
aba5ba6e2e
Switch to Open page policy for HBM3 regression test
2025-01-10 16:42:42 +01:00
83cc41e318
Minor refactorings of CMakeList files
2025-01-09 08:12:49 +00:00
e2342350d0
Minor improvements on package handling
2024-12-20 17:40:15 +01:00
c3eb5e6a62
Hide the use of FetchContent behind a flag
...
FetchContent is now disabled by default, when the project is included as
an subproject by another top-level project.
Also, every usage of FetchContent is behind a separate flag to enable and
disable the usage with granular control.
2024-12-20 17:40:15 +01:00
ca9ef16d0d
Remove unnecessary project() calls
...
project() should only be called if the subdirectory, in fact, can be
built standalone.
2024-12-20 17:40:15 +01:00
e1b8bbf12d
Clean up and refactor CMakeLists
2024-12-20 17:40:15 +01:00
a37171c6fd
Remove file globs from CMakeLists
...
Fix build
2024-12-20 17:40:15 +01:00
Lukas Steiner
5825eb8c58
Merge branch 'feat/simulation_time' into 'develop'
...
Introduce SimulationTime config
Closes #62
See merge request ems/astdm/modeling.dram/dram.sys.5!91
2024-12-17 14:52:22 +00:00
ecf9127faa
Fix some tests and refactor simulation script
2024-12-11 12:56:56 +01:00
703ee81d7e
Introduce SimulationTime config
...
Use SimulationTime to forcefully stop simulation at a specified point in
time.
2024-12-10 10:04:59 +01:00
5dd7c22a74
Refactor CMakeLists and GitLab CI/CD pipeline
...
- Remove nested minimum required to supress warnings.
- Declare SystemC as system library to supress warnings in headers.
- Add a BUILD_SHARED_LIBS option
- Remove hardcoded STATIC in various add_library calls to honor the
BUILD_SHARED_LIBS option
- Remove _deps/ directory from the build directory in GitLab pipeline
- Remove *.tdb files after test stage in pipeline
- Set Ninja as the default generator for the dev preset and re-enable
colored diagnostics
2024-06-28 11:07:56 +02:00
12bfba1fb3
Fix various bugs
...
- Fix data race for some tests by disabling database recording
- Fix undefined behaviour in configuration test
- Port clkMhz to tCK for simulation script
- Port memUtil Python script to tCK with backwards compatibility
2024-02-26 09:58:19 +01:00
Lukas Steiner
5b4ed9559d
Merge branch 'config_refactor' into 'develop'
...
Configuration Refactoring
See merge request ems/astdm/modeling.dram/dram.sys.5!63
2024-02-23 14:29:06 +00:00
539a525f3d
Fix DDR3 regression
...
Using the new tCK entry in the memspecs, there was a small power deviation in the database
2024-02-23 12:04:29 +01:00
0ec6ea79ad
Migrate from clkMhz to tCK entry in memspecs
2024-02-23 12:04:22 +01:00
59cf73fe9c
Clean up public API (DRAMSys.h)
...
Remove DRAMSysRecordable.h/cpp as the functionality has been incorporated into
DRAMSys.h/cpp. The databaseRecording config is now completely handled by
DRAMSys itself without needing the user of the library to instanciate DRAMSys
or DRAMSysRecordable depending on this config.
2024-02-23 11:54:51 +01:00
5391b4351d
Fix configuration tests
2024-02-23 11:54:51 +01:00
454cb00ddb
Refactor: remove monolithic configuration class
2024-02-23 11:54:51 +01:00
1ba63bd1f7
Add support for more than two XOR bits
2023-12-13 10:32:03 +01:00
ed2a675145
Extract plausability check from AddressDecoder to separate function
2023-12-11 10:32:39 +01:00
74a9155993
Add RequestBufferSizeRead and RequestBufferSizeWrite configurations for ReadWrite Buffer
2023-11-14 11:00:28 +01:00
Lukas Steiner
8224e97abe
Reformat all files.
2023-09-21 16:50:59 +02:00
a539e3c011
Merge branch 'develop' into work/partial_writes
2023-08-23 09:31:42 +02:00
a0f93a75e2
Merge develop
2023-08-21 10:01:08 +02:00
b30df49d67
Use tCCDMW for masked write in LPDDR4
2023-08-21 09:26:05 +02:00
c5f1320399
Implement Partial Write for DDR5
2023-08-16 09:38:57 +02:00
a4342f7104
Update expected traces for DDR5 and HBM3
2023-08-15 11:28:03 +02:00
a18bbc7465
Add the resource directory option to the json converter
2023-08-15 10:58:11 +02:00
c352ca4372
Remove compare.sh scripts and invoke sqldiff directly from CMake
2023-08-15 10:58:10 +02:00
b988544be2
Enable PerBank refresh in HBM2,HBM3 regression test
2023-08-15 10:58:10 +02:00
0fc74e93c4
Add LPDDR5 regression test
2023-08-15 10:58:10 +02:00
81eaccf3d6
Add lastCommandOn{C,R}asBus != scMaxTime check for HBM2 and HBM3
2023-08-15 10:58:10 +02:00
e3bd773cac
Implement isFullCycle, alignAtNext functions in utils and add tests
2023-08-15 10:58:10 +02:00
599761c341
Add regression test for DDR5
2023-08-15 10:58:10 +02:00
42d1caa372
Add HBM3 regression test
2023-08-15 10:58:10 +02:00
14ecc64ed0
Introduce Simulator class
2023-07-14 14:31:03 +02:00
a9759f51fa
Enable warnings in dev preset and fix them
2023-06-09 11:29:15 +02:00
Lukas Steiner
20f6aae787
Replace tabs with whitespaces.
2023-05-25 16:09:55 +02:00
Lukas Steiner
b3955d6d02
Update TUK to RPTU.
2023-05-25 15:15:52 +02:00
Lukas Steiner
93aecc3555
Merge branch 'gem5_instructions' into 'develop'
...
Add instructions for the new gem5 integration
See merge request ems/astdm/modeling.dram/dram.sys.5!23
2023-05-23 13:12:07 +00:00
Lukas Steiner
e389474139
Remove deprecated gem5 files.
2023-05-23 14:53:06 +02:00
69cd04c448
Namespace the complete DRAMSys library
2023-05-17 11:42:00 +02:00
e040e087a2
Fix sporadic CI/CD failures due to race condition
...
When running tests in parallel, there was a case where two tests
accessed the same generated resource. This is resolved by moving
all regression tests into their own subdirectory.
2023-04-26 15:25:05 +02:00
fa88b34052
Refactor deserilization of RefreshPolicyType and remove McConfig.cpp
2023-04-24 09:34:50 +02:00
85f944fe58
Rename RAACDR to RAADEC
2023-04-21 11:10:09 +02:00
aa07f071aa
Update AddressDecoderTest
2023-04-13 11:34:27 +02:00
3d4f73361f
Fix timings in new StlPlayer
2023-04-13 11:21:36 +02:00
a49afa40eb
Use key "addressmapping" instead of "CONGEN" in addressmapping configs
2023-04-13 11:21:36 +02:00
