Migrate from clkMhz to tCK entry in memspecs

2023-12-18 10:50:32 +01:00
parent 5eabecc9f9
commit 0ec6ea79ad
178 changed files with 188 additions and 194 deletions
--- a/tests/tests_dramsys/b_transport/configs/no_storage.json
+++ b/tests/tests_dramsys/b_transport/configs/no_storage.json
@@ -129,7 +129,7 @@
                "XPDLL": 255,
                "XS": 252,
                "XSDLL": 512,
-                "clkMhz": 933
+                "tCK": 1072
            }
        },
        "simconfig": {
@@ -150,4 +150,4 @@
        },
        "simulationid": "ddr4-example"
    }
-}
+}
--- a/tests/tests_dramsys/b_transport/configs/storage.json
+++ b/tests/tests_dramsys/b_transport/configs/storage.json
@@ -127,7 +127,7 @@
                "XPDLL": 255,
                "XS": 252,
                "XSDLL": 512,
-                "clkMhz": 933
+                "tCK": 1072
            }
        },
        "simconfig": {
@@ -148,4 +148,4 @@
        },
        "simulationid": "ddr4-example"
    }
-}
+}
--- a/tests/tests_regression/DDR3/ddr3-example.json
+++ b/tests/tests_regression/DDR3/ddr3-example.json
@@ -111,7 +111,7 @@
                "PRPDEN": 1,
                "REFPDEN": 1,
                "RTRS": 1,
-                "clkMhz": 533
+                "tCK": 1876
            }
        },
        "simconfig": {
--- a/tests/tests_regression/DDR4/ddr4-example.json
+++ b/tests/tests_regression/DDR4/ddr4-example.json
@@ -122,7 +122,7 @@
                "PRPDEN": 1,
                "REFPDEN": 1,
                "RTRS": 1,
-                "clkMhz": 933
+                "tCK": 1072
            }
        },
        "simconfig": {
--- a/tests/tests_regression/DDR5/ddr5-example.json
+++ b/tests/tests_regression/DDR5/ddr5-example.json
@@ -138,7 +138,7 @@
                "WTR_M": 16,
                "WTR_S": 4,
                "XP": 12,
-                "clkMhz": 1600
+                "tCK": 625
            }
        },
        "simconfig": {
@@ -162,4 +162,4 @@
            }
        ]
    }
-}
+}
--- a/tests/tests_regression/HBM2/hbm2-example.json
+++ b/tests/tests_regression/HBM2/hbm2-example.json
@@ -100,7 +100,7 @@
                "WTRS": 4,
                "XP": 8,
                "XS": 216,
-                "clkMhz": 1000
+                "tCK": 1000
            }
        },
        "simconfig": {
--- a/tests/tests_regression/HBM3/hbm3-example.json
+++ b/tests/tests_regression/HBM3/hbm3-example.json
@@ -103,7 +103,7 @@
                "WTRS": 4,
                "XP": 8,
                "XS": 260,
-                "clkMhz": 1600
+                "tCK": 625
            }
        },
        "simconfig": {
--- a/tests/tests_regression/LPDDR4/lpddr4-example.json
+++ b/tests/tests_regression/LPDDR4/lpddr4-example.json
@@ -99,7 +99,7 @@
                "XP": 12,
                "XSR": 460,
                "RTRS": 1,
-                "clkMhz": 1600
+                "tCK": 625
            }
        },
        "simconfig": {
--- a/tests/tests_regression/LPDDR5/lpddr5-example.json
+++ b/tests/tests_regression/LPDDR5/lpddr5-example.json
@@ -112,9 +112,9 @@
                "WR": 28,
                "WTR_L": 10,
                "WTR_S": 5,
-                "clkMhz": 800,
                "pbR2act": 6,
-                "pbR2pbR": 72
+                "pbR2pbR": 72,
+                "tCK": 800
            }
        },
        "simconfig": {
@@ -138,4 +138,4 @@
            }
        ]
    }
-}
+}