Merge develop

2023-08-21 10:01:08 +02:00
parent 1208d3e799 a8d15e35a5
commit a0f93a75e2
117 changed files with 3036 additions and 2858 deletions
--- a/tests/tests_configuration/jsonconverter.cpp
+++ b/tests/tests_configuration/jsonconverter.cpp
@@ -41,14 +41,18 @@

 int main(int argc, char **argv)
 {
-    if (argc != 2)
+    if (argc < 2)
    {
        std::cerr << "Must specify a simulation json as single argument.\n";
        return -1;
    }

    std::string pathToJson = argv[1];
-    auto configuration = DRAMSys::Config::from_path(pathToJson);
+    std::string resourceDirectory = argc <= 2 ? DRAMSYS_RESOURCE_DIR : argv[2];
+
+    auto configuration = DRAMSys::Config::from_path(pathToJson, resourceDirectory);
+
+
    nlohmann::json json;
    json["simulation"] = configuration;

--- a/tests/tests_configuration/simpletest.cpp
+++ b/tests/tests_configuration/simpletest.cpp
@@ -1,216 +0,0 @@
-/*
- * Copyright (c) 2021, RPTU Kaiserslautern-Landau
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its
- *    contributors may be used to endorse or promote products derived from
- *    this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
- * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors:
- *    Derek Christ
- */
-
-#include <DRAMSys/config/DRAMSysConfiguration.h>
-
-#include <DRAMSys/util/json.h>
-
-#include <fstream>
-#include <iostream>
-
-using namespace DRAMSys::Config;
-
-DRAMSys::Config::AddressMapping getAddressMapping()
-{
-    return DRAMSys::Config::AddressMapping{
-        {{0, 1}},
-        {{2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12}},
-        {{16}},
-        {{13, 14, 15}},
-        {{17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32}},
-        {{33}},
-        {{}},
-        {{}}
-    };
-}
-
-DRAMSys::Config::McConfig getMcConfig()
-{
-    return McConfig{
-        PagePolicy::Open,
-        Scheduler::FrFcfs,
-        0,
-        0,
-        SchedulerBuffer::Bankwise,
-        8,
-        CmdMux::Oldest,
-        RespQueue::Fifo,
-        RefreshPolicy::AllBank,
-        0,
-        0,
-        PowerDownPolicy::NoPowerDown,
-        Arbiter::Simple,
-        128,
-        {}
-    };
-}
-
-DRAMSys::Config::SimConfig getSimConfig()
-{
-    return DRAMSys::Config::SimConfig{
-        0,   false, true,     false, false, {"error.csv"},
-        42,  false, {"ddr5"}, true,  DRAMSys::Config::StoreMode::NoStorage,        false, false,
-        1000};
-}
-
-DRAMSys::Config::TracePlayer getTracePlayer()
-{
-    DRAMSys::Config::TracePlayer player;
-    player.clkMhz = 100;
-    player.name = "mytrace.stl";
-
-    return player;
-}
-
-DRAMSys::Config::TraceGenerator getTraceGeneratorOneState()
-{
-    DRAMSys::Config::TraceGenerator gen;
-    gen.clkMhz = 100;
-    gen.name = "MyTestGen";
-
-    DRAMSys::Config::TraceGeneratorTrafficState state0;
-    state0.numRequests = 1000;
-    state0.rwRatio = 0.5;
-    state0.addressDistribution = DRAMSys::Config::AddressDistribution::Random;
-    state0.addressIncrement = {};
-    state0.minAddress = {};
-    state0.maxAddress = {};
-    state0.clksPerRequest = {};
-
-    gen.states.emplace(0, state0);
-
-    return gen;
-}
-
-DRAMSys::Config::TraceGenerator getTraceGeneratorMultipleStates()
-{
-    DRAMSys::Config::TraceGenerator gen;
-
-    gen.clkMhz = 100;
-    gen.name = "MyTestGen";
-    gen.maxPendingReadRequests = 8;
-
-    DRAMSys::Config::TraceGeneratorTrafficState state0;
-    state0.numRequests = 1000;
-    state0.rwRatio = 0.5;
-    state0.addressDistribution = DRAMSys::Config::AddressDistribution::Sequential;
-    state0.addressIncrement = 256;
-    state0.minAddress = {};
-    state0.maxAddress = 1024;
-    state0.clksPerRequest = {};
-
-    DRAMSys::Config::TraceGeneratorTrafficState state1;
-    state1.numRequests = 100;
-    state1.rwRatio = 0.75;
-    state1.addressDistribution = DRAMSys::Config::AddressDistribution::Sequential;
-    state1.addressIncrement = 512;
-    state1.minAddress = 1024;
-    state1.maxAddress = 2048;
-    state1.clksPerRequest = {};
-
-    gen.states.emplace(0, state0);
-    gen.states.emplace(1, state1);
-
-    DRAMSys::Config::TraceGeneratorStateTransition transistion0{1, 1.0};
-
-    gen.transitions.emplace(0, transistion0);
-
-    return gen;
-}
-
-DRAMSys::Config::TraceHammer getTraceHammer()
-{
-    DRAMSys::Config::TraceHammer hammer;
-
-    hammer.clkMhz = 100;
-    hammer.name = "MyTestHammer";
-    hammer.numRequests = 4000;
-    hammer.rowIncrement = 2097152;
-
-    return hammer;
-}
-
-DRAMSys::Config::TraceSetup getTraceSetup()
-{
-    using namespace DRAMSys::Config;
-
-    std::vector<std::variant<TracePlayer, TraceGenerator, TraceHammer>> initiators;
-    initiators.emplace_back(getTracePlayer());
-    initiators.emplace_back(getTraceGeneratorOneState());
-    initiators.emplace_back(getTraceGeneratorMultipleStates());
-    initiators.emplace_back(getTraceHammer());
-
-    return DRAMSys::Config::TraceSetup{initiators};
-}
-
-DRAMSys::Config::Configuration getConfig(const DRAMSys::Config::MemSpec &memSpec)
-{
-    return DRAMSys::Config::Configuration{
-        getAddressMapping(),
-        getMcConfig(),
-        memSpec,
-        getSimConfig(),
-        "std::string_simulationId",
-        // {{}, false}, works too
-        getTraceSetup(),
-    };
-}
-
-int main()
-{
-    DRAMSys::Config::Configuration conf = DRAMSys::Config::from_path("ddr5.json");
-    std::ofstream fileout("myjson.json");
-    json_t j_my;
-    j_my["simulation"] = getConfig(conf.memSpec); // just copy memspec over
-    fileout << j_my.dump(4);
-
-    std::ifstream file2("hbm2.json");
-    json_t hbm2_j = json_t::parse(file2, nullptr, false);
-    json_t hbm2_config = hbm2_j.at("simulation");
-    DRAMSys::Config::Configuration hbm2conf = hbm2_config.get<DRAMSys::Config::Configuration>();
-    std::ofstream filehbm2("myhbm2.json");
-    json_t j_myhbm2;
-    j_myhbm2["simulation"] = hbm2conf;
-    filehbm2 << j_myhbm2.dump(4);
-
-    std::ifstream file3("myjson.json");
-    json_t ddr5_old = json_t::parse(file3, nullptr, false);
-    json_t ddr5_old_conf = ddr5_old.at("simulation");
-    DRAMSys::Config::Configuration ddr5_old_config = ddr5_old_conf.get<DRAMSys::Config::Configuration>();
-    std::ofstream fileoldout("myjson2.json");
-    json_t j_oldconfconv;
-    j_oldconfconv["simulation"] = ddr5_old_config;
-    fileoldout << j_oldconfconv.dump(4);
-}
--- a/tests/tests_configuration/test_configuration.cpp
+++ b/tests/tests_configuration/test_configuration.cpp
@@ -118,7 +118,7 @@ protected:
    DRAMSys::Config::TrafficGenerator traceGeneratorOneState;
    DRAMSys::Config::TrafficGeneratorStateMachine traceGeneratorMultipleStates;
    DRAMSys::Config::RowHammer traceHammer;
-    DRAMSys::Config::TraceSetup traceSetup{{tracePlayer, traceGeneratorOneState, traceGeneratorMultipleStates, traceHammer}};
+    std::vector<DRAMSys::Config::Initiator> traceSetup{{tracePlayer, traceGeneratorOneState, traceGeneratorMultipleStates, traceHammer}};

    DRAMSys::Config::Configuration configuration{
        addressMapping,
@@ -310,7 +310,7 @@ TEST(RefreshPolicyType, BackwardsCompatibility)
 TEST_F(ConfigurationTest, SimConfig)
 {
    std::string_view simconfig_string = R"(
-        {        
+        {
            "simconfig": {
                    "AddressOffset": 0,
                    "CheckTLM2Protocol": false,
--- a/tests/tests_dramsys/test_utils.cpp
+++ b/tests/tests_dramsys/test_utils.cpp
@@ -0,0 +1,42 @@
+#include <gtest/gtest.h>
+
+#include <DRAMSys/common/utils.h>
+
+using sc_core::sc_time;
+using sc_core::SC_NS;
+using sc_core::SC_US;
+
+TEST(AlignAtNext, FullCycle)
+{
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(5, SC_NS), sc_time(1, SC_NS)), sc_time(5, SC_NS));
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(10, SC_NS), sc_time(2, SC_NS)), sc_time(10, SC_NS));
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(10, SC_NS), sc_time(10, SC_NS)), sc_time(10, SC_NS));
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(100, SC_NS), sc_time(10, SC_NS)), sc_time(100, SC_NS));
+}
+
+TEST(AlignAtNext, HalfCycle)
+{
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(0.5, SC_NS), sc_time(1, SC_NS)), sc_time(1, SC_NS));
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(5, SC_NS), sc_time(10, SC_NS)), sc_time(10, SC_NS));
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(22.5, SC_NS), sc_time(5, SC_NS)), sc_time(25, SC_NS));
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(55, SC_NS), sc_time(5, SC_NS)), sc_time(55, SC_NS));
+}
+
+TEST(AlignAtNext, ArbitraryCycle)
+{
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(0.37, SC_NS), sc_time(1, SC_NS)), sc_time(1, SC_NS));
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(5, SC_NS), sc_time(6.67, SC_NS)), sc_time(6.67, SC_NS));
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(4.99, SC_NS), sc_time(5, SC_NS)), sc_time(5, SC_NS));
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(0, SC_NS), sc_time(7.77, SC_NS)), sc_time(0, SC_NS));
+    EXPECT_EQ(DRAMSys::alignAtNext(sc_time(4.49, SC_US), sc_time(500, SC_NS)), sc_time(4.5, SC_US));
+}
+
+TEST(IsFullCycle, IsFullCycle)
+{
+    EXPECT_TRUE(DRAMSys::isFullCycle(sc_time(0, SC_NS), sc_time(1, SC_NS)));
+    EXPECT_TRUE(DRAMSys::isFullCycle(sc_time(0, SC_NS), sc_time(1000, SC_US)));
+    EXPECT_TRUE(DRAMSys::isFullCycle(sc_time(5, SC_NS), sc_time(1, SC_NS)));
+    EXPECT_FALSE(DRAMSys::isFullCycle(sc_time(0.5, SC_NS), sc_time(1, SC_NS)));
+    EXPECT_TRUE(DRAMSys::isFullCycle(sc_time(67, SC_US), sc_time(1, SC_NS)));
+    EXPECT_FALSE(DRAMSys::isFullCycle(sc_time(67.05, SC_US), sc_time(100, SC_NS)));
+}
--- a/tests/tests_regression/CMakeLists.txt
+++ b/tests/tests_regression/CMakeLists.txt
@@ -28,7 +28,7 @@
 # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: 
+# Authors:
 #    Derek Christ

 ###############################################
@@ -39,11 +39,10 @@ cmake_minimum_required(VERSION 3.1.0)

 project(tests_regression)

-find_program(Bash bash)
 find_program(SqlDiff sqldiff)

-if(NOT Bash OR NOT SqlDiff)
-    message(WARNING "Regression tests require bash and sqldiff to be installed")
+if(NOT SqlDiff)
+    message(WARNING "Regression tests require sqldiff to be installed")
    return()
 endif()

@@ -53,45 +52,53 @@ set(TABLES_TO_COMPARE
    Power
 )

-function(test_standard standard base_config resource_dir output_filename)
-    # Put all the generated files into a subdirectory
-    file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${standard})
+function(test_standard standard test_name base_config resource_dir output_filename)
+    if(NOT IS_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/${standard})
+        message(WARNING "Cannot find regression test ${standard}")
+        return()
+    endif()

-    configure_file(compare.sh ${standard}/compare.sh)
+    # Put all the generated files into a subdirectory
+    file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${test_name})

    # Test to create database
    add_test(
-        NAME Regression${standard}.CreateDatabase
-        WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${standard}
+        NAME Regression${test_name}.CreateDatabase
+        WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${test_name}
        COMMAND $<TARGET_FILE:DRAMSys> ${base_config} ${resource_dir}
    )
-    set_tests_properties(Regression${standard}.CreateDatabase PROPERTIES FIXTURES_SETUP Regression${standard}.CreateDatabase)
+    set_tests_properties(Regression${test_name}.CreateDatabase PROPERTIES FIXTURES_SETUP Regression${test_name}.CreateDatabase)

    # Test to diff the whole database. This test should not fail.
    # The purpose of this test is solely to output the differences of the two databases
    # so that they can be inspected easily.
    add_test(
-        NAME Regression${standard}.SqlDiff
-        WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${standard}
-        COMMAND compare.sh
+        NAME Regression${test_name}.SqlDiff
+        WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${test_name}
+        COMMAND sqldiff ${CMAKE_CURRENT_SOURCE_DIR}/${standard}/expected/${output_filename} ${output_filename}
    )
-    set_tests_properties(Regression${standard}.SqlDiff PROPERTIES FIXTURES_REQUIRED Regression${standard}.CreateDatabase)
+    set_tests_properties(Regression${test_name}.SqlDiff PROPERTIES FIXTURES_REQUIRED Regression${test_name}.CreateDatabase)

    # Tests to diff individual tables
    foreach(table IN LISTS TABLES_TO_COMPARE)
-        configure_file(compare_table.sh ${standard}/compare_table-${table}.sh)
-
        add_test(
-            NAME Regression${standard}.SqlDiff.${table}
-            WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${standard}
-            COMMAND compare_table-${table}.sh
+            NAME Regression${test_name}.SqlDiff.${table}
+            WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${test_name}
+            COMMAND sqldiff --table ${table} ${CMAKE_CURRENT_SOURCE_DIR}/${standard}/expected/${output_filename} ${output_filename}
        )
-        set_tests_properties(Regression${standard}.SqlDiff.${table} PROPERTIES FIXTURES_REQUIRED Regression${standard}.CreateDatabase)
+        set_tests_properties(Regression${test_name}.SqlDiff.${table} PROPERTIES FIXTURES_REQUIRED Regression${test_name}.CreateDatabase)
+
+        # Only pass test if output is empty
+        set_tests_properties(Regression${test_name}.SqlDiff.${table} PROPERTIES PASS_REGULAR_EXPRESSION "^$")
    endforeach()
 endfunction()

-test_standard(DDR3 ${CMAKE_CURRENT_SOURCE_DIR}/DDR3/ddr3-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR3 DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb)
-test_standard(DDR4 ${CMAKE_CURRENT_SOURCE_DIR}/DDR4/ddr4-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR4 DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb)
-test_standard(LPDDR4 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4/lpddr4-example.json ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4 DRAMSys_lpddr4-example_lpddr4_ch0.tdb)
-test_standard(HBM2.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM2 DRAMSys_hbm2-example_hbm2_ch0.tdb)
-test_standard(HBM2.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM2 DRAMSys_hbm2-example_hbm2_ch1.tdb)
+test_standard(DDR3 DDR3 ${CMAKE_CURRENT_SOURCE_DIR}/DDR3/ddr3-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR3 DRAMSys_ddr3-dual-rank_ddr3_ch0.tdb)
+test_standard(DDR4 DDR4 ${CMAKE_CURRENT_SOURCE_DIR}/DDR4/ddr4-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR4 DRAMSys_ddr4-bankgrp_ddr4_ch0.tdb)
+test_standard(DDR5 DDR5.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/DDR5/ddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR5 DRAMSys_ddr5-example_ddr5_ch0.tdb)
+test_standard(DDR5 DDR5.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/DDR5/ddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/DDR5 DRAMSys_ddr5-example_ddr5_ch1.tdb)
+test_standard(LPDDR4 LPDDR4 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4/lpddr4-example.json ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR4 DRAMSys_lpddr4-example_lpddr4_ch0.tdb)
+test_standard(LPDDR5 LPDDR5 ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR5/lpddr5-example.json ${CMAKE_CURRENT_SOURCE_DIR}/LPDDR5 DRAMSys_lpddr5-example_lpddr5_ch0.tdb)
+test_standard(HBM2 HBM2.Ch0 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM2 DRAMSys_hbm2-example_hbm2_ch0.tdb)
+test_standard(HBM2 HBM2.Ch1 ${CMAKE_CURRENT_SOURCE_DIR}/HBM2/hbm2-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM2 DRAMSys_hbm2-example_hbm2_ch1.tdb)
+test_standard(HBM3 HBM3 ${CMAKE_CURRENT_SOURCE_DIR}/HBM3/hbm3-example.json ${CMAKE_CURRENT_SOURCE_DIR}/HBM3 DRAMSys_hbm3-example_hbm3_ch0.tdb)
--- a/tests/tests_regression/DDR5/ddr5-example.json
+++ b/tests/tests_regression/DDR5/ddr5-example.json
@@ -0,0 +1,165 @@
+{
+    "simulation": {
+        "addressmapping": {
+            "BANKGROUP_BIT": [
+                13,
+                14,
+                15
+            ],
+            "BANK_BIT": [
+                16
+            ],
+            "BYTE_BIT": [
+                0,
+                1
+            ],
+            "CHANNEL_BIT": [
+                33
+            ],
+            "COLUMN_BIT": [
+                2,
+                3,
+                4,
+                5,
+                6,
+                7,
+                8,
+                9,
+                10,
+                11,
+                12
+            ],
+            "ROW_BIT": [
+                17,
+                18,
+                19,
+                20,
+                21,
+                22,
+                23,
+                24,
+                25,
+                26,
+                27,
+                28,
+                29,
+                30,
+                31,
+                32
+            ]
+        },
+        "mcconfig": {
+            "Arbiter": "Simple",
+            "CmdMux": "Oldest",
+            "MaxActiveTransactions": 128,
+            "PagePolicy": "Open",
+            "PowerDownPolicy": "NoPowerDown",
+            "RefreshManagement": false,
+            "RefreshMaxPostponed": 0,
+            "RefreshMaxPulledin": 0,
+            "RefreshPolicy": "AllBank",
+            "RequestBufferSize": 8,
+            "RespQueue": "Fifo",
+            "Scheduler": "FrFcfs",
+            "SchedulerBuffer": "Bankwise"
+        },
+        "memspec": {
+            "memarchitecturespec": {
+                "RAADEC": 16,
+                "RAAIMT": 32,
+                "RAAMMT": 96,
+                "burstLength": 16,
+                "cmdMode": 1,
+                "dataRate": 2,
+                "nbrOfBankGroups": 8,
+                "nbrOfBanks": 16,
+                "nbrOfChannels": 2,
+                "nbrOfColumns": 2048,
+                "nbrOfDIMMRanks": 1,
+                "nbrOfDevices": 8,
+                "nbrOfLogicalRanks": 1,
+                "nbrOfPhysicalRanks": 1,
+                "nbrOfRanks": 1,
+                "nbrOfRows": 65536,
+                "refMode": 1,
+                "width": 4
+            },
+            "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
+            "memoryType": "DDR5",
+            "memtimingspec": {
+                "ACTPDEN": 2,
+                "CCD_L_WR2_slr": 16,
+                "CCD_L_WR_slr": 32,
+                "CCD_L_slr": 8,
+                "CCD_M_WR_slr": 32,
+                "CCD_M_slr": 8,
+                "CCD_S_WR_slr": 8,
+                "CCD_S_slr": 8,
+                "CCD_WR_dlr": 0,
+                "CCD_WR_dpr": 0,
+                "CCD_dlr": 0,
+                "CPDED": 8,
+                "FAW_dlr": 0,
+                "FAW_slr": 32,
+                "PD": 12,
+                "PPD": 2,
+                "PRPDEN": 2,
+                "RAS": 52,
+                "RCD": 22,
+                "RDDQS": 0,
+                "REFI1": 6240,
+                "REFI2": 3120,
+                "REFISB": 1560,
+                "REFPDEN": 2,
+                "REFSBRD_dlr": 0,
+                "REFSBRD_slr": 48,
+                "RFC1_dlr": 0,
+                "RFC1_dpr": 0,
+                "RFC1_slr": 312,
+                "RFC2_dlr": 0,
+                "RFC2_dpr": 0,
+                "RFC2_slr": 208,
+                "RFCsb_dlr": 0,
+                "RFCsb_slr": 184,
+                "RL": 22,
+                "RP": 22,
+                "RPRE": 1,
+                "RPST": 0,
+                "RRD_L_slr": 8,
+                "RRD_S_slr": 8,
+                "RRD_dlr": 0,
+                "RTP": 12,
+                "RTRS": 2,
+                "WL": 20,
+                "WPRE": 2,
+                "WPST": 0,
+                "WR": 48,
+                "WTR_L": 16,
+                "WTR_M": 16,
+                "WTR_S": 4,
+                "XP": 12,
+                "clkMhz": 1600
+            }
+        },
+        "simconfig": {
+            "AddressOffset": 0,
+            "CheckTLM2Protocol": false,
+            "DatabaseRecording": true,
+            "Debug": false,
+            "EnableWindowing": false,
+            "PowerAnalysis": false,
+            "SimulationName": "ddr5",
+            "SimulationProgressBar": true,
+            "StoreMode": "NoStorage",
+            "UseMalloc": false,
+            "WindowSize": 1000
+        },
+        "simulationid": "ddr5-example",
+        "tracesetup": [
+            {
+                "clkMhz": 1600,
+                "name": "trace_test3.stl"
+            }
+        ]
+    }
+}
--- a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb
+++ b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch0.tdb
--- a/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb
+++ b/tests/tests_regression/DDR5/expected/DRAMSys_ddr5-example_ddr5_ch1.tdb
--- a/tests/tests_regression/DDR5/traces/trace_test3.stl
+++ b/tests/tests_regression/DDR5/traces/trace_test3.stl
--- a/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch0.tdb
+++ b/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch0.tdb
--- a/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch1.tdb
+++ b/tests/tests_regression/HBM2/expected/DRAMSys_hbm2-example_hbm2_ch1.tdb
--- a/tests/tests_regression/HBM2/hbm2-example.json
+++ b/tests/tests_regression/HBM2/hbm2-example.json
@@ -51,7 +51,7 @@
            "RequestBufferSize": 8,
            "CmdMux": "Strict",
            "RespQueue": "Fifo",
-            "RefreshPolicy": "NoRefresh",
+            "RefreshPolicy": "PerBank",
            "RefreshMaxPostponed": 0,
            "RefreshMaxPulledin": 0,
            "PowerDownPolicy": "NoPowerDown",
--- a/tests/tests_regression/HBM2/hbm2.txt
+++ b/tests/tests_regression/HBM2/hbm2.txt
--- a/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb
+++ b/tests/tests_regression/HBM3/expected/DRAMSys_hbm3-example_hbm3_ch0.tdb
--- a/tests/tests_regression/HBM3/hbm3-example.json
+++ b/tests/tests_regression/HBM3/hbm3-example.json
@@ -0,0 +1,138 @@
+{
+    "simulation": {
+        "addressmapping": {
+            "PSEUDOCHANNEL_BIT":[
+                29
+            ],
+            "BANKGROUP_BIT":[
+                27,
+                28
+            ],
+            "BANK_BIT": [
+                25,
+                26
+            ],
+            "BYTE_BIT": [
+                0,
+                1
+            ],
+            "COLUMN_BIT": [
+                2,
+                3,
+                4,
+                5,
+                6,
+                7,
+                8
+            ],
+            "ROW_BIT": [
+                9,
+                10,
+                11,
+                12,
+                13,
+                14,
+                15,
+                16,
+                17,
+                18,
+                19,
+                20,
+                21,
+                22,
+                23,
+                24
+            ]
+        },
+        "mcconfig": {
+            "PagePolicy": "Closed",
+            "Scheduler": "Fifo",
+            "RequestBufferSize": 8,
+            "CmdMux": "Strict",
+            "RespQueue": "Fifo",
+            "RefreshPolicy": "PerBank",
+            "RefreshMaxPostponed": 0,
+            "RefreshMaxPulledin": 0,
+            "PowerDownPolicy": "NoPowerDown",
+            "PowerDownTimeout": 100
+        },
+        "memspec": {
+            "memarchitecturespec": {
+                "burstLength": 8,
+                "dataRate": 4,
+                "nbrOfBankGroups": 4,
+                "nbrOfBanks": 16,
+                "nbrOfColumns": 128,
+                "nbrOfPseudoChannels": 2,
+                "nbrOfRows": 65536,
+                "width": 32,
+                "nbrOfDevices": 1,
+                "nbrOfChannels": 1,
+                "RAAIMT" : 16,
+                "RAAMMT" : 96,
+                "RAADEC" : 16
+            },
+            "memoryId": "",
+            "memoryType": "HBM3",
+            "memtimingspec": {
+                "CCDL": 4,
+                "CCDS": 2,
+                "CKE": 8,
+                "DQSCK": 1,
+                "FAW": 16,
+                "PL": 0,
+                "PPD": 2,
+                "RAS": 28,
+                "RC": 42,
+                "RCDRD": 12,
+                "RCDWR": 6,
+                "REFI": 3900,
+                "REFIPB": 122,
+                "RFC": 260,
+                "RFCPB": 96,
+                "RL": 17,
+                "RP": 14,
+                "RRDL": 6,
+                "RRDS": 4,
+                "RREFD": 8,
+                "RTP": 5,
+                "RTW": 18,
+                "WL": 12,
+                "WR": 23,
+                "WTRL": 9,
+                "WTRS": 4,
+                "XP": 8,
+                "XS": 260,
+                "clkMhz": 1600
+            }
+        },
+        "simconfig": {
+            "AddressOffset": 0,
+            "CheckTLM2Protocol": false,
+            "DatabaseRecording": true,
+            "Debug": false,
+            "ECCControllerMode": "Disabled",
+            "EnableWindowing": false,
+            "ErrorCSVFile": "",
+            "ErrorChipSeed": 42,
+            "PowerAnalysis": false,
+            "SimulationName": "hbm3",
+            "SimulationProgressBar": true,
+            "StoreMode": "NoStorage",
+            "ThermalSimulation": false,
+            "UseMalloc": false,
+            "WindowSize": 1000
+        },
+        "simulationid": "hbm3-example",
+        "tracesetup": [
+            {
+                "clkMhz": 1600,
+                "name": "trace1_test4.stl"
+            },
+	    {
+                "clkMhz": 1600,
+                "name": "trace2_test4.stl"
+            }
+        ]
+    }
+}
--- a/tests/tests_regression/HBM3/traces/trace1_test4.stl
+++ b/tests/tests_regression/HBM3/traces/trace1_test4.stl
--- a/tests/tests_regression/HBM3/traces/trace2_test4.stl
+++ b/tests/tests_regression/HBM3/traces/trace2_test4.stl
--- a/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb
+++ b/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr4-example_lpddr4_ch0.tdb
--- a/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr5-example_lpddr5_ch0.tdb
+++ b/tests/tests_regression/LPDDR5/expected/DRAMSys_lpddr5-example_lpddr5_ch0.tdb
--- a/tests/tests_regression/LPDDR5/lpddr5-example.json
+++ b/tests/tests_regression/LPDDR5/lpddr5-example.json
@@ -0,0 +1,141 @@
+{
+    "simulation": {
+        "addressmapping": {
+            "BANKGROUP_BIT": [
+                5,
+                6
+            ],
+            "BANK_BIT": [
+                7,
+                8
+            ],
+            "BYTE_BIT": [
+                0
+            ],
+            "COLUMN_BIT": [
+                1,
+                2,
+                3,
+                4,
+                9,
+                10,
+                11,
+                12,
+                13,
+                14
+            ],
+            "ROW_BIT": [
+                15,
+                16,
+                17,
+                18,
+                19,
+                20,
+                21,
+                22,
+                23,
+                24,
+                25,
+                26,
+                27,
+                28,
+                29,
+                30
+            ]
+        },
+        "mcconfig": {
+            "Arbiter": "Simple",
+            "CmdMux": "Oldest",
+            "MaxActiveTransactions": 128,
+            "PagePolicy": "Open",
+            "PowerDownPolicy": "NoPowerDown",
+            "RefreshManagement": false,
+            "RefreshMaxPostponed": 0,
+            "RefreshMaxPulledin": 0,
+            "RefreshPolicy": "Per2Bank",
+            "RequestBufferSize": 8,
+            "RespQueue": "Fifo",
+            "Scheduler": "FrFcfs",
+            "SchedulerBuffer": "Bankwise"
+        },
+        "memspec": {
+            "memarchitecturespec": {
+                "burstLength": 16,
+                "dataRate": 8,
+                "nbrOfBankGroups": 4,
+                "nbrOfBanks": 16,
+                "nbrOfChannels": 1,
+                "nbrOfColumns": 1024,
+                "nbrOfDevices": 1,
+                "nbrOfRanks": 1,
+                "nbrOfRows": 65536,
+                "per2BankOffset": 8,
+                "width": 16
+            },
+            "memoryId": "JEDEC_1Gbx16_BG_LPDDR5-6400",
+            "memoryType": "LPDDR5",
+            "memtimingspec": {
+                "BL_n_L_16": 4,
+                "BL_n_L_32": 8,
+                "BL_n_S_16": 2,
+                "BL_n_S_32": 2,
+                "BL_n_max_16": 4,
+                "BL_n_max_32": 8,
+                "BL_n_min_16": 2,
+                "BL_n_min_32": 6,
+                "CCDMW": 16,
+                "FAW": 16,
+                "PPD": 2,
+                "RAS": 34,
+                "RBTP": 4,
+                "RCD_L": 15,
+                "RCD_S": 15,
+                "RCab": 51,
+                "RCpb": 48,
+                "REFI": 3124,
+                "REFIpb": 390,
+                "RFCab": 224,
+                "RFCpb": 112,
+                "RL": 17,
+                "RPRE": 0,
+                "RPST": 0,
+                "RPab": 17,
+                "RPpb": 15,
+                "RRD": 4,
+                "RTRS": 1,
+                "WCK2CK": 0,
+                "WCK2DQI": 0,
+                "WCK2DQO": 1,
+                "WL": 9,
+                "WPRE": 0,
+                "WPST": 0,
+                "WR": 28,
+                "WTR_L": 10,
+                "WTR_S": 5,
+                "clkMhz": 800,
+                "pbR2act": 6,
+                "pbR2pbR": 72
+            }
+        },
+        "simconfig": {
+            "AddressOffset": 0,
+            "CheckTLM2Protocol": false,
+            "DatabaseRecording": true,
+            "Debug": false,
+            "EnableWindowing": false,
+            "PowerAnalysis": false,
+            "SimulationName": "example",
+            "SimulationProgressBar": true,
+            "StoreMode": "NoStorage",
+            "UseMalloc": false,
+            "WindowSize": 1000
+        },
+        "simulationid": "lpddr5-example",
+        "tracesetup": [
+            {
+                "clkMhz": 1600,
+                "name": "trace_lpddr5.stl"
+            }
+        ]
+    }
+}
--- a/tests/tests_regression/LPDDR5/traces/trace_lpddr5.stl
+++ b/tests/tests_regression/LPDDR5/traces/trace_lpddr5.stl
--- a/tests/tests_regression/compare.sh
+++ b/tests/tests_regression/compare.sh
@@ -1,9 +0,0 @@
-#!/bin/bash
-
-# When comparing the whole database, we do not care if there are differences or not.
-# The tables that need to be checked have their own tests.
-# The purpose of this script is solely to output the differences of the two databases
-# so that they can be inspected easily.
-
-sqldiff ${CMAKE_CURRENT_SOURCE_DIR}/${standard}/expected/${output_filename} ${output_filename}
-exit 0
--- a/tests/tests_regression/compare_table.sh
+++ b/tests/tests_regression/compare_table.sh
@@ -1,10 +0,0 @@
-#!/bin/bash
-
-stdout=$(sqldiff --table ${table} ${CMAKE_CURRENT_SOURCE_DIR}/${standard}/expected/${output_filename} ${output_filename})
-
-if [[ $stdout ]]; then
-    echo $stdout
-    exit -1
-else
-    exit 0
-fi