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Merge branch 'config_refactor' into 'develop'

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Configuration Refactoring

See merge request ems/astdm/modeling.dram/dram.sys.5!63
This commit is contained in:
Lukas Steiner
2024-02-23 14:29:06 +00:00
parent d0c3c04098 1a2e5497ee
commit 5b4ed9559d
117 changed files with 2557 additions and 3035 deletions
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4
tests/tests_configuration/reference.json
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@@ -145,8 +145,6 @@
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": false,
"ErrorCSVFile": "error.csv",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "ddr5",
"SimulationProgressBar": true,
@@ -207,4 +205,4 @@
}
]
}
}
}

2
tests/tests_configuration/resources/simconfig/ddr5.json
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@@ -6,8 +6,6 @@
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "ddr5",
"SimulationProgressBar": true,

10
tests/tests_configuration/test_configuration.cpp
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@@ -108,8 +108,6 @@ protected:
true,
false,
false,
{"error.csv"},
42,
false,
{"ddr5"},
true,
@@ -168,7 +166,11 @@ DRAMSys::Config::MemSpec ConfigurationTest::createMemSpec()
{"clkMhz", 1600},
}}};
return {memArchitectureSpec, "JEDEC_2x8x2Gbx4_DDR5-3200A", "DDR5", memTimingSpec, {}};
return {memArchitectureSpec,
"JEDEC_2x8x2Gbx4_DDR5-3200A",
DRAMSys::Config::MemoryType::DDR5,
memTimingSpec,
{}};
}
DRAMSys::Config::TracePlayer ConfigurationTest::createTracePlayer()
@@ -319,8 +321,6 @@ TEST_F(ConfigurationTest, SimConfig)
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": false,
"ErrorCSVFile": "error.csv",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "ddr5",
"SimulationProgressBar": true,

5
tests/tests_dramsys/b_transport/b_transport.cpp
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@@ -36,7 +36,6 @@
#include <gtest/gtest.h>
#include <DRAMSys/simulation/DRAMSys.h>
#include <DRAMSys/simulation/dram/Dram.h>
class SystemCTest : public testing::Test
{
@@ -92,7 +91,7 @@ struct BlockingInitiator : sc_core::sc_module
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
iSocket->b_transport(payload, delay);
EXPECT_EQ(delay, dramSys.getConfig().blockingReadDelay);
EXPECT_EQ(delay, dramSys.getMcConfig().blockingReadDelay);
}
void writeAccess()
@@ -105,7 +104,7 @@ struct BlockingInitiator : sc_core::sc_module
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
iSocket->b_transport(payload, delay);
EXPECT_EQ(delay, dramSys.getConfig().blockingWriteDelay);
EXPECT_EQ(delay, dramSys.getMcConfig().blockingWriteDelay);
}
};

2
tests/tests_dramsys/b_transport/configs/no_storage.json
View File

@@ -138,8 +138,6 @@
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "example",
"SimulationProgressBar": true,

2
tests/tests_dramsys/b_transport/configs/storage.json
View File

@@ -136,8 +136,6 @@
"DatabaseRecording": true,
"Debug": false,
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "example",
"SimulationProgressBar": true,