101 Commits

Author SHA1 Message Date
1ef2b3bd9c chore: update DRAMUtils version
Update the DRAMUtils version and fix all configs that now require DBI
parameters for the memimpedance spec.
2025-11-21 16:02:11 +01:00
adf374ad81 Fix DDR4 test after upgrade to SystemC 3 2025-10-10 10:09:35 +02:00
db74e7549a Update to SystemC 3.0.1
Fix some of the deprecation warnings introduced in the new version such
as the removal of SC_HAS_PROCESS.
2025-10-10 09:39:13 +02:00
7e10f627c0 Fix various compile warnings 2025-09-24 15:58:54 +02:00
7e77593f23 Use integer address in decode function again 2025-09-24 15:58:54 +02:00
ac39afbf1d Disable clang-tidy warnings in configuration test 2025-09-24 15:58:54 +02:00
cc85eefaf6 Add common MemoryManager 2025-09-24 15:58:54 +02:00
Thomas Zimmermann
ce1332ca81 Feature: Rewrote AddressDecoder 2025-09-22 12:00:49 +00:00
565e725cf6 Make dataLength parameter required for initiators 2025-08-06 09:37:12 +02:00
8c861d81c9 Decouple initiator clock from memory responses
Previously, the initiators were implicitly coupled to the responses of
the memory, calculating each new initiator clock relatively based on the
time of the BEGIN_RESP phase. This lead to an implicit coupling as
same rounding error of the initiator clock to the memory clock was
applied each time again.

Now, initiators are in itself self-clocked and only send requests based
on backpressure.
2025-08-06 09:35:07 +02:00
marcomoerz
bc8274433a Deserialize std::variant without throwing exception 2025-05-09 16:45:54 +02:00
marcomoerz
4120e9c35b Integrate DRAMUtils and new DRAMPower 2025-05-09 16:45:54 +02:00
Lukas Steiner
1863987af3 Merge branch 'feat/remove_resource_directory' into 'develop'
Remove the concept of a resource directory

See merge request ems/astdm/modeling.dram/dram.sys.5!115
2025-04-24 14:12:23 +00:00
Lukas Steiner
0f2be6ece5 Merge branch 'fix/lpddr5_ref' into 'develop'
Fix LPDDR5 AllBank and Per2Bank Refresh

See merge request ems/astdm/modeling.dram/dram.sys.5!114
2025-04-24 14:07:59 +00:00
a4d8705c8d Fix crash in Cache Test 2025-04-23 14:18:49 +02:00
939fc90f98 Remove hard-coded subdirectory paths for configs
Previously, the subdirectories in which the sub-json files were searched
in were hardcoded. Now, DRAMSys simply searches in the directory of the
base config, making this approach more flexible.
2025-04-15 14:56:35 +02:00
a97b676b92 Remove the concept of a resource directory
The concept of a resource directory was confusing, error-prone and
was only used to specify the directory of the base config json anyway.
Therefore, remove the concept of the resource directory and use the
parent directory of the base config directly.
2025-04-15 14:56:35 +02:00
ee85f0df8f Merge branch 'refactor/database' into 'develop'
Removal of Recordable abstractions

See merge request ems/astdm/modeling.dram/dram.sys.5!110
2025-04-15 12:54:06 +00:00
42d17f95ec Merge branch 'tools/json_converter' into 'develop'
Make tool out of json_converter

See merge request ems/astdm/modeling.dram/dram.sys.5!112
2025-04-11 13:23:59 +00:00
0dc9eeeea2 Add optional support for vcpkg 2025-04-10 08:46:39 +02:00
330d5c77b6 Fix LPDDR5 regression test 2025-04-08 17:42:30 +02:00
Jonathan Hager
d773abc7ce Updated unit tests for HBM2
This is necessary, as recording the phases with tlmRecorders on the bus
changed the internal call order in the SystemC kernel. This leads to
different IDs in the database
2025-03-26 13:53:23 +01:00
dc81bc008a Make tool out of json_converter 2025-03-26 09:08:36 +01:00
98eae7fcf4 Fix the forward declaration of the Dram class 2025-03-25 19:18:09 +01:00
dbb6636c5a Fix LPDDR4 and LPDDR5 regression tests 2025-02-26 17:10:11 +01:00
6861576550 Implement tCCDR for HBM2 and fix bug with SID 2025-02-21 14:18:30 +01:00
Lukas Steiner
f223e6c500 Merge branch 'feat/hbm3_sid' into 'develop'
Feat/hbm3 sid

See merge request ems/astdm/modeling.dram/dram.sys.5!96
2025-01-28 09:04:16 +00:00
581794b970 Allow responses to be sent back-to-back 2025-01-24 14:58:06 +01:00
ba94d9fd84 Have a one cycle END_RESP delay in the standard initiator 2025-01-24 14:43:06 +01:00
1225f6b044 Fix tests after ThinkDelayFw 2025-01-24 14:19:53 +01:00
7a8633d36e Implement stack ID for HBM3 2025-01-13 15:36:05 +01:00
a82efdbb3a Fix HBM3 regression test 2025-01-13 10:24:09 +01:00
aba5ba6e2e Switch to Open page policy for HBM3 regression test 2025-01-10 16:42:42 +01:00
83cc41e318 Minor refactorings of CMakeList files 2025-01-09 08:12:49 +00:00
e2342350d0 Minor improvements on package handling 2024-12-20 17:40:15 +01:00
c3eb5e6a62 Hide the use of FetchContent behind a flag
FetchContent is now disabled by default, when the project is included as
an subproject by another top-level project.
Also, every usage of FetchContent is behind a separate flag to enable and
disable the usage with granular control.
2024-12-20 17:40:15 +01:00
ca9ef16d0d Remove unnecessary project() calls
project() should only be called if the subdirectory, in fact, can be
built standalone.
2024-12-20 17:40:15 +01:00
e1b8bbf12d Clean up and refactor CMakeLists 2024-12-20 17:40:15 +01:00
a37171c6fd Remove file globs from CMakeLists
Fix build
2024-12-20 17:40:15 +01:00
Lukas Steiner
5825eb8c58 Merge branch 'feat/simulation_time' into 'develop'
Introduce SimulationTime config

Closes #62

See merge request ems/astdm/modeling.dram/dram.sys.5!91
2024-12-17 14:52:22 +00:00
ecf9127faa Fix some tests and refactor simulation script 2024-12-11 12:56:56 +01:00
703ee81d7e Introduce SimulationTime config
Use SimulationTime to forcefully stop simulation at a specified point in
time.
2024-12-10 10:04:59 +01:00
5dd7c22a74 Refactor CMakeLists and GitLab CI/CD pipeline
- Remove nested minimum required to supress warnings.
- Declare SystemC as system library to supress warnings in headers.
- Add a BUILD_SHARED_LIBS option
- Remove hardcoded STATIC in various add_library calls to honor the
  BUILD_SHARED_LIBS option
- Remove _deps/ directory from the build directory in GitLab pipeline
- Remove *.tdb files after test stage in pipeline
- Set Ninja as the default generator for the dev preset and re-enable
  colored diagnostics
2024-06-28 11:07:56 +02:00
12bfba1fb3 Fix various bugs
- Fix data race for some tests by disabling database recording
- Fix undefined behaviour in configuration test
- Port clkMhz to tCK for simulation script
- Port memUtil Python script to tCK with backwards compatibility
2024-02-26 09:58:19 +01:00
Lukas Steiner
5b4ed9559d Merge branch 'config_refactor' into 'develop'
Configuration Refactoring

See merge request ems/astdm/modeling.dram/dram.sys.5!63
2024-02-23 14:29:06 +00:00
539a525f3d Fix DDR3 regression
Using the new tCK entry in the memspecs, there was a small power deviation in the database
2024-02-23 12:04:29 +01:00
0ec6ea79ad Migrate from clkMhz to tCK entry in memspecs 2024-02-23 12:04:22 +01:00
59cf73fe9c Clean up public API (DRAMSys.h)
Remove DRAMSysRecordable.h/cpp as the functionality has been incorporated into
DRAMSys.h/cpp. The databaseRecording config is now completely handled by
DRAMSys itself without needing the user of the library to instanciate DRAMSys
or DRAMSysRecordable depending on this config.
2024-02-23 11:54:51 +01:00
5391b4351d Fix configuration tests 2024-02-23 11:54:51 +01:00
454cb00ddb Refactor: remove monolithic configuration class 2024-02-23 11:54:51 +01:00