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Fix various compile warnings

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This commit is contained in:
Derek Christ
2025-09-24 08:21:52 +02:00
parent 6af3dd5b28
commit 7e10f627c0
6 changed files with 14 additions and 21 deletions
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16
src/libdramsys/DRAMSys/simulation/Dram.cpp
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@@ -159,17 +159,15 @@ Dram::nb_transport_fw(tlm_generic_payload& trans, tlm_phase& phase, [[maybe_unus
if (DRAMPower)
{
std::size_t channel = static_cast<std::size_t>(ArbiterExtension::getChannel(trans));
std::size_t rank = static_cast<std::size_t>(
auto rank = static_cast<std::size_t>(
ControllerExtension::getRank(trans)); // relaitve to the channel
std::size_t bank_group_abs = static_cast<std::size_t>(
auto bank_group_abs = static_cast<std::size_t>(
ControllerExtension::getBankGroup(trans)); // relative to the channel
std::size_t bank_group =
bank_group_abs - rank * memSpec.groupsPerRank; // relative to the rank
std::size_t bank = static_cast<std::size_t>(ControllerExtension::getBank(trans)) -
bank_group_abs * memSpec.banksPerGroup; // relative to the bank_group
std::size_t row = static_cast<std::size_t>(ControllerExtension::getRow(trans));
std::size_t column = static_cast<std::size_t>(ControllerExtension::getColumn(trans));
auto bank_group = bank_group_abs - (rank * memSpec.groupsPerRank); // relative to the rank
auto bank = static_cast<std::size_t>(ControllerExtension::getBank(trans)) -
(bank_group_abs * memSpec.banksPerGroup); // relative to the bank_group
auto row = static_cast<std::size_t>(ControllerExtension::getRow(trans));
auto column = static_cast<std::size_t>(ControllerExtension::getColumn(trans));
uint64_t cycle = std::lround((sc_time_stamp() + delay) / memSpec.tCK);
// DRAMPower:

8
src/simulator/simulator/Simulator.cpp
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@@ -86,14 +86,8 @@ Simulator::instantiateInitiator(const DRAMSys::Config::Initiator& initiator)
uint64_t memorySize = dramSys->getMemSpec().getSimMemSizeInBytes();
sc_core::sc_time interfaceClk = dramSys->getMemSpec().tCK;
// To support non-power-of-two values for the burst length and width, we round the BL
// down to the smaller-or-equal power-of-two.
unsigned int burstBits = std::log2(dramSys->getMemSpec().defaultBurstLength);
unsigned int widthBits = std::log2(dramSys->getMemSpec().dataBusWidth);
unsigned int defaultDataLength = std::pow(2, burstBits) * std::pow(2, widthBits) / 8;
return std::visit(
[=](auto&& config) -> std::unique_ptr<RequestIssuer>
[this, memorySize, interfaceClk](auto&& config) -> std::unique_ptr<RequestIssuer>
{
using T = std::decay_t<decltype(config)>;
if constexpr (std::is_same_v<T, DRAMSys::Config::TrafficGenerator> ||

4
src/simulator/simulator/generator/TrafficGenerator.cpp
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@@ -49,7 +49,7 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGeneratorStateMachine
for (auto const& state : config.states)
{
std::visit(
[=, &config](auto&& arg)
[this, memorySize, dataLength, dataAlignment, &config](auto&& arg)
{
using DRAMSys::Config::TrafficGeneratorActiveState;
using DRAMSys::Config::TrafficGeneratorIdleState;
@@ -132,7 +132,7 @@ TrafficGenerator::TrafficGenerator(DRAMSys::Config::TrafficGenerator const& conf
Request TrafficGenerator::nextRequest()
{
if (currentState == STOP_STATE)
return Request{Request::Command::Stop};
return Request{Request::Command::Stop, 0, 0, {}};
Request request = producers[currentState]->nextRequest();
requestsInState++;

2
src/simulator/simulator/hammer/RowHammer.cpp
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@@ -46,7 +46,7 @@ RowHammer::RowHammer(DRAMSys::Config::RowHammer const& config) :
Request RowHammer::nextRequest()
{
if (generatedRequests >= numberOfRequests)
return Request{Request::Command::Stop};
return Request{Request::Command::Stop, 0, 0, {}};
generatedRequests++;

2
src/simulator/simulator/player/StlPlayer.cpp
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@@ -108,7 +108,7 @@ Request StlPlayer::nextRequest()
if (!currentLineContent.has_value())
{
// The file is read in completely. Nothing more to do.
return Request{Request::Command::Stop};
return Request{Request::Command::Stop, 0, 0, {}};
}
auto command = currentLineContent->command == LineContent::Command::Read

3
tests/tests_dramsys/AddressDecoderTests.cpp
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@@ -93,8 +93,9 @@ TEST_F(AddressDecoderFixture, DecodingNP2Failure)
addressDecoder.plausibilityCheck(*memSpec);
uint64_t address = 0x3A59'1478;
addressDecoder.decodeAddress(address);
std::ignore = addressDecoder.decodeAddress(address);
// EXPECT_EQ(trans.get_response_status(), tlm::TLM_ADDRESS_ERROR_RESPONSE);
}
TEST_F(AddressDecoderFixture, DecodingNP2Success)