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Add common MemoryManager

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This commit is contained in:
Derek Christ
2024-05-15 15:01:50 +02:00
committed by Derek Christ
parent 417bc26ce1
commit cc85eefaf6
16 changed files with 139 additions and 183 deletions
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1
src/libdramsys/CMakeLists.txt
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@@ -51,6 +51,7 @@ add_library(libdramsys
DRAMSys/common/DramATRecorder.cpp
DRAMSys/common/dramExtensions.cpp
DRAMSys/common/utils.cpp
DRAMSys/common/MemoryManager.cpp
DRAMSys/configuration/memspec/MemSpec.cpp
DRAMSys/configuration/memspec/MemSpecDDR3.cpp
DRAMSys/configuration/memspec/MemSpecDDR4.cpp

51
src/simulator/simulator/MemoryManager.cpp → src/libdramsys/DRAMSys/common/MemoryManager.cpp
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015, RPTU Kaiserslautern-Landau
* Copyright (c) 2024, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -32,46 +33,40 @@
* Authors:
* Robert Gernhardt
* Matthias Jung
* Lukas Steiner
* Derek Christ
*/
#include "MemoryManager.h"
#include "DRAMSys/common/DebugManager.h"
using namespace tlm;
MemoryManager::MemoryManager(bool storageEnabled) : storageEnabled(storageEnabled)
namespace DRAMSys
{
}
MemoryManager::MemoryManager(bool storageEnabled) : storageEnabled(storageEnabled) {};
MemoryManager::~MemoryManager()
{
for (auto& innerBuffer : freePayloads)
for (auto& [size, stack] : freePayloads)
{
while (!innerBuffer.second.empty())
while (!stack.empty())
{
tlm_generic_payload* payload = innerBuffer.second.top();
if (storageEnabled)
tlm::tlm_generic_payload* payload = stack.top();
if (size != 0)
delete[] payload->get_data_ptr();
payload->reset();
delete payload;
innerBuffer.second.pop();
numberOfFrees++;
stack.pop();
}
}
// Comment in if you are suspecting a memory leak in the manager
// PRINTDEBUGMESSAGE("MemoryManager","Number of allocated payloads: " +
// to_string(numberOfAllocations)); PRINTDEBUGMESSAGE("MemoryManager","Number of freed payloads:
// " + to_string(numberOfFrees));
}
tlm_generic_payload& MemoryManager::allocate(unsigned dataLength)
tlm::tlm_generic_payload* MemoryManager::allocate(std::size_t dataLength)
{
if (freePayloads[dataLength].empty())
{
numberOfAllocations++;
auto* payload = new tlm_generic_payload(this);
auto* payload = new tlm::tlm_generic_payload(this);
if (storageEnabled)
{
@@ -81,16 +76,18 @@ tlm_generic_payload& MemoryManager::allocate(unsigned dataLength)
payload->set_data_ptr(data);
}
return *payload;
return payload;
}
tlm_generic_payload* result = freePayloads[dataLength].top();
tlm::tlm_generic_payload* result = freePayloads[dataLength].top();
freePayloads[dataLength].pop();
return *result;
return result;
}
void MemoryManager::free(tlm_generic_payload* payload)
void MemoryManager::free(tlm::tlm_generic_payload* trans)
{
unsigned dataLength = payload->get_data_length();
freePayloads[dataLength].push(payload);
unsigned dataLength = trans->get_data_length();
freePayloads[dataLength].push(trans);
}
} // namespace DRAMSys

20
src/simulator/simulator/MemoryManager.h → src/libdramsys/DRAMSys/common/MemoryManager.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, RPTU Kaiserslautern-Landau
* Copyright (c) 2024, RPTU Kaiserslautern-Landau
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -32,6 +32,7 @@
* Authors:
* Robert Gernhardt
* Matthias Jung
* Lukas Steiner
* Derek Christ
*/
@@ -42,24 +43,27 @@
#include <tlm>
#include <unordered_map>
namespace DRAMSys
{
class MemoryManager : public tlm::tlm_mm_interface
{
public:
explicit MemoryManager(bool storageEnabled);
MemoryManager(bool storageEnabled);
MemoryManager(const MemoryManager&) = delete;
MemoryManager(MemoryManager&&) = delete;
MemoryManager& operator=(const MemoryManager&) = delete;
MemoryManager& operator=(MemoryManager&&) = delete;
~MemoryManager() override;
tlm::tlm_generic_payload& allocate(unsigned dataLength);
void free(tlm::tlm_generic_payload* payload) override;
tlm::tlm_generic_payload* allocate(std::size_t dataLength = 0);
void free(tlm::tlm_generic_payload* trans) override;
private:
uint64_t numberOfAllocations = 0;
uint64_t numberOfFrees = 0;
std::unordered_map<unsigned, std::stack<tlm::tlm_generic_payload*>> freePayloads;
bool storageEnabled = false;
std::unordered_map<std::size_t, std::stack<tlm::tlm_generic_payload*>> freePayloads;
bool storageEnabled;
};
} // namespace DRAMSys
#endif // MEMORYMANAGER_H

64
src/libdramsys/DRAMSys/controller/Controller.cpp
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@@ -102,7 +102,8 @@ Controller::Controller(const sc_module_name& name,
nextWindowEventTime(windowSizeTime),
numberOfBeatsServed(memSpec.ranksPerChannel, 0),
minBytesPerBurst(memSpec.defaultBytesPerBurst),
maxBytesPerBurst(memSpec.maxBytesPerBurst)
maxBytesPerBurst(memSpec.maxBytesPerBurst),
memoryManager(simConfig.storeMode == Config::StoreModeType::Store)
{
if (simConfig.databaseRecording && tlmRecorder != nullptr)
{
@@ -741,34 +742,6 @@ void Controller::sendToFrontend(tlm_generic_payload& trans, tlm_phase& phase, sc
tSocket->nb_transport_bw(trans, phase, delay);
}
Controller::MemoryManager::~MemoryManager()
{
while (!freePayloads.empty())
{
tlm_generic_payload* trans = freePayloads.top();
freePayloads.pop();
trans->reset();
delete trans;
}
}
tlm::tlm_generic_payload& Controller::MemoryManager::allocate()
{
if (freePayloads.empty())
{
return *new tlm_generic_payload(this);
}
tlm_generic_payload* result = freePayloads.top();
freePayloads.pop();
return *result;
}
void Controller::MemoryManager::free(tlm::tlm_generic_payload* trans)
{
freePayloads.push(trans);
}
void Controller::createChildTranses(tlm::tlm_generic_payload& parentTrans)
{
std::vector<tlm_generic_payload*> childTranses;
@@ -779,14 +752,14 @@ void Controller::createChildTranses(tlm::tlm_generic_payload& parentTrans)
for (unsigned childId = 0; childId < numChildTranses; childId++)
{
tlm_generic_payload& childTrans = memoryManager.allocate();
childTrans.acquire();
childTrans.set_command(parentTrans.get_command());
childTrans.set_address(startAddress + childId * maxBytesPerBurst);
childTrans.set_data_length(maxBytesPerBurst);
childTrans.set_data_ptr(startDataPtr + childId * maxBytesPerBurst);
ChildExtension::setExtension(childTrans, parentTrans);
childTranses.push_back(&childTrans);
tlm_generic_payload* childTrans = memoryManager.allocate();
childTrans->acquire();
childTrans->set_command(parentTrans.get_command());
childTrans->set_address(startAddress + childId * maxBytesPerBurst);
childTrans->set_data_length(maxBytesPerBurst);
childTrans->set_data_ptr(startDataPtr + childId * maxBytesPerBurst);
ChildExtension::setExtension(*childTrans, parentTrans);
childTranses.push_back(childTrans);
}
if (startAddress != parentTrans.get_address())
@@ -795,14 +768,15 @@ void Controller::createChildTranses(tlm::tlm_generic_payload& parentTrans)
firstChildTrans.set_address(firstChildTrans.get_address() + minBytesPerBurst);
firstChildTrans.set_data_ptr(firstChildTrans.get_data_ptr() + minBytesPerBurst);
firstChildTrans.set_data_length(minBytesPerBurst);
tlm_generic_payload& lastChildTrans = memoryManager.allocate();
lastChildTrans.acquire();
lastChildTrans.set_command(parentTrans.get_command());
lastChildTrans.set_address(startAddress + numChildTranses * maxBytesPerBurst);
lastChildTrans.set_data_length(minBytesPerBurst);
lastChildTrans.set_data_ptr(startDataPtr + numChildTranses * maxBytesPerBurst);
ChildExtension::setExtension(lastChildTrans, parentTrans);
childTranses.push_back(&lastChildTrans);
tlm_generic_payload* lastChildTrans = memoryManager.allocate();
lastChildTrans->acquire();
lastChildTrans->set_command(parentTrans.get_command());
lastChildTrans->set_address(startAddress + numChildTranses * maxBytesPerBurst);
lastChildTrans->set_data_length(minBytesPerBurst);
lastChildTrans->set_data_ptr(startDataPtr + numChildTranses * maxBytesPerBurst);
ChildExtension::setExtension(*lastChildTrans, parentTrans);
childTranses.push_back(lastChildTrans);
}
for (auto* childTrans : childTranses)

20
src/libdramsys/DRAMSys/controller/Controller.h
View File

@@ -51,6 +51,7 @@
#include "DRAMSys/common/TlmRecorder.h"
#include "DRAMSys/simulation/SimConfig.h"
#include <DRAMSys/common/DebugManager.h>
#include <DRAMSys/common/MemoryManager.h>
#include <DRAMSys/simulation/AddressDecoder.h>
#include <functional>
@@ -148,25 +149,10 @@ private:
const unsigned minBytesPerBurst;
const unsigned maxBytesPerBurst;
MemoryManager memoryManager;
void createChildTranses(tlm::tlm_generic_payload& parentTrans);
class MemoryManager : public tlm::tlm_mm_interface
{
public:
MemoryManager() = default;
MemoryManager(const MemoryManager&) = delete;
MemoryManager(MemoryManager&&) = delete;
MemoryManager& operator=(const MemoryManager&) = delete;
MemoryManager& operator=(MemoryManager&&) = delete;
~MemoryManager() override;
tlm::tlm_generic_payload& allocate();
void free(tlm::tlm_generic_payload* trans) override;
private:
std::stack<tlm::tlm_generic_payload*> freePayloads;
} memoryManager;
class IdleTimeCollector
{
public:

1
src/simulator/CMakeLists.txt
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@@ -43,7 +43,6 @@ find_package(Threads)
add_library(simulator
simulator/Cache.cpp
simulator/EccModule.cpp
simulator/MemoryManager.cpp
simulator/Simulator.cpp
simulator/generator/RandomState.cpp
simulator/generator/SequentialState.cpp

43
src/simulator/simulator/Cache.cpp
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@@ -35,7 +35,6 @@
*/
#include "Cache.h"
#include "MemoryManager.h"
#include <cstring>
@@ -55,7 +54,7 @@ Cache::Cache(const sc_module_name& name,
bool storageEnabled,
sc_core::sc_time cycleTime,
std::size_t hitCycles,
MemoryManager& memoryManager) :
DRAMSys::MemoryManager& memoryManager) :
sc_module(name),
payloadEventQueue(this, &Cache::peqCallback),
storageEnabled(storageEnabled),
@@ -432,17 +431,17 @@ Cache::CacheLine* Cache::evictLine(Cache::index_t index)
if (oldestLine.valid && oldestLine.dirty)
{
auto& wbTrans = memoryManager.allocate(lineSize);
wbTrans.acquire();
wbTrans.set_address(encodeAddress(index, oldestLine.tag));
wbTrans.set_write();
wbTrans.set_data_length(lineSize);
wbTrans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
auto* wbTrans = memoryManager.allocate(lineSize);
wbTrans->acquire();
wbTrans->set_address(encodeAddress(index, oldestLine.tag));
wbTrans->set_write();
wbTrans->set_data_length(lineSize);
wbTrans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
if (storageEnabled)
std::copy(oldestLine.dataPtr, oldestLine.dataPtr + lineSize, wbTrans.get_data_ptr());
std::copy(oldestLine.dataPtr, oldestLine.dataPtr + lineSize, wbTrans->get_data_ptr());
writeBuffer.emplace_back(index, oldestLine.tag, &wbTrans);
writeBuffer.emplace_back(index, oldestLine.tag, wbTrans);
}
oldestLine.allocated = false;
@@ -500,13 +499,13 @@ void Cache::processMshrQueue()
// Prevents that the cache line will get fetched multiple times from the target
mshrIt->issued = true;
auto& fetchTrans = memoryManager.allocate(lineSize);
fetchTrans.acquire();
fetchTrans.set_read();
fetchTrans.set_data_length(lineSize);
fetchTrans.set_streaming_width(lineSize);
fetchTrans.set_address(alignedAddress);
fetchTrans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
auto* fetchTrans = memoryManager.allocate(lineSize);
fetchTrans->acquire();
fetchTrans->set_read();
fetchTrans->set_data_length(lineSize);
fetchTrans->set_streaming_width(lineSize);
fetchTrans->set_address(alignedAddress);
fetchTrans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
tlm_phase fwPhase = BEGIN_REQ;
@@ -514,22 +513,22 @@ void Cache::processMshrQueue()
// or we cleared the backpressure from another END_REQ.
sc_time fwDelay = cycleTime;
requestInProgress = &fetchTrans;
tlm_sync_enum returnValue = iSocket->nb_transport_fw(fetchTrans, fwPhase, fwDelay);
requestInProgress = fetchTrans;
tlm_sync_enum returnValue = iSocket->nb_transport_fw(*fetchTrans, fwPhase, fwDelay);
if (returnValue == tlm::TLM_UPDATED)
{
// END_REQ or BEGIN_RESP
payloadEventQueue.notify(fetchTrans, fwPhase, fwDelay);
payloadEventQueue.notify(*fetchTrans, fwPhase, fwDelay);
}
else if (returnValue == tlm::TLM_COMPLETED)
{
clearInitiatorBackpressureAndProcessBuffers();
fillLine(fetchTrans);
fillLine(*fetchTrans);
processMshrResponse();
fetchTrans.release();
fetchTrans->release();
}
if (endRequestPending != nullptr && hasBufferSpace())

7
src/simulator/simulator/Cache.h
View File

@@ -36,11 +36,10 @@
#pragma once
#include "MemoryManager.h"
#include <DRAMSys/common/MemoryManager.h>
#include <cstdint>
#include <list>
#include <queue>
#include <systemc>
#include <tlm>
#include <tlm_utils/peq_with_cb_and_phase.h>
@@ -63,7 +62,7 @@ public:
bool storageEnabled,
sc_core::sc_time cycleTime,
std::size_t hitCycles,
MemoryManager& memoryManager);
DRAMSys::MemoryManager& memoryManager);
SC_HAS_PROCESS(Cache);
private:
@@ -217,5 +216,5 @@ private:
sc_core::sc_time ceilTime(const sc_core::sc_time& inTime) const;
sc_core::sc_time ceilDelay(const sc_core::sc_time& inDelay) const;
MemoryManager& memoryManager;
DRAMSys::MemoryManager& memoryManager;
};

26
src/simulator/simulator/EccModule.cpp
View File

@@ -38,12 +38,10 @@
#include "DRAMSys/common/dramExtensions.h"
#include <fstream>
using namespace sc_core;
using namespace tlm;
EccModule::EccModule(sc_module_name name, DRAMSys::AddressDecoder const& addressDecoder) :
EccModule::EccModule(sc_module_name const& name, DRAMSys::AddressDecoder const& addressDecoder) :
sc_core::sc_module(name),
payloadEventQueue(this, &EccModule::peqCallback),
memoryManager(false),
@@ -252,18 +250,18 @@ tlm::tlm_generic_payload* EccModule::generateEccPayload(DRAMSys::DecodedAddress
decodedAddress.column = eccColumn;
uint64_t eccAddress = addressDecoder.encodeAddress(decodedAddress);
tlm_generic_payload& payload = memoryManager.allocate(32);
payload.acquire();
payload.set_address(eccAddress);
payload.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
payload.set_dmi_allowed(false);
payload.set_byte_enable_length(0);
payload.set_data_length(32);
payload.set_streaming_width(32);
payload.set_command(tlm::TLM_READ_COMMAND);
payload.set_extension<DRAMSys::EccExtension>(new DRAMSys::EccExtension);
tlm_generic_payload *payload = memoryManager.allocate(32);
payload->acquire();
payload->set_address(eccAddress);
payload->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
payload->set_dmi_allowed(false);
payload->set_byte_enable_length(0);
payload->set_data_length(32);
payload->set_streaming_width(32);
payload->set_command(tlm::TLM_READ_COMMAND);
payload->set_extension<DRAMSys::EccExtension>(new DRAMSys::EccExtension);
return &payload;
return payload;
}
unsigned int EccModule::alignToBlock(unsigned column)

7
src/simulator/simulator/EccModule.h
View File

@@ -37,8 +37,7 @@
#ifndef ECCMODULE_H
#define ECCMODULE_H
#include "simulator/MemoryManager.h"
#include <DRAMSys/common/MemoryManager.h>
#include <DRAMSys/simulation/AddressDecoder.h>
#include <deque>
@@ -55,7 +54,7 @@ public:
tlm_utils::simple_initiator_socket<EccModule> iSocket;
tlm_utils::simple_target_socket<EccModule> tSocket;
EccModule(sc_core::sc_module_name name, DRAMSys::AddressDecoder const& addressDecoder);
EccModule(sc_core::sc_module_name const& name, DRAMSys::AddressDecoder const& addressDecoder);
SC_HAS_PROCESS(EccModule);
private:
@@ -91,7 +90,7 @@ private:
bool targetBusy = false;
const sc_core::sc_time tCK;
MemoryManager memoryManager;
DRAMSys::MemoryManager memoryManager;
DRAMSys::AddressDecoder const& addressDecoder;
std::unordered_map<Bank, EccQueue> activeEccBlocks;

4
src/simulator/simulator/Simulator.h
View File

@@ -35,9 +35,9 @@
#pragma once
#include "MemoryManager.h"
#include "simulator/request/RequestIssuer.h"
#include <DRAMSys/common/MemoryManager.h>
#include <DRAMSys/config/DRAMSysConfiguration.h>
#include <DRAMSys/simulation/DRAMSys.h>
@@ -52,7 +52,7 @@ private:
std::unique_ptr<RequestIssuer> instantiateInitiator(const DRAMSys::Config::Initiator& initiator);
bool storageEnabled;
MemoryManager memoryManager;
DRAMSys::MemoryManager memoryManager;
DRAMSys::Config::Configuration configuration;

24
src/simulator/simulator/request/RequestIssuer.cpp
View File

@@ -37,7 +37,7 @@
RequestIssuer::RequestIssuer(sc_core::sc_module_name const& name,
std::unique_ptr<RequestProducer> producer,
MemoryManager& memoryManager,
DRAMSys::MemoryManager& memoryManager,
sc_core::sc_time interfaceClk,
std::optional<unsigned int> maxPendingReadRequests,
std::optional<unsigned int> maxPendingWriteRequests,
@@ -79,23 +79,23 @@ void RequestIssuer::sendNextRequest()
wait(beginResp);
}
tlm::tlm_generic_payload& payload = memoryManager.allocate(request.length);
payload.acquire();
payload.set_address(request.address);
payload.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
payload.set_dmi_allowed(false);
payload.set_byte_enable_length(0);
payload.set_data_length(request.length);
payload.set_streaming_width(request.length);
payload.set_command(request.command == Request::Command::Read ? tlm::TLM_READ_COMMAND
tlm::tlm_generic_payload* payload = memoryManager.allocate(request.length);
payload->acquire();
payload->set_address(request.address);
payload->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
payload->set_dmi_allowed(false);
payload->set_byte_enable_length(0);
payload->set_data_length(request.length);
payload->set_streaming_width(request.length);
payload->set_command(request.command == Request::Command::Read ? tlm::TLM_READ_COMMAND
: tlm::TLM_WRITE_COMMAND);
std::copy(request.data.cbegin(), request.data.cend(), payload.get_data_ptr());
std::copy(request.data.cbegin(), request.data.cend(), payload->get_data_ptr());
tlm::tlm_phase phase = tlm::BEGIN_REQ;
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
iSocket->nb_transport_fw(payload, phase, delay);
iSocket->nb_transport_fw(*payload, phase, delay);
requestInProgress = true;
if (request.command == Request::Command::Read)

8
src/simulator/simulator/request/RequestIssuer.h
View File

@@ -35,9 +35,9 @@
#pragma once
#include "Request.h"
#include "RequestProducer.h"
#include "simulator/MemoryManager.h"
#include <DRAMSys/common/MemoryManager.h>
#include <memory>
#include <systemc>
@@ -54,7 +54,7 @@ public:
RequestIssuer(sc_core::sc_module_name const& name,
std::unique_ptr<RequestProducer> producer,
MemoryManager& memoryManager,
DRAMSys::MemoryManager& memoryManager,
sc_core::sc_time interfaceClk,
std::optional<unsigned int> maxPendingReadRequests,
std::optional<unsigned int> maxPendingWriteRequests,
@@ -85,7 +85,7 @@ private:
std::unique_ptr<RequestProducer> producer;
tlm_utils::peq_with_cb_and_phase<RequestIssuer> payloadEventQueue;
MemoryManager& memoryManager;
DRAMSys::MemoryManager& memoryManager;
sc_core::sc_time interfaceClk;

36
tests/tests_simulator/cache/ListInitiator.cpp vendored
View File

@@ -43,7 +43,7 @@
#include <tlm>
#include <utility>
ListInitiator::ListInitiator(const sc_core::sc_module_name& name, MemoryManager& memoryManager) :
ListInitiator::ListInitiator(const sc_core::sc_module_name& name, DRAMSys::MemoryManager& memoryManager) :
sc_core::sc_module(name),
iSocket("iSocket"),
peq(this, &ListInitiator::peqCallback),
@@ -64,30 +64,30 @@ void ListInitiator::process()
? tlm::TLM_WRITE_COMMAND
: tlm::TLM_READ_COMMAND;
auto& trans = memoryManager.allocate(testTransactionData.dataLength);
trans.acquire();
auto* trans = memoryManager.allocate(testTransactionData.dataLength);
trans->acquire();
TestExtension* ext = new TestExtension(testTransactionData);
trans.set_auto_extension(ext);
trans->set_auto_extension(ext);
trans.set_command(command);
trans.set_address(testTransactionData.address);
trans.set_data_length(testTransactionData.dataLength);
trans.set_streaming_width(testTransactionData.dataLength);
trans.set_byte_enable_ptr(nullptr);
trans.set_dmi_allowed(false);
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
trans->set_command(command);
trans->set_address(testTransactionData.address);
trans->set_data_length(testTransactionData.dataLength);
trans->set_streaming_width(testTransactionData.dataLength);
trans->set_byte_enable_ptr(nullptr);
trans->set_dmi_allowed(false);
trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
if (trans.is_write())
if (trans->is_write())
std::memcpy(
trans.get_data_ptr(), &testTransactionData.data, testTransactionData.dataLength);
trans->get_data_ptr(), &testTransactionData.data, testTransactionData.dataLength);
if (requestInProgress != nullptr)
{
wait(endRequest);
}
requestInProgress = &trans;
requestInProgress = trans;
tlm::tlm_phase phase = tlm::BEGIN_REQ;
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
@@ -99,17 +99,17 @@ void ListInitiator::process()
<< "0x" << std::setfill('0') << std::setw(8) << std::hex
<< testTransactionData.data << "(nb_transport) \033[0m" << std::endl;
tlm::tlm_sync_enum status = iSocket->nb_transport_fw(trans, phase, delay);
tlm::tlm_sync_enum status = iSocket->nb_transport_fw(*trans, phase, delay);
if (status == tlm::TLM_UPDATED)
{
peq.notify(trans, phase, delay);
peq.notify(*trans, phase, delay);
}
else if (status == tlm::TLM_COMPLETED)
{
requestInProgress = nullptr;
checkTransaction(trans);
trans.release();
checkTransaction(*trans);
trans->release();
}
}
}

6
tests/tests_simulator/cache/ListInitiator.h vendored
View File

@@ -33,7 +33,7 @@
* Derek Christ
*/
#include "simulator/MemoryManager.h"
#include <DRAMSys/common/MemoryManager.h>
#include <tlm_utils/peq_with_cb_and_phase.h>
#include <tlm_utils/simple_initiator_socket.h>
@@ -44,7 +44,7 @@ public:
tlm_utils::simple_initiator_socket<ListInitiator> iSocket;
SC_HAS_PROCESS(ListInitiator);
ListInitiator(const sc_core::sc_module_name& name, MemoryManager& memoryManager);
ListInitiator(const sc_core::sc_module_name& name, DRAMSys::MemoryManager& memoryManager);
struct TestTransactionData
{
@@ -102,5 +102,5 @@ private:
sc_core::sc_event endRequest;
tlm_utils::peq_with_cb_and_phase<ListInitiator> peq;
tlm::tlm_generic_payload* requestInProgress = nullptr;
MemoryManager& memoryManager;
DRAMSys::MemoryManager& memoryManager;
};

4
tests/tests_simulator/cache/tests_cache.cpp vendored
View File

@@ -37,7 +37,7 @@
#include "TargetMemory.h"
#include <simulator/Cache.h>
#include <simulator/MemoryManager.h>
#include <DRAMSys/common/MemoryManager.h>
#include <gtest/gtest.h>
@@ -72,7 +72,7 @@ protected:
cache.iSocket.bind(target.tSocket);
}
MemoryManager memoryManager;
DRAMSys::MemoryManager memoryManager;
ListInitiator initiator;
TargetMemory target;
Cache cache;