Ayaz Akram 00719e4257 arch-riscv: add pma/pmp checks during page table walks ...

This change adds pma/pmp checks when page table entries
are accessed by hardware page table walker.

Change-Id: I161aad514bb7421e61a8c56af088c73969837704
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46279
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2021-06-24 04:49:45 +00:00

..

bare_metal

base: Rename Loader namespace as loader

2021-05-29 11:13:49 +00:00

insts

base: Rename Loader namespace as loader

2021-05-29 11:13:49 +00:00

isa

base: Rename Loader namespace as loader

2021-05-29 11:13:49 +00:00

linux

base: Rename Loader namespace as loader

2021-05-29 11:13:49 +00:00

regs

arch-riscv: Pull non-public content out of arch/registers.hh.

2021-04-25 05:43:44 +00:00

decoder.cc

arch,cpu: Make the decoder width a property of the decoder.

2021-05-26 00:31:54 +00:00

decoder.hh

arch,cpu: Rename DecodeCache namespace as decode_cache

2021-05-26 23:08:21 +00:00

faults.cc

arch-riscv: Pull non-public content out of arch/registers.hh.

2021-04-25 05:43:44 +00:00

faults.hh

arch-riscv: Pull non-public content out of arch/registers.hh.

2021-04-25 05:43:44 +00:00

fp_inst.hh

arch-riscv: When an inst generates a fault, return it immediately.

2021-05-20 23:42:13 +00:00

idle_event.cc

arch,cpu,sim: Eliminate the now empty kernel statistics classes.

2020-06-17 19:54:41 +00:00

idle_event.hh

riscv: Delete authors lists from riscv files.

2020-02-18 03:36:09 +00:00

interrupts.hh

arch-riscv: Pull non-public content out of arch/registers.hh.

2021-04-25 05:43:44 +00:00

isa.cc

misc: Replace M5_VAR_USED with GEM5_VAR_USED.

2021-05-11 20:16:31 +00:00

isa.hh

arch-riscv: Pull non-public content out of arch/registers.hh.

2021-04-25 05:43:44 +00:00

locked_mem.cc

riscv: fix AMO, LR and SC instructions

2019-02-08 15:27:04 +00:00

locked_mem.hh

arch-riscv: Pull non-public content out of arch/registers.hh.

2021-04-25 05:43:44 +00:00

mmu.hh

arch-riscv: Add riscv pmp support

2021-04-05 04:18:12 +00:00

page_size.hh

arch,dev,gpu-compute,sim: Rename isa_traits.hh page_size.hh.

2021-03-30 10:17:48 +00:00

pagetable_walker.cc

arch-riscv: add pma/pmp checks during page table walks

2021-06-24 04:49:45 +00:00

pagetable_walker.hh

arch-riscv: Add riscv pmp support

2021-04-05 04:18:12 +00:00

pagetable.cc

arch,dev,gpu-compute,sim: Rename isa_traits.hh page_size.hh.

2021-03-30 10:17:48 +00:00

pagetable.hh

misc: Fix a few accidental transitive includes.

2020-10-21 22:56:14 +00:00

pcstate.hh

arch,base,cpu: Split arch/pcstate.hh out of arch/types.hh.

2021-05-28 23:41:03 +00:00

pma_checker.cc

arch-riscv: Fix Clint and SATP write side effects

2021-03-24 02:48:14 +00:00

pma_checker.hh

arch-riscv: Fixed CPU switching and PLIC issue with MinorCPU

2021-03-13 08:06:29 +00:00

PMAChecker.py

arch-riscv: Added PMA support for RiscvTLB

2021-02-23 03:43:47 +00:00

pmp.cc

arch-riscv: add pma/pmp checks during page table walks

2021-06-24 04:49:45 +00:00

pmp.hh

arch-riscv: add pma/pmp checks during page table walks

2021-06-24 04:49:45 +00:00

PMP.py

arch-riscv: Add riscv pmp support

2021-04-05 04:18:12 +00:00

pra_constants.hh

riscv: Delete authors lists from riscv files.

2020-02-18 03:36:09 +00:00

process.cc

base: Rename Loader namespace as loader

2021-05-29 11:13:49 +00:00

process.hh

base: Rename Loader namespace as loader

2021-05-29 11:13:49 +00:00

reg_abi.cc

riscv: Export the system call ABI for use in gem5 ops.

2021-01-26 12:12:23 +00:00

reg_abi.hh

riscv: Export the system call ABI for use in gem5 ops.

2021-01-26 12:12:23 +00:00

remote_gdb.cc

arch,base,sim: Construct the GDB stub with no threads.

2021-05-28 07:56:19 +00:00

remote_gdb.hh

arch,base,sim: Construct the GDB stub with no threads.

2021-05-28 07:56:19 +00:00

RiscvFsWorkload.py

arch-riscv: Added DTB Generation Functionality to RISC-V FS

2021-03-24 02:47:30 +00:00

RiscvInterrupts.py

riscv: Delete authors lists from riscv files.

2020-02-18 03:36:09 +00:00

RiscvISA.py

riscv: Delete authors lists from riscv files.

2020-02-18 03:36:09 +00:00

RiscvMMU.py

arch-riscv: Add riscv pmp support

2021-04-05 04:18:12 +00:00

RiscvSeWorkload.py

riscv: Implement an SE workload for Linux.

2020-10-29 01:34:41 +00:00

RiscvTLB.py

arch-riscv: Add riscv pmp support

2021-04-05 04:18:12 +00:00

SConscript

arch-riscv, arch-x86: Define unique PageTableWalker flag

2021-04-30 09:28:00 +00:00

SConsopts

riscv: Delete authors lists from riscv files.

2020-02-18 03:36:09 +00:00

se_workload.hh

base: Rename Loader namespace as loader

2021-05-29 11:13:49 +00:00

stacktrace.hh

arch,cpu: Consolidate most of the StackTrace classes into a base class.

2020-07-11 00:24:38 +00:00

tlb.cc

arch-riscv: Update the way a valid virtual address is computed

2021-06-08 07:17:09 +00:00

tlb.hh

base-stats,misc: Rename Stats namespace as statistics

2021-05-29 11:13:49 +00:00

types.hh

arch,base,cpu: Split arch/pcstate.hh out of arch/types.hh.

2021-05-28 23:41:03 +00:00

utility.hh

arch,cpu: Get rid of is*Reg() methods in RegId.

2021-05-10 20:03:38 +00:00

vecregs.hh

arch: Delete a few unused vector register types/constants.

2021-05-08 19:37:26 +00:00