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arch,base,cpu: Split arch/pcstate.hh out of arch/types.hh.

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The only thing brought in by arch/types.hh is TheISA::PCState. Instead
of having the other types around where they could be used accidentally,
and to make it more obvious what's being exported, this change splits
PCState out into a new switching header called arch/pcstate.hh. The
original arch/types.hh is no longer a switching header, and includes
pcstate.hh.

Change-Id: I8dfd298349e4565f316f7b9a028703289ada6010
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40177
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-01-29 23:01:31 -08:00
parent 1cf41d4c54
commit 8ab9e72804
38 changed files with 776 additions and 496 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/SConscript
View File

@@ -61,7 +61,7 @@ env.SwitchingHeaders(
isa.hh
locked_mem.hh
page_size.hh
types.hh
pcstate.hh
vecregs.hh
'''),
env.subst('${TARGET_ISA}'))

421
src/arch/arm/pcstate.hh Normal file
View File

@@ -0,0 +1,421 @@
/*
* Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_ARM_PCSTATE_HH__
#define __ARCH_ARM_PCSTATE_HH__
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
#include "base/types.hh"
#include "debug/Decoder.hh"
namespace ArmISA
{
BitUnion8(ITSTATE)
/* Note that the split (cond, mask) below is not as in ARM ARM.
* But it is more convenient for simulation. The condition
* is always the concatenation of the top 3 bits and the next bit,
* which applies when one of the bottom 4 bits is set.
* Refer to predecoder.cc for the use case.
*/
Bitfield<7, 4> cond;
Bitfield<3, 0> mask;
// Bitfields for moving to/from CPSR
Bitfield<7, 2> top6;
Bitfield<1, 0> bottom2;
EndBitUnion(ITSTATE)
class PCState : public GenericISA::UPCState<4>
{
protected:
typedef GenericISA::UPCState<4> Base;
enum FlagBits
{
ThumbBit = (1 << 0),
JazelleBit = (1 << 1),
AArch64Bit = (1 << 2)
};
uint8_t flags;
uint8_t nextFlags;
uint8_t _itstate;
uint8_t _nextItstate;
uint8_t _size;
bool _illegalExec;
// Software Step flags
bool _debugStep;
bool _stepped;
public:
PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0),
_size(0), _illegalExec(false), _debugStep(false),
_stepped(false)
{}
void
set(Addr val)
{
Base::set(val);
npc(val + (thumb() ? 2 : 4));
}
PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
_nextItstate(0), _size(0), _illegalExec(false),
_debugStep(false), _stepped(false)
{ set(val); }
bool
illegalExec() const
{
return _illegalExec;
}
void
illegalExec(bool val)
{
_illegalExec = val;
}
bool
debugStep() const
{
return _debugStep;
}
void
debugStep(bool val)
{
_debugStep = val;
}
bool
stepped() const
{
return _stepped;
}
void
stepped(bool val)
{
_stepped = val;
}
bool
thumb() const
{
return flags & ThumbBit;
}
void
thumb(bool val)
{
if (val)
flags |= ThumbBit;
else
flags &= ~ThumbBit;
}
bool
nextThumb() const
{
return nextFlags & ThumbBit;
}
void
nextThumb(bool val)
{
if (val)
nextFlags |= ThumbBit;
else
nextFlags &= ~ThumbBit;
}
void size(uint8_t s) { _size = s; }
uint8_t size() const { return _size; }
bool
branching() const
{
return ((this->pc() + this->size()) != this->npc());
}
bool
jazelle() const
{
return flags & JazelleBit;
}
void
jazelle(bool val)
{
if (val)
flags |= JazelleBit;
else
flags &= ~JazelleBit;
}
bool
nextJazelle() const
{
return nextFlags & JazelleBit;
}
void
nextJazelle(bool val)
{
if (val)
nextFlags |= JazelleBit;
else
nextFlags &= ~JazelleBit;
}
bool
aarch64() const
{
return flags & AArch64Bit;
}
void
aarch64(bool val)
{
if (val)
flags |= AArch64Bit;
else
flags &= ~AArch64Bit;
}
bool
nextAArch64() const
{
return nextFlags & AArch64Bit;
}
void
nextAArch64(bool val)
{
if (val)
nextFlags |= AArch64Bit;
else
nextFlags &= ~AArch64Bit;
}
uint8_t
itstate() const
{
return _itstate;
}
void
itstate(uint8_t value)
{
_itstate = value;
}
uint8_t
nextItstate() const
{
return _nextItstate;
}
void
nextItstate(uint8_t value)
{
_nextItstate = value;
}
void
advance()
{
Base::advance();
flags = nextFlags;
npc(pc() + (thumb() ? 2 : 4));
if (_nextItstate) {
_itstate = _nextItstate;
_nextItstate = 0;
} else if (_itstate) {
ITSTATE it = _itstate;
uint8_t cond_mask = it.mask;
uint8_t thumb_cond = it.cond;
DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n",
thumb_cond, cond_mask);
cond_mask <<= 1;
uint8_t new_bit = bits(cond_mask, 4);
cond_mask &= mask(4);
if (cond_mask == 0)
thumb_cond = 0;
else
replaceBits(thumb_cond, 0, new_bit);
DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n",
thumb_cond, cond_mask);
it.mask = cond_mask;
it.cond = thumb_cond;
_itstate = it;
}
}
void
uEnd()
{
advance();
upc(0);
nupc(1);
}
Addr
instPC() const
{
return pc() + (thumb() ? 4 : 8);
}
void
instNPC(Addr val)
{
// @todo: review this when AArch32/64 interprocessing is
// supported
if (aarch64())
npc(val); // AArch64 doesn't force PC alignment, a PC
// Alignment Fault can be raised instead
else
npc(val &~ mask(nextThumb() ? 1 : 2));
}
Addr
instNPC() const
{
return npc();
}
// Perform an interworking branch.
void
instIWNPC(Addr val)
{
bool thumbEE = (thumb() && jazelle());
Addr newPC = val;
if (thumbEE) {
if (bits(newPC, 0)) {
newPC = newPC & ~mask(1);
} // else we have a bad interworking address; do not call
// panic() since the instruction could be executed
// speculatively
} else {
if (bits(newPC, 0)) {
nextThumb(true);
newPC = newPC & ~mask(1);
} else if (!bits(newPC, 1)) {
nextThumb(false);
} else {
// This state is UNPREDICTABLE in the ARM architecture
// The easy thing to do is just mask off the bit and
// stay in the current mode, so we'll do that.
newPC &= ~mask(2);
}
}
npc(newPC);
}
// Perform an interworking branch in ARM mode, a regular branch
// otherwise.
void
instAIWNPC(Addr val)
{
if (!thumb() && !jazelle())
instIWNPC(val);
else
instNPC(val);
}
bool
operator == (const PCState &opc) const
{
return Base::operator == (opc) &&
flags == opc.flags && nextFlags == opc.nextFlags &&
_itstate == opc._itstate &&
_nextItstate == opc._nextItstate &&
_illegalExec == opc._illegalExec &&
_debugStep == opc._debugStep &&
_stepped == opc._stepped;
}
bool
operator != (const PCState &opc) const
{
return !(*this == opc);
}
void
serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(flags);
SERIALIZE_SCALAR(_size);
SERIALIZE_SCALAR(nextFlags);
SERIALIZE_SCALAR(_itstate);
SERIALIZE_SCALAR(_nextItstate);
SERIALIZE_SCALAR(_illegalExec);
SERIALIZE_SCALAR(_debugStep);
SERIALIZE_SCALAR(_stepped);
}
void
unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(flags);
UNSERIALIZE_SCALAR(_size);
UNSERIALIZE_SCALAR(nextFlags);
UNSERIALIZE_SCALAR(_itstate);
UNSERIALIZE_SCALAR(_nextItstate);
UNSERIALIZE_SCALAR(_illegalExec);
UNSERIALIZE_SCALAR(_debugStep);
UNSERIALIZE_SCALAR(_stepped);
}
};
} // namespace ArmISA
#endif

2
src/arch/arm/regs/int.hh
View File

@@ -44,6 +44,8 @@
#define __ARCH_ARM_REGS_INT_HH__
#include "arch/arm/types.hh"
#include "base/logging.hh"
#include "sim/core.hh"
namespace ArmISA
{

373
src/arch/arm/types.hh
View File

@@ -41,11 +41,11 @@
#ifndef __ARCH_ARM_TYPES_HH__
#define __ARCH_ARM_TYPES_HH__
#include "arch/generic/types.hh"
#include <cstdint>
#include "arch/arm/pcstate.hh"
#include "base/bitunion.hh"
#include "base/logging.hh"
#include "base/types.hh"
#include "debug/Decoder.hh"
namespace ArmISA
{
@@ -53,20 +53,6 @@ namespace ArmISA
typedef uint16_t vmid_t;
BitUnion8(ITSTATE)
/* Note that the split (cond, mask) below is not as in ARM ARM.
* But it is more convenient for simulation. The condition
* is always the concatenation of the top 3 bits and the next bit,
* which applies when one of the bottom 4 bits is set.
* Refer to predecoder.cc for the use case.
*/
Bitfield<7, 4> cond;
Bitfield<3, 0> mask;
// Bitfields for moving to/from CPSR
Bitfield<7, 2> top6;
Bitfield<1, 0> bottom2;
EndBitUnion(ITSTATE)
BitUnion64(ExtMachInst)
// Decoder state
Bitfield<63, 62> decoderFault; // See DecoderFault
@@ -213,359 +199,6 @@ namespace ArmISA
Bitfield<11, 8> ltcoproc;
EndBitUnion(ExtMachInst)
class PCState : public GenericISA::UPCState<4>
{
protected:
typedef GenericISA::UPCState<4> Base;
enum FlagBits
{
ThumbBit = (1 << 0),
JazelleBit = (1 << 1),
AArch64Bit = (1 << 2)
};
uint8_t flags;
uint8_t nextFlags;
uint8_t _itstate;
uint8_t _nextItstate;
uint8_t _size;
bool _illegalExec;
// Software Step flags
bool _debugStep;
bool _stepped;
public:
PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0),
_size(0), _illegalExec(false), _debugStep(false),
_stepped(false)
{}
void
set(Addr val)
{
Base::set(val);
npc(val + (thumb() ? 2 : 4));
}
PCState(Addr val) : flags(0), nextFlags(0), _itstate(0),
_nextItstate(0), _size(0), _illegalExec(false),
_debugStep(false), _stepped(false)
{ set(val); }
bool
illegalExec() const
{
return _illegalExec;
}
void
illegalExec(bool val)
{
_illegalExec = val;
}
bool
debugStep() const
{
return _debugStep;
}
void
debugStep(bool val)
{
_debugStep = val;
}
bool
stepped() const
{
return _stepped;
}
void
stepped(bool val)
{
_stepped = val;
}
bool
thumb() const
{
return flags & ThumbBit;
}
void
thumb(bool val)
{
if (val)
flags |= ThumbBit;
else
flags &= ~ThumbBit;
}
bool
nextThumb() const
{
return nextFlags & ThumbBit;
}
void
nextThumb(bool val)
{
if (val)
nextFlags |= ThumbBit;
else
nextFlags &= ~ThumbBit;
}
void size(uint8_t s) { _size = s; }
uint8_t size() const { return _size; }
bool
branching() const
{
return ((this->pc() + this->size()) != this->npc());
}
bool
jazelle() const
{
return flags & JazelleBit;
}
void
jazelle(bool val)
{
if (val)
flags |= JazelleBit;
else
flags &= ~JazelleBit;
}
bool
nextJazelle() const
{
return nextFlags & JazelleBit;
}
void
nextJazelle(bool val)
{
if (val)
nextFlags |= JazelleBit;
else
nextFlags &= ~JazelleBit;
}
bool
aarch64() const
{
return flags & AArch64Bit;
}
void
aarch64(bool val)
{
if (val)
flags |= AArch64Bit;
else
flags &= ~AArch64Bit;
}
bool
nextAArch64() const
{
return nextFlags & AArch64Bit;
}
void
nextAArch64(bool val)
{
if (val)
nextFlags |= AArch64Bit;
else
nextFlags &= ~AArch64Bit;
}
uint8_t
itstate() const
{
return _itstate;
}
void
itstate(uint8_t value)
{
_itstate = value;
}
uint8_t
nextItstate() const
{
return _nextItstate;
}
void
nextItstate(uint8_t value)
{
_nextItstate = value;
}
void
advance()
{
Base::advance();
flags = nextFlags;
npc(pc() + (thumb() ? 2 : 4));
if (_nextItstate) {
_itstate = _nextItstate;
_nextItstate = 0;
} else if (_itstate) {
ITSTATE it = _itstate;
uint8_t cond_mask = it.mask;
uint8_t thumb_cond = it.cond;
DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n",
thumb_cond, cond_mask);
cond_mask <<= 1;
uint8_t new_bit = bits(cond_mask, 4);
cond_mask &= mask(4);
if (cond_mask == 0)
thumb_cond = 0;
else
replaceBits(thumb_cond, 0, new_bit);
DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n",
thumb_cond, cond_mask);
it.mask = cond_mask;
it.cond = thumb_cond;
_itstate = it;
}
}
void
uEnd()
{
advance();
upc(0);
nupc(1);
}
Addr
instPC() const
{
return pc() + (thumb() ? 4 : 8);
}
void
instNPC(Addr val)
{
// @todo: review this when AArch32/64 interprocessing is
// supported
if (aarch64())
npc(val); // AArch64 doesn't force PC alignment, a PC
// Alignment Fault can be raised instead
else
npc(val &~ mask(nextThumb() ? 1 : 2));
}
Addr
instNPC() const
{
return npc();
}
// Perform an interworking branch.
void
instIWNPC(Addr val)
{
bool thumbEE = (thumb() && jazelle());
Addr newPC = val;
if (thumbEE) {
if (bits(newPC, 0)) {
newPC = newPC & ~mask(1);
} // else we have a bad interworking address; do not call
// panic() since the instruction could be executed
// speculatively
} else {
if (bits(newPC, 0)) {
nextThumb(true);
newPC = newPC & ~mask(1);
} else if (!bits(newPC, 1)) {
nextThumb(false);
} else {
// This state is UNPREDICTABLE in the ARM architecture
// The easy thing to do is just mask off the bit and
// stay in the current mode, so we'll do that.
newPC &= ~mask(2);
}
}
npc(newPC);
}
// Perform an interworking branch in ARM mode, a regular branch
// otherwise.
void
instAIWNPC(Addr val)
{
if (!thumb() && !jazelle())
instIWNPC(val);
else
instNPC(val);
}
bool
operator == (const PCState &opc) const
{
return Base::operator == (opc) &&
flags == opc.flags && nextFlags == opc.nextFlags &&
_itstate == opc._itstate &&
_nextItstate == opc._nextItstate &&
_illegalExec == opc._illegalExec &&
_debugStep == opc._debugStep &&
_stepped == opc._stepped;
}
bool
operator != (const PCState &opc) const
{
return !(*this == opc);
}
void
serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(flags);
SERIALIZE_SCALAR(_size);
SERIALIZE_SCALAR(nextFlags);
SERIALIZE_SCALAR(_itstate);
SERIALIZE_SCALAR(_nextItstate);
SERIALIZE_SCALAR(_illegalExec);
SERIALIZE_SCALAR(_debugStep);
SERIALIZE_SCALAR(_stepped);
}
void
unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(flags);
UNSERIALIZE_SCALAR(_size);
UNSERIALIZE_SCALAR(nextFlags);
UNSERIALIZE_SCALAR(_itstate);
UNSERIALIZE_SCALAR(_nextItstate);
UNSERIALIZE_SCALAR(_illegalExec);
UNSERIALIZE_SCALAR(_debugStep);
UNSERIALIZE_SCALAR(_stepped);
}
};
// Shift types for ARM instructions
enum ArmShiftType
{

40
src/arch/mips/pcstate.hh Normal file
View File

@@ -0,0 +1,40 @@
/*
* Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_MIPS_PCSTATE_HH__
#define __ARCH_MIPS_PCSTATE_HH__
#include "arch/generic/types.hh"
namespace MipsISA
{
typedef GenericISA::DelaySlotPCState<4> PCState;
} // namespace MipsISA
#endif

7
src/arch/mips/types.hh
View File

@@ -29,8 +29,9 @@
#ifndef __ARCH_MIPS_TYPES_HH__
#define __ARCH_MIPS_TYPES_HH__
#include "arch/generic/types.hh"
#include "base/types.hh"
#include <cstdint>
#include "arch/mips/pcstate.hh"
namespace MipsISA
{
@@ -38,8 +39,6 @@ namespace MipsISA
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
typedef GenericISA::DelaySlotPCState<4> PCState;
//used in FP convert & round function
enum ConvertType
{

0
src/arch/null/types.hh → src/arch/null/pcstate.hh
View File

3
src/arch/null/vecregs.hh
View File

@@ -38,6 +38,9 @@
#ifndef __ARCH_NULL_VECREGS_HH__
#define __ARCH_NULL_VECREGS_HH__
#include <cstdint>
#include "arch/generic/types.hh"
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"

1
src/arch/power/insts/static_inst.hh
View File

@@ -29,6 +29,7 @@
#ifndef __ARCH_POWER_INSTS_STATICINST_HH__
#define __ARCH_POWER_INSTS_STATICINST_HH__
#include "arch/power/types.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"

41
src/arch/power/pcstate.hh Normal file
View File

@@ -0,0 +1,41 @@
/*
* Copyright (c) 2009 The University of Edinburgh
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_POWER_PCSTATE_HH__
#define __ARCH_POWER_PCSTATE_HH__
#include "arch/generic/types.hh"
namespace PowerISA
{
typedef GenericISA::SimplePCState<4> PCState;
}
#endif // __ARCH_POWER_PCSTATE_HH__

7
src/arch/power/types.hh
View File

@@ -29,9 +29,10 @@
#ifndef __ARCH_POWER_TYPES_HH__
#define __ARCH_POWER_TYPES_HH__
#include "arch/generic/types.hh"
#include <cstdint>
#include "arch/power/pcstate.hh"
#include "base/bitunion.hh"
#include "base/types.hh"
namespace PowerISA
{
@@ -81,8 +82,6 @@ BitUnion32(ExtMachInst)
Bitfield<19, 12> fxm;
EndBitUnion(ExtMachInst)
typedef GenericISA::SimplePCState<4> PCState;
// typedef uint64_t LargestRead;
// // Need to use 64 bits to make sure that read requests get handled properly

79
src/arch/riscv/pcstate.hh Normal file
View File

@@ -0,0 +1,79 @@
/*
* Copyright (c) 2013 ARM Limited
* Copyright (c) 2014 Sven Karlsson
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2017 The University of Virginia
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_RISCV_PCSTATE_HH__
#define __ARCH_RISCV_PCSTATE_HH__
#include "arch/generic/types.hh"
namespace RiscvISA
{
class PCState : public GenericISA::UPCState<4>
{
private:
bool _compressed;
bool _rv32;
public:
PCState() : UPCState() { _compressed = false; _rv32 = false; }
PCState(Addr val) : UPCState(val) { _compressed = false; _rv32 = false; }
void compressed(bool c) { _compressed = c; }
bool compressed() { return _compressed; }
void rv32(bool val) { _rv32 = val; }
bool rv32() const { return _rv32; }
bool
branching() const
{
if (_compressed) {
return npc() != pc() + 2 || nupc() != upc() + 1;
} else {
return npc() != pc() + 4 || nupc() != upc() + 1;
}
}
};
}
#endif // __ARCH_RISCV_PCSTATE_HH__

31
src/arch/riscv/types.hh
View File

@@ -42,7 +42,7 @@
#ifndef __ARCH_RISCV_TYPES_HH__
#define __ARCH_RISCV_TYPES_HH__
#include "arch/generic/types.hh"
#include "arch/riscv/pcstate.hh"
namespace RiscvISA
{
@@ -50,35 +50,6 @@ namespace RiscvISA
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
class PCState : public GenericISA::UPCState<4>
{
private:
bool _compressed;
bool _rv32;
public:
PCState() : UPCState() { _compressed = false; _rv32 = false; }
PCState(Addr val) : UPCState(val) { _compressed = false; _rv32 = false; }
void compressed(bool c) { _compressed = c; }
bool compressed() { return _compressed; }
void rv32(bool val) { _rv32 = val; }
bool rv32() const { return _rv32; }
bool
branching() const
{
if (_compressed) {
return npc() != pc() + sizeof(MachInst)/2 ||
nupc() != upc() + 1;
} else {
return npc() != pc() + sizeof(MachInst) ||
nupc() != upc() + 1;
}
}
};
}
#endif // __ARCH_RISCV_TYPES_HH__

1
src/arch/sparc/insts/static_inst.hh
View File

@@ -32,6 +32,7 @@
#include <cstdint>
#include "arch/sparc/types.hh"
#include "base/trace.hh"
#include "cpu/exec_context.hh"
#include "cpu/static_inst.hh"

41
src/arch/sparc/pcstate.hh Normal file
View File

@@ -0,0 +1,41 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_SPARC_PCSTATE_HH__
#define __ARCH_SPARC_PCSTATE_HH__
#include "arch/generic/types.hh"
namespace SparcISA
{
typedef GenericISA::DelaySlotUPCState<4> PCState;
}
#endif

1
src/arch/sparc/remote_gdb.cc
View File

@@ -126,6 +126,7 @@
#include "arch/sparc/regs/int.hh"
#include "arch/sparc/regs/misc.hh"
#include "arch/sparc/types.hh"
#include "base/intmath.hh"
#include "base/remote_gdb.hh"
#include "base/socket.hh"

1
src/arch/sparc/tlb.cc
View File

@@ -35,6 +35,7 @@
#include "arch/sparc/interrupts.hh"
#include "arch/sparc/mmu.hh"
#include "arch/sparc/regs/misc.hh"
#include "arch/sparc/types.hh"
#include "base/bitfield.hh"
#include "base/compiler.hh"
#include "base/trace.hh"

4
src/arch/sparc/types.hh
View File

@@ -29,7 +29,7 @@
#ifndef __ARCH_SPARC_TYPES_HH__
#define __ARCH_SPARC_TYPES_HH__
#include "arch/generic/types.hh"
#include "arch/sparc/pcstate.hh"
#include "base/types.hh"
namespace SparcISA
@@ -38,8 +38,6 @@ namespace SparcISA
typedef uint32_t MachInst;
typedef uint64_t ExtMachInst;
typedef GenericISA::DelaySlotUPCState<4> PCState;
}
#endif

1
src/arch/x86/insts/static_inst.hh
View File

@@ -38,6 +38,7 @@
#ifndef __ARCH_X86_INSTS_STATICINST_HH__
#define __ARCH_X86_INSTS_STATICINST_HH__
#include "arch/x86/types.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "debug/X86.hh"

113
src/arch/x86/pcstate.hh Normal file
View File

@@ -0,0 +1,113 @@
/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCH_X86_PCSTATE_HH__
#define __ARCH_X86_PCSTATE_HH__
#include "arch/generic/types.hh"
#include "sim/serialize.hh"
namespace X86ISA
{
class PCState : public GenericISA::UPCState<8>
{
protected:
typedef GenericISA::UPCState<8> Base;
uint8_t _size;
public:
void
set(Addr val)
{
Base::set(val);
_size = 0;
}
PCState() {}
PCState(Addr val) { set(val); }
void
setNPC(Addr val)
{
Base::setNPC(val);
_size = 0;
}
uint8_t size() const { return _size; }
void size(uint8_t newSize) { _size = newSize; }
bool
branching() const
{
return (this->npc() != this->pc() + size()) ||
(this->nupc() != this->upc() + 1);
}
void
advance()
{
Base::advance();
_size = 0;
}
void
uEnd()
{
Base::uEnd();
_size = 0;
}
void
serialize(CheckpointOut &cp) const
{
Base::serialize(cp);
SERIALIZE_SCALAR(_size);
}
void
unserialize(CheckpointIn &cp)
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_size);
}
};
}
#endif // __ARCH_X86_PCSTATE_HH__

70
src/arch/x86/types.hh
View File

@@ -38,13 +38,13 @@
#ifndef __ARCH_X86_TYPES_HH__
#define __ARCH_X86_TYPES_HH__
#include <cstdint>
#include <functional>
#include <iostream>
#include "arch/generic/types.hh"
#include "arch/x86/pcstate.hh"
#include "base/bitunion.hh"
#include "base/cprintf.hh"
#include "base/types.hh"
#include "sim/serialize.hh"
namespace X86ISA
{
@@ -287,70 +287,6 @@ operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
return true;
}
class PCState : public GenericISA::UPCState<8>
{
protected:
typedef GenericISA::UPCState<8> Base;
uint8_t _size;
public:
void
set(Addr val)
{
Base::set(val);
_size = 0;
}
PCState() {}
PCState(Addr val) { set(val); }
void
setNPC(Addr val)
{
Base::setNPC(val);
_size = 0;
}
uint8_t size() const { return _size; }
void size(uint8_t newSize) { _size = newSize; }
bool
branching() const
{
return (this->npc() != this->pc() + size()) ||
(this->nupc() != this->upc() + 1);
}
void
advance()
{
Base::advance();
_size = 0;
}
void
uEnd()
{
Base::uEnd();
_size = 0;
}
void
serialize(CheckpointOut &cp) const
{
Base::serialize(cp);
SERIALIZE_SCALAR(_size);
}
void
unserialize(CheckpointIn &cp)
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_size);
}
};
}
namespace std

2
src/base/remote_gdb.hh
View File

@@ -50,7 +50,7 @@
#include <string>
#include <vector>
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "base/cprintf.hh"
#include "base/pollevent.hh"
#include "base/socket.hh"

2
src/cpu/checker/cpu.hh
View File

@@ -46,7 +46,7 @@
#include <map>
#include <queue>
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "base/statistics.hh"
#include "cpu/base.hh"
#include "cpu/exec_context.hh"

2
src/cpu/checker/thread_context.hh
View File

@@ -42,7 +42,7 @@
#ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__
#define __CPU_CHECKER_THREAD_CONTEXT_HH__
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "config/the_isa.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/simple_thread.hh"

2
src/cpu/inst_pb_trace.hh
View File

@@ -38,7 +38,7 @@
#ifndef __CPU_INST_PB_TRACE_HH__
#define __CPU_INST_PB_TRACE_HH__
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst_fwd.hh"

2
src/cpu/o3/comm.hh
View File

@@ -44,7 +44,7 @@
#include <vector>
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/dyn_inst_ptr.hh"

2
src/cpu/o3/cpu.hh
View File

@@ -50,7 +50,7 @@
#include <vector>
#include "arch/generic/types.hh"
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
#include "cpu/o3/comm.hh"

2
src/cpu/o3/decode.cc
View File

@@ -40,7 +40,7 @@
#include "cpu/o3/decode.hh"
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"

1
src/cpu/o3/regfile.hh
View File

@@ -45,6 +45,7 @@
#include <vector>
#include "arch/generic/isa.hh"
#include "arch/pcstate.hh"
#include "arch/vecregs.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"

2
src/cpu/o3/rename_map.hh
View File

@@ -47,8 +47,6 @@
#include <vector>
#include "arch/generic/isa.hh"
#include "arch/types.hh"
#include "config/the_isa.hh"
#include "cpu/o3/free_list.hh"
#include "cpu/o3/regfile.hh"
#include "cpu/reg_class.hh"

2
src/cpu/pred/bpred_unit.cc
View File

@@ -44,7 +44,7 @@
#include <algorithm>
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "base/compiler.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"

2
src/cpu/pred/btb.hh
View File

@@ -29,7 +29,7 @@
#ifndef __CPU_PRED_BTB_HH__
#define __CPU_PRED_BTB_HH__
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "base/logging.hh"
#include "base/types.hh"
#include "config/the_isa.hh"

2
src/cpu/pred/indirect.hh
View File

@@ -29,7 +29,7 @@
#ifndef __CPU_PRED_INDIRECT_BASE_HH__
#define __CPU_PRED_INDIRECT_BASE_HH__
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
#include "params/IndirectPredictor.hh"

2
src/cpu/pred/ras.hh
View File

@@ -31,7 +31,7 @@
#include <vector>
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "base/types.hh"
#include "config/the_isa.hh"

2
src/cpu/simple_thread.hh
View File

@@ -50,7 +50,7 @@
#include "arch/generic/mmu.hh"
#include "arch/generic/tlb.hh"
#include "arch/isa.hh"
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "arch/vecregs.hh"
#include "base/types.hh"
#include "config/the_isa.hh"

2
src/cpu/static_inst.hh
View File

@@ -47,7 +47,7 @@
#include <memory>
#include <string>
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "base/logging.hh"
#include "base/refcnt.hh"
#include "config/the_isa.hh"

2
src/cpu/thread_context.hh
View File

@@ -47,7 +47,7 @@
#include "arch/generic/htm.hh"
#include "arch/generic/isa.hh"
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "arch/vecregs.hh"
#include "base/types.hh"
#include "config/the_isa.hh"

2
src/cpu/thread_state.hh
View File

@@ -29,7 +29,7 @@
#ifndef __CPU_THREAD_STATE_HH__
#define __CPU_THREAD_STATE_HH__
#include "arch/types.hh"
#include "arch/pcstate.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"