From 8ab9e72804f0c3c10903fe29005eb130a5ffffd8 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 29 Jan 2021 23:01:31 -0800 Subject: [PATCH] arch,base,cpu: Split arch/pcstate.hh out of arch/types.hh. The only thing brought in by arch/types.hh is TheISA::PCState. Instead of having the other types around where they could be used accidentally, and to make it more obvious what's being exported, this change splits PCState out into a new switching header called arch/pcstate.hh. The original arch/types.hh is no longer a switching header, and includes pcstate.hh. Change-Id: I8dfd298349e4565f316f7b9a028703289ada6010 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40177 Tested-by: kokoro Reviewed-by: Gabe Black Maintainer: Gabe Black --- src/arch/SConscript | 2 +- src/arch/arm/pcstate.hh | 421 +++++++++++++++++++++++++ src/arch/arm/regs/int.hh | 2 + src/arch/arm/types.hh | 373 +--------------------- src/arch/mips/pcstate.hh | 40 +++ src/arch/mips/types.hh | 7 +- src/arch/null/{types.hh => pcstate.hh} | 0 src/arch/null/vecregs.hh | 3 + src/arch/power/insts/static_inst.hh | 1 + src/arch/power/pcstate.hh | 41 +++ src/arch/power/types.hh | 7 +- src/arch/riscv/pcstate.hh | 79 +++++ src/arch/riscv/types.hh | 31 +- src/arch/sparc/insts/static_inst.hh | 1 + src/arch/sparc/pcstate.hh | 41 +++ src/arch/sparc/remote_gdb.cc | 1 + src/arch/sparc/tlb.cc | 1 + src/arch/sparc/types.hh | 4 +- src/arch/x86/insts/static_inst.hh | 1 + src/arch/x86/pcstate.hh | 113 +++++++ src/arch/x86/types.hh | 70 +--- src/base/remote_gdb.hh | 2 +- src/cpu/checker/cpu.hh | 2 +- src/cpu/checker/thread_context.hh | 2 +- src/cpu/inst_pb_trace.hh | 2 +- src/cpu/o3/comm.hh | 2 +- src/cpu/o3/cpu.hh | 2 +- src/cpu/o3/decode.cc | 2 +- src/cpu/o3/regfile.hh | 1 + src/cpu/o3/rename_map.hh | 2 - src/cpu/pred/bpred_unit.cc | 2 +- src/cpu/pred/btb.hh | 2 +- src/cpu/pred/indirect.hh | 2 +- src/cpu/pred/ras.hh | 2 +- src/cpu/simple_thread.hh | 2 +- src/cpu/static_inst.hh | 2 +- src/cpu/thread_context.hh | 2 +- src/cpu/thread_state.hh | 2 +- 38 files changed, 776 insertions(+), 496 deletions(-) create mode 100644 src/arch/arm/pcstate.hh create mode 100644 src/arch/mips/pcstate.hh rename src/arch/null/{types.hh => pcstate.hh} (100%) create mode 100644 src/arch/power/pcstate.hh create mode 100644 src/arch/riscv/pcstate.hh create mode 100644 src/arch/sparc/pcstate.hh create mode 100644 src/arch/x86/pcstate.hh diff --git a/src/arch/SConscript b/src/arch/SConscript index 599e410a14..e545892819 100644 --- a/src/arch/SConscript +++ b/src/arch/SConscript @@ -61,7 +61,7 @@ env.SwitchingHeaders( isa.hh locked_mem.hh page_size.hh - types.hh + pcstate.hh vecregs.hh '''), env.subst('${TARGET_ISA}')) diff --git a/src/arch/arm/pcstate.hh b/src/arch/arm/pcstate.hh new file mode 100644 index 0000000000..f82afa2807 --- /dev/null +++ b/src/arch/arm/pcstate.hh @@ -0,0 +1,421 @@ +/* + * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Copyright (c) 2007-2008 The Florida State University + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_ARM_PCSTATE_HH__ +#define __ARCH_ARM_PCSTATE_HH__ + +#include "arch/generic/types.hh" +#include "base/bitunion.hh" +#include "base/types.hh" +#include "debug/Decoder.hh" + +namespace ArmISA +{ + +BitUnion8(ITSTATE) + /* Note that the split (cond, mask) below is not as in ARM ARM. + * But it is more convenient for simulation. The condition + * is always the concatenation of the top 3 bits and the next bit, + * which applies when one of the bottom 4 bits is set. + * Refer to predecoder.cc for the use case. + */ + Bitfield<7, 4> cond; + Bitfield<3, 0> mask; + // Bitfields for moving to/from CPSR + Bitfield<7, 2> top6; + Bitfield<1, 0> bottom2; +EndBitUnion(ITSTATE) + +class PCState : public GenericISA::UPCState<4> +{ + protected: + + typedef GenericISA::UPCState<4> Base; + + enum FlagBits + { + ThumbBit = (1 << 0), + JazelleBit = (1 << 1), + AArch64Bit = (1 << 2) + }; + + uint8_t flags; + uint8_t nextFlags; + uint8_t _itstate; + uint8_t _nextItstate; + uint8_t _size; + bool _illegalExec; + + // Software Step flags + bool _debugStep; + bool _stepped; + + public: + PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0), + _size(0), _illegalExec(false), _debugStep(false), + _stepped(false) + {} + + void + set(Addr val) + { + Base::set(val); + npc(val + (thumb() ? 2 : 4)); + } + + PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), + _nextItstate(0), _size(0), _illegalExec(false), + _debugStep(false), _stepped(false) + { set(val); } + + bool + illegalExec() const + { + return _illegalExec; + } + + void + illegalExec(bool val) + { + _illegalExec = val; + } + + bool + debugStep() const + { + return _debugStep; + } + + void + debugStep(bool val) + { + _debugStep = val; + } + + bool + stepped() const + { + return _stepped; + } + + void + stepped(bool val) + { + _stepped = val; + } + + bool + thumb() const + { + return flags & ThumbBit; + } + + void + thumb(bool val) + { + if (val) + flags |= ThumbBit; + else + flags &= ~ThumbBit; + } + + bool + nextThumb() const + { + return nextFlags & ThumbBit; + } + + void + nextThumb(bool val) + { + if (val) + nextFlags |= ThumbBit; + else + nextFlags &= ~ThumbBit; + } + + void size(uint8_t s) { _size = s; } + uint8_t size() const { return _size; } + + bool + branching() const + { + return ((this->pc() + this->size()) != this->npc()); + } + + + bool + jazelle() const + { + return flags & JazelleBit; + } + + void + jazelle(bool val) + { + if (val) + flags |= JazelleBit; + else + flags &= ~JazelleBit; + } + + bool + nextJazelle() const + { + return nextFlags & JazelleBit; + } + + void + nextJazelle(bool val) + { + if (val) + nextFlags |= JazelleBit; + else + nextFlags &= ~JazelleBit; + } + + bool + aarch64() const + { + return flags & AArch64Bit; + } + + void + aarch64(bool val) + { + if (val) + flags |= AArch64Bit; + else + flags &= ~AArch64Bit; + } + + bool + nextAArch64() const + { + return nextFlags & AArch64Bit; + } + + void + nextAArch64(bool val) + { + if (val) + nextFlags |= AArch64Bit; + else + nextFlags &= ~AArch64Bit; + } + + + uint8_t + itstate() const + { + return _itstate; + } + + void + itstate(uint8_t value) + { + _itstate = value; + } + + uint8_t + nextItstate() const + { + return _nextItstate; + } + + void + nextItstate(uint8_t value) + { + _nextItstate = value; + } + + void + advance() + { + Base::advance(); + flags = nextFlags; + npc(pc() + (thumb() ? 2 : 4)); + + if (_nextItstate) { + _itstate = _nextItstate; + _nextItstate = 0; + } else if (_itstate) { + ITSTATE it = _itstate; + uint8_t cond_mask = it.mask; + uint8_t thumb_cond = it.cond; + DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n", + thumb_cond, cond_mask); + cond_mask <<= 1; + uint8_t new_bit = bits(cond_mask, 4); + cond_mask &= mask(4); + if (cond_mask == 0) + thumb_cond = 0; + else + replaceBits(thumb_cond, 0, new_bit); + DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n", + thumb_cond, cond_mask); + it.mask = cond_mask; + it.cond = thumb_cond; + _itstate = it; + } + } + + void + uEnd() + { + advance(); + upc(0); + nupc(1); + } + + Addr + instPC() const + { + return pc() + (thumb() ? 4 : 8); + } + + void + instNPC(Addr val) + { + // @todo: review this when AArch32/64 interprocessing is + // supported + if (aarch64()) + npc(val); // AArch64 doesn't force PC alignment, a PC + // Alignment Fault can be raised instead + else + npc(val &~ mask(nextThumb() ? 1 : 2)); + } + + Addr + instNPC() const + { + return npc(); + } + + // Perform an interworking branch. + void + instIWNPC(Addr val) + { + bool thumbEE = (thumb() && jazelle()); + + Addr newPC = val; + if (thumbEE) { + if (bits(newPC, 0)) { + newPC = newPC & ~mask(1); + } // else we have a bad interworking address; do not call + // panic() since the instruction could be executed + // speculatively + } else { + if (bits(newPC, 0)) { + nextThumb(true); + newPC = newPC & ~mask(1); + } else if (!bits(newPC, 1)) { + nextThumb(false); + } else { + // This state is UNPREDICTABLE in the ARM architecture + // The easy thing to do is just mask off the bit and + // stay in the current mode, so we'll do that. + newPC &= ~mask(2); + } + } + npc(newPC); + } + + // Perform an interworking branch in ARM mode, a regular branch + // otherwise. + void + instAIWNPC(Addr val) + { + if (!thumb() && !jazelle()) + instIWNPC(val); + else + instNPC(val); + } + + bool + operator == (const PCState &opc) const + { + return Base::operator == (opc) && + flags == opc.flags && nextFlags == opc.nextFlags && + _itstate == opc._itstate && + _nextItstate == opc._nextItstate && + _illegalExec == opc._illegalExec && + _debugStep == opc._debugStep && + _stepped == opc._stepped; + } + + bool + operator != (const PCState &opc) const + { + return !(*this == opc); + } + + void + serialize(CheckpointOut &cp) const override + { + Base::serialize(cp); + SERIALIZE_SCALAR(flags); + SERIALIZE_SCALAR(_size); + SERIALIZE_SCALAR(nextFlags); + SERIALIZE_SCALAR(_itstate); + SERIALIZE_SCALAR(_nextItstate); + SERIALIZE_SCALAR(_illegalExec); + SERIALIZE_SCALAR(_debugStep); + SERIALIZE_SCALAR(_stepped); + } + + void + unserialize(CheckpointIn &cp) override + { + Base::unserialize(cp); + UNSERIALIZE_SCALAR(flags); + UNSERIALIZE_SCALAR(_size); + UNSERIALIZE_SCALAR(nextFlags); + UNSERIALIZE_SCALAR(_itstate); + UNSERIALIZE_SCALAR(_nextItstate); + UNSERIALIZE_SCALAR(_illegalExec); + UNSERIALIZE_SCALAR(_debugStep); + UNSERIALIZE_SCALAR(_stepped); + } +}; + +} // namespace ArmISA + +#endif diff --git a/src/arch/arm/regs/int.hh b/src/arch/arm/regs/int.hh index d7090416f7..fa52c1680b 100644 --- a/src/arch/arm/regs/int.hh +++ b/src/arch/arm/regs/int.hh @@ -44,6 +44,8 @@ #define __ARCH_ARM_REGS_INT_HH__ #include "arch/arm/types.hh" +#include "base/logging.hh" +#include "sim/core.hh" namespace ArmISA { diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index 6d5bc2a908..60566fc655 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -41,11 +41,11 @@ #ifndef __ARCH_ARM_TYPES_HH__ #define __ARCH_ARM_TYPES_HH__ -#include "arch/generic/types.hh" +#include + +#include "arch/arm/pcstate.hh" #include "base/bitunion.hh" #include "base/logging.hh" -#include "base/types.hh" -#include "debug/Decoder.hh" namespace ArmISA { @@ -53,20 +53,6 @@ namespace ArmISA typedef uint16_t vmid_t; - BitUnion8(ITSTATE) - /* Note that the split (cond, mask) below is not as in ARM ARM. - * But it is more convenient for simulation. The condition - * is always the concatenation of the top 3 bits and the next bit, - * which applies when one of the bottom 4 bits is set. - * Refer to predecoder.cc for the use case. - */ - Bitfield<7, 4> cond; - Bitfield<3, 0> mask; - // Bitfields for moving to/from CPSR - Bitfield<7, 2> top6; - Bitfield<1, 0> bottom2; - EndBitUnion(ITSTATE) - BitUnion64(ExtMachInst) // Decoder state Bitfield<63, 62> decoderFault; // See DecoderFault @@ -213,359 +199,6 @@ namespace ArmISA Bitfield<11, 8> ltcoproc; EndBitUnion(ExtMachInst) - class PCState : public GenericISA::UPCState<4> - { - protected: - - typedef GenericISA::UPCState<4> Base; - - enum FlagBits - { - ThumbBit = (1 << 0), - JazelleBit = (1 << 1), - AArch64Bit = (1 << 2) - }; - - uint8_t flags; - uint8_t nextFlags; - uint8_t _itstate; - uint8_t _nextItstate; - uint8_t _size; - bool _illegalExec; - - // Software Step flags - bool _debugStep; - bool _stepped; - - public: - PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0), - _size(0), _illegalExec(false), _debugStep(false), - _stepped(false) - {} - - void - set(Addr val) - { - Base::set(val); - npc(val + (thumb() ? 2 : 4)); - } - - PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), - _nextItstate(0), _size(0), _illegalExec(false), - _debugStep(false), _stepped(false) - { set(val); } - - bool - illegalExec() const - { - return _illegalExec; - } - - void - illegalExec(bool val) - { - _illegalExec = val; - } - - bool - debugStep() const - { - return _debugStep; - } - - void - debugStep(bool val) - { - _debugStep = val; - } - - bool - stepped() const - { - return _stepped; - } - - void - stepped(bool val) - { - _stepped = val; - } - - bool - thumb() const - { - return flags & ThumbBit; - } - - void - thumb(bool val) - { - if (val) - flags |= ThumbBit; - else - flags &= ~ThumbBit; - } - - bool - nextThumb() const - { - return nextFlags & ThumbBit; - } - - void - nextThumb(bool val) - { - if (val) - nextFlags |= ThumbBit; - else - nextFlags &= ~ThumbBit; - } - - void size(uint8_t s) { _size = s; } - uint8_t size() const { return _size; } - - bool - branching() const - { - return ((this->pc() + this->size()) != this->npc()); - } - - - bool - jazelle() const - { - return flags & JazelleBit; - } - - void - jazelle(bool val) - { - if (val) - flags |= JazelleBit; - else - flags &= ~JazelleBit; - } - - bool - nextJazelle() const - { - return nextFlags & JazelleBit; - } - - void - nextJazelle(bool val) - { - if (val) - nextFlags |= JazelleBit; - else - nextFlags &= ~JazelleBit; - } - - bool - aarch64() const - { - return flags & AArch64Bit; - } - - void - aarch64(bool val) - { - if (val) - flags |= AArch64Bit; - else - flags &= ~AArch64Bit; - } - - bool - nextAArch64() const - { - return nextFlags & AArch64Bit; - } - - void - nextAArch64(bool val) - { - if (val) - nextFlags |= AArch64Bit; - else - nextFlags &= ~AArch64Bit; - } - - - uint8_t - itstate() const - { - return _itstate; - } - - void - itstate(uint8_t value) - { - _itstate = value; - } - - uint8_t - nextItstate() const - { - return _nextItstate; - } - - void - nextItstate(uint8_t value) - { - _nextItstate = value; - } - - void - advance() - { - Base::advance(); - flags = nextFlags; - npc(pc() + (thumb() ? 2 : 4)); - - if (_nextItstate) { - _itstate = _nextItstate; - _nextItstate = 0; - } else if (_itstate) { - ITSTATE it = _itstate; - uint8_t cond_mask = it.mask; - uint8_t thumb_cond = it.cond; - DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n", - thumb_cond, cond_mask); - cond_mask <<= 1; - uint8_t new_bit = bits(cond_mask, 4); - cond_mask &= mask(4); - if (cond_mask == 0) - thumb_cond = 0; - else - replaceBits(thumb_cond, 0, new_bit); - DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n", - thumb_cond, cond_mask); - it.mask = cond_mask; - it.cond = thumb_cond; - _itstate = it; - } - } - - void - uEnd() - { - advance(); - upc(0); - nupc(1); - } - - Addr - instPC() const - { - return pc() + (thumb() ? 4 : 8); - } - - void - instNPC(Addr val) - { - // @todo: review this when AArch32/64 interprocessing is - // supported - if (aarch64()) - npc(val); // AArch64 doesn't force PC alignment, a PC - // Alignment Fault can be raised instead - else - npc(val &~ mask(nextThumb() ? 1 : 2)); - } - - Addr - instNPC() const - { - return npc(); - } - - // Perform an interworking branch. - void - instIWNPC(Addr val) - { - bool thumbEE = (thumb() && jazelle()); - - Addr newPC = val; - if (thumbEE) { - if (bits(newPC, 0)) { - newPC = newPC & ~mask(1); - } // else we have a bad interworking address; do not call - // panic() since the instruction could be executed - // speculatively - } else { - if (bits(newPC, 0)) { - nextThumb(true); - newPC = newPC & ~mask(1); - } else if (!bits(newPC, 1)) { - nextThumb(false); - } else { - // This state is UNPREDICTABLE in the ARM architecture - // The easy thing to do is just mask off the bit and - // stay in the current mode, so we'll do that. - newPC &= ~mask(2); - } - } - npc(newPC); - } - - // Perform an interworking branch in ARM mode, a regular branch - // otherwise. - void - instAIWNPC(Addr val) - { - if (!thumb() && !jazelle()) - instIWNPC(val); - else - instNPC(val); - } - - bool - operator == (const PCState &opc) const - { - return Base::operator == (opc) && - flags == opc.flags && nextFlags == opc.nextFlags && - _itstate == opc._itstate && - _nextItstate == opc._nextItstate && - _illegalExec == opc._illegalExec && - _debugStep == opc._debugStep && - _stepped == opc._stepped; - } - - bool - operator != (const PCState &opc) const - { - return !(*this == opc); - } - - void - serialize(CheckpointOut &cp) const override - { - Base::serialize(cp); - SERIALIZE_SCALAR(flags); - SERIALIZE_SCALAR(_size); - SERIALIZE_SCALAR(nextFlags); - SERIALIZE_SCALAR(_itstate); - SERIALIZE_SCALAR(_nextItstate); - SERIALIZE_SCALAR(_illegalExec); - SERIALIZE_SCALAR(_debugStep); - SERIALIZE_SCALAR(_stepped); - } - - void - unserialize(CheckpointIn &cp) override - { - Base::unserialize(cp); - UNSERIALIZE_SCALAR(flags); - UNSERIALIZE_SCALAR(_size); - UNSERIALIZE_SCALAR(nextFlags); - UNSERIALIZE_SCALAR(_itstate); - UNSERIALIZE_SCALAR(_nextItstate); - UNSERIALIZE_SCALAR(_illegalExec); - UNSERIALIZE_SCALAR(_debugStep); - UNSERIALIZE_SCALAR(_stepped); - } - }; - // Shift types for ARM instructions enum ArmShiftType { diff --git a/src/arch/mips/pcstate.hh b/src/arch/mips/pcstate.hh new file mode 100644 index 0000000000..12334d691f --- /dev/null +++ b/src/arch/mips/pcstate.hh @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2007 MIPS Technologies, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_MIPS_PCSTATE_HH__ +#define __ARCH_MIPS_PCSTATE_HH__ + +#include "arch/generic/types.hh" + +namespace MipsISA +{ + +typedef GenericISA::DelaySlotPCState<4> PCState; + +} // namespace MipsISA +#endif diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh index 33a3afc0da..35c77c3445 100644 --- a/src/arch/mips/types.hh +++ b/src/arch/mips/types.hh @@ -29,8 +29,9 @@ #ifndef __ARCH_MIPS_TYPES_HH__ #define __ARCH_MIPS_TYPES_HH__ -#include "arch/generic/types.hh" -#include "base/types.hh" +#include + +#include "arch/mips/pcstate.hh" namespace MipsISA { @@ -38,8 +39,6 @@ namespace MipsISA typedef uint32_t MachInst; typedef uint64_t ExtMachInst; -typedef GenericISA::DelaySlotPCState<4> PCState; - //used in FP convert & round function enum ConvertType { diff --git a/src/arch/null/types.hh b/src/arch/null/pcstate.hh similarity index 100% rename from src/arch/null/types.hh rename to src/arch/null/pcstate.hh diff --git a/src/arch/null/vecregs.hh b/src/arch/null/vecregs.hh index 016b99cdd9..1f4f7ecd36 100644 --- a/src/arch/null/vecregs.hh +++ b/src/arch/null/vecregs.hh @@ -38,6 +38,9 @@ #ifndef __ARCH_NULL_VECREGS_HH__ #define __ARCH_NULL_VECREGS_HH__ +#include + +#include "arch/generic/types.hh" #include "arch/generic/vec_pred_reg.hh" #include "arch/generic/vec_reg.hh" diff --git a/src/arch/power/insts/static_inst.hh b/src/arch/power/insts/static_inst.hh index 585e8a389e..eed7c8668f 100644 --- a/src/arch/power/insts/static_inst.hh +++ b/src/arch/power/insts/static_inst.hh @@ -29,6 +29,7 @@ #ifndef __ARCH_POWER_INSTS_STATICINST_HH__ #define __ARCH_POWER_INSTS_STATICINST_HH__ +#include "arch/power/types.hh" #include "base/trace.hh" #include "cpu/static_inst.hh" diff --git a/src/arch/power/pcstate.hh b/src/arch/power/pcstate.hh new file mode 100644 index 0000000000..1d3cd271d4 --- /dev/null +++ b/src/arch/power/pcstate.hh @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2009 The University of Edinburgh + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_POWER_PCSTATE_HH__ +#define __ARCH_POWER_PCSTATE_HH__ + +#include "arch/generic/types.hh" + +namespace PowerISA +{ + +typedef GenericISA::SimplePCState<4> PCState; + +} + +#endif // __ARCH_POWER_PCSTATE_HH__ diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh index cd060ccc1c..bc5b4eecde 100644 --- a/src/arch/power/types.hh +++ b/src/arch/power/types.hh @@ -29,9 +29,10 @@ #ifndef __ARCH_POWER_TYPES_HH__ #define __ARCH_POWER_TYPES_HH__ -#include "arch/generic/types.hh" +#include + +#include "arch/power/pcstate.hh" #include "base/bitunion.hh" -#include "base/types.hh" namespace PowerISA { @@ -81,8 +82,6 @@ BitUnion32(ExtMachInst) Bitfield<19, 12> fxm; EndBitUnion(ExtMachInst) -typedef GenericISA::SimplePCState<4> PCState; - // typedef uint64_t LargestRead; // // Need to use 64 bits to make sure that read requests get handled properly diff --git a/src/arch/riscv/pcstate.hh b/src/arch/riscv/pcstate.hh new file mode 100644 index 0000000000..720f2916c4 --- /dev/null +++ b/src/arch/riscv/pcstate.hh @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2013 ARM Limited + * Copyright (c) 2014 Sven Karlsson + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Copyright (c) 2017 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_RISCV_PCSTATE_HH__ +#define __ARCH_RISCV_PCSTATE_HH__ + +#include "arch/generic/types.hh" + +namespace RiscvISA +{ + +class PCState : public GenericISA::UPCState<4> +{ + private: + bool _compressed; + bool _rv32; + + public: + PCState() : UPCState() { _compressed = false; _rv32 = false; } + PCState(Addr val) : UPCState(val) { _compressed = false; _rv32 = false; } + + void compressed(bool c) { _compressed = c; } + bool compressed() { return _compressed; } + + void rv32(bool val) { _rv32 = val; } + bool rv32() const { return _rv32; } + + bool + branching() const + { + if (_compressed) { + return npc() != pc() + 2 || nupc() != upc() + 1; + } else { + return npc() != pc() + 4 || nupc() != upc() + 1; + } + } +}; + +} + +#endif // __ARCH_RISCV_PCSTATE_HH__ diff --git a/src/arch/riscv/types.hh b/src/arch/riscv/types.hh index 68c3f98762..146d234457 100644 --- a/src/arch/riscv/types.hh +++ b/src/arch/riscv/types.hh @@ -42,7 +42,7 @@ #ifndef __ARCH_RISCV_TYPES_HH__ #define __ARCH_RISCV_TYPES_HH__ -#include "arch/generic/types.hh" +#include "arch/riscv/pcstate.hh" namespace RiscvISA { @@ -50,35 +50,6 @@ namespace RiscvISA typedef uint32_t MachInst; typedef uint64_t ExtMachInst; -class PCState : public GenericISA::UPCState<4> -{ - private: - bool _compressed; - bool _rv32; - - public: - PCState() : UPCState() { _compressed = false; _rv32 = false; } - PCState(Addr val) : UPCState(val) { _compressed = false; _rv32 = false; } - - void compressed(bool c) { _compressed = c; } - bool compressed() { return _compressed; } - - void rv32(bool val) { _rv32 = val; } - bool rv32() const { return _rv32; } - - bool - branching() const - { - if (_compressed) { - return npc() != pc() + sizeof(MachInst)/2 || - nupc() != upc() + 1; - } else { - return npc() != pc() + sizeof(MachInst) || - nupc() != upc() + 1; - } - } -}; - } #endif // __ARCH_RISCV_TYPES_HH__ diff --git a/src/arch/sparc/insts/static_inst.hh b/src/arch/sparc/insts/static_inst.hh index ffcf135936..f8af2d952b 100644 --- a/src/arch/sparc/insts/static_inst.hh +++ b/src/arch/sparc/insts/static_inst.hh @@ -32,6 +32,7 @@ #include +#include "arch/sparc/types.hh" #include "base/trace.hh" #include "cpu/exec_context.hh" #include "cpu/static_inst.hh" diff --git a/src/arch/sparc/pcstate.hh b/src/arch/sparc/pcstate.hh new file mode 100644 index 0000000000..fea933928d --- /dev/null +++ b/src/arch/sparc/pcstate.hh @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_SPARC_PCSTATE_HH__ +#define __ARCH_SPARC_PCSTATE_HH__ + +#include "arch/generic/types.hh" + +namespace SparcISA +{ + +typedef GenericISA::DelaySlotUPCState<4> PCState; + +} + +#endif diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc index 53d2250a10..f59a41848e 100644 --- a/src/arch/sparc/remote_gdb.cc +++ b/src/arch/sparc/remote_gdb.cc @@ -126,6 +126,7 @@ #include "arch/sparc/regs/int.hh" #include "arch/sparc/regs/misc.hh" +#include "arch/sparc/types.hh" #include "base/intmath.hh" #include "base/remote_gdb.hh" #include "base/socket.hh" diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 2a84aed635..6bbd8cd0b5 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -35,6 +35,7 @@ #include "arch/sparc/interrupts.hh" #include "arch/sparc/mmu.hh" #include "arch/sparc/regs/misc.hh" +#include "arch/sparc/types.hh" #include "base/bitfield.hh" #include "base/compiler.hh" #include "base/trace.hh" diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh index ffb9806690..3999cde4b2 100644 --- a/src/arch/sparc/types.hh +++ b/src/arch/sparc/types.hh @@ -29,7 +29,7 @@ #ifndef __ARCH_SPARC_TYPES_HH__ #define __ARCH_SPARC_TYPES_HH__ -#include "arch/generic/types.hh" +#include "arch/sparc/pcstate.hh" #include "base/types.hh" namespace SparcISA @@ -38,8 +38,6 @@ namespace SparcISA typedef uint32_t MachInst; typedef uint64_t ExtMachInst; -typedef GenericISA::DelaySlotUPCState<4> PCState; - } #endif diff --git a/src/arch/x86/insts/static_inst.hh b/src/arch/x86/insts/static_inst.hh index 4e0cba2a4d..dc04a4f5be 100644 --- a/src/arch/x86/insts/static_inst.hh +++ b/src/arch/x86/insts/static_inst.hh @@ -38,6 +38,7 @@ #ifndef __ARCH_X86_INSTS_STATICINST_HH__ #define __ARCH_X86_INSTS_STATICINST_HH__ +#include "arch/x86/types.hh" #include "base/trace.hh" #include "cpu/static_inst.hh" #include "debug/X86.hh" diff --git a/src/arch/x86/pcstate.hh b/src/arch/x86/pcstate.hh new file mode 100644 index 0000000000..8ad2d97b4f --- /dev/null +++ b/src/arch/x86/pcstate.hh @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2007 The Hewlett-Packard Development Company + * All rights reserved. + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_X86_PCSTATE_HH__ +#define __ARCH_X86_PCSTATE_HH__ + +#include "arch/generic/types.hh" +#include "sim/serialize.hh" + +namespace X86ISA +{ + +class PCState : public GenericISA::UPCState<8> +{ + protected: + typedef GenericISA::UPCState<8> Base; + + uint8_t _size; + + public: + void + set(Addr val) + { + Base::set(val); + _size = 0; + } + + PCState() {} + PCState(Addr val) { set(val); } + + void + setNPC(Addr val) + { + Base::setNPC(val); + _size = 0; + } + + uint8_t size() const { return _size; } + void size(uint8_t newSize) { _size = newSize; } + + bool + branching() const + { + return (this->npc() != this->pc() + size()) || + (this->nupc() != this->upc() + 1); + } + + void + advance() + { + Base::advance(); + _size = 0; + } + + void + uEnd() + { + Base::uEnd(); + _size = 0; + } + + void + serialize(CheckpointOut &cp) const + { + Base::serialize(cp); + SERIALIZE_SCALAR(_size); + } + + void + unserialize(CheckpointIn &cp) + { + Base::unserialize(cp); + UNSERIALIZE_SCALAR(_size); + } +}; + +} + +#endif // __ARCH_X86_PCSTATE_HH__ diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index f2b612f91d..ce03de285a 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -38,13 +38,13 @@ #ifndef __ARCH_X86_TYPES_HH__ #define __ARCH_X86_TYPES_HH__ +#include +#include #include -#include "arch/generic/types.hh" +#include "arch/x86/pcstate.hh" #include "base/bitunion.hh" #include "base/cprintf.hh" -#include "base/types.hh" -#include "sim/serialize.hh" namespace X86ISA { @@ -287,70 +287,6 @@ operator == (const ExtMachInst &emi1, const ExtMachInst &emi2) return true; } -class PCState : public GenericISA::UPCState<8> -{ - protected: - typedef GenericISA::UPCState<8> Base; - - uint8_t _size; - - public: - void - set(Addr val) - { - Base::set(val); - _size = 0; - } - - PCState() {} - PCState(Addr val) { set(val); } - - void - setNPC(Addr val) - { - Base::setNPC(val); - _size = 0; - } - - uint8_t size() const { return _size; } - void size(uint8_t newSize) { _size = newSize; } - - bool - branching() const - { - return (this->npc() != this->pc() + size()) || - (this->nupc() != this->upc() + 1); - } - - void - advance() - { - Base::advance(); - _size = 0; - } - - void - uEnd() - { - Base::uEnd(); - _size = 0; - } - - void - serialize(CheckpointOut &cp) const - { - Base::serialize(cp); - SERIALIZE_SCALAR(_size); - } - - void - unserialize(CheckpointIn &cp) - { - Base::unserialize(cp); - UNSERIALIZE_SCALAR(_size); - } -}; - } namespace std diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh index 93d3621c9c..ce39869094 100644 --- a/src/base/remote_gdb.hh +++ b/src/base/remote_gdb.hh @@ -50,7 +50,7 @@ #include #include -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "base/cprintf.hh" #include "base/pollevent.hh" #include "base/socket.hh" diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 4a7dad86e3..6d191741d6 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -46,7 +46,7 @@ #include #include -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "base/statistics.hh" #include "cpu/base.hh" #include "cpu/exec_context.hh" diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index 5d404ed4be..933df4292d 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -42,7 +42,7 @@ #ifndef __CPU_CHECKER_THREAD_CONTEXT_HH__ #define __CPU_CHECKER_THREAD_CONTEXT_HH__ -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "config/the_isa.hh" #include "cpu/checker/cpu.hh" #include "cpu/simple_thread.hh" diff --git a/src/cpu/inst_pb_trace.hh b/src/cpu/inst_pb_trace.hh index bce9bf7916..5984a306bb 100644 --- a/src/cpu/inst_pb_trace.hh +++ b/src/cpu/inst_pb_trace.hh @@ -38,7 +38,7 @@ #ifndef __CPU_INST_PB_TRACE_HH__ #define __CPU_INST_PB_TRACE_HH__ -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "base/trace.hh" #include "base/types.hh" #include "cpu/static_inst_fwd.hh" diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh index ceb7d9d6e5..e4c3a208bd 100644 --- a/src/cpu/o3/comm.hh +++ b/src/cpu/o3/comm.hh @@ -44,7 +44,7 @@ #include -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "base/types.hh" #include "cpu/inst_seq.hh" #include "cpu/o3/dyn_inst_ptr.hh" diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 5d40e0041b..41e340baba 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -50,7 +50,7 @@ #include #include "arch/generic/types.hh" -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "base/statistics.hh" #include "config/the_isa.hh" #include "cpu/o3/comm.hh" diff --git a/src/cpu/o3/decode.cc b/src/cpu/o3/decode.cc index 6815a22589..c89d74030c 100644 --- a/src/cpu/o3/decode.cc +++ b/src/cpu/o3/decode.cc @@ -40,7 +40,7 @@ #include "cpu/o3/decode.hh" -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "base/trace.hh" #include "config/the_isa.hh" #include "cpu/inst_seq.hh" diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 3447b36dae..543d19fff2 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -45,6 +45,7 @@ #include #include "arch/generic/isa.hh" +#include "arch/pcstate.hh" #include "arch/vecregs.hh" #include "base/trace.hh" #include "config/the_isa.hh" diff --git a/src/cpu/o3/rename_map.hh b/src/cpu/o3/rename_map.hh index 21abd84f32..8f7e589c28 100644 --- a/src/cpu/o3/rename_map.hh +++ b/src/cpu/o3/rename_map.hh @@ -47,8 +47,6 @@ #include #include "arch/generic/isa.hh" -#include "arch/types.hh" -#include "config/the_isa.hh" #include "cpu/o3/free_list.hh" #include "cpu/o3/regfile.hh" #include "cpu/reg_class.hh" diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc index f8965f0616..9eb596336b 100644 --- a/src/cpu/pred/bpred_unit.cc +++ b/src/cpu/pred/bpred_unit.cc @@ -44,7 +44,7 @@ #include -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "base/compiler.hh" #include "base/trace.hh" #include "config/the_isa.hh" diff --git a/src/cpu/pred/btb.hh b/src/cpu/pred/btb.hh index 2134c9bd9b..06adf87f80 100644 --- a/src/cpu/pred/btb.hh +++ b/src/cpu/pred/btb.hh @@ -29,7 +29,7 @@ #ifndef __CPU_PRED_BTB_HH__ #define __CPU_PRED_BTB_HH__ -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "base/logging.hh" #include "base/types.hh" #include "config/the_isa.hh" diff --git a/src/cpu/pred/indirect.hh b/src/cpu/pred/indirect.hh index 469c48d7d2..9f64e3f1ba 100644 --- a/src/cpu/pred/indirect.hh +++ b/src/cpu/pred/indirect.hh @@ -29,7 +29,7 @@ #ifndef __CPU_PRED_INDIRECT_BASE_HH__ #define __CPU_PRED_INDIRECT_BASE_HH__ -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "config/the_isa.hh" #include "cpu/inst_seq.hh" #include "params/IndirectPredictor.hh" diff --git a/src/cpu/pred/ras.hh b/src/cpu/pred/ras.hh index 65bc1d407c..c05a83529a 100644 --- a/src/cpu/pred/ras.hh +++ b/src/cpu/pred/ras.hh @@ -31,7 +31,7 @@ #include -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "base/types.hh" #include "config/the_isa.hh" diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index fa52c88573..5763da683c 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -50,7 +50,7 @@ #include "arch/generic/mmu.hh" #include "arch/generic/tlb.hh" #include "arch/isa.hh" -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "arch/vecregs.hh" #include "base/types.hh" #include "config/the_isa.hh" diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index 78efd6d72c..49a82431a2 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -47,7 +47,7 @@ #include #include -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "base/logging.hh" #include "base/refcnt.hh" #include "config/the_isa.hh" diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 333c084d54..aec573e259 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -47,7 +47,7 @@ #include "arch/generic/htm.hh" #include "arch/generic/isa.hh" -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "arch/vecregs.hh" #include "base/types.hh" #include "config/the_isa.hh" diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index 9408d667d8..cf363697f7 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -29,7 +29,7 @@ #ifndef __CPU_THREAD_STATE_HH__ #define __CPU_THREAD_STATE_HH__ -#include "arch/types.hh" +#include "arch/pcstate.hh" #include "config/the_isa.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh"