arch-riscv: Update the way a valid virtual address is computed

According to privileged ISA specs, a valid 64 bit virtual address should
have bit 63-39 same as bit 38 (for Sv39). Without this change, kernel page
fault handler does not seem to work correctly. For example, while running
a program, the kernel was segfaulting complaining that it cannot handle
kernel paging request at some virtual address (which is the faulting
address returned by gem5 currently, with all bits after first 39 cleared).
With this change, that error goes away.

Change-Id: Iae7c9d0af19e29214e14a0db08d7c0ac122122bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45920
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nils Asmussen <nils.asmussen@barkhauseninstitut.org>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/riscv/pagetable_walker.cc

@@ -418,7 +418,7 @@ Walker::WalkerState::endWalk()
 void
 Walker::WalkerState::setupWalk(Addr vaddr)
 {
-    vaddr &= (static_cast<Addr>(1) << VADDR_BITS) - 1;
+    vaddr = Addr(sext<VADDR_BITS>(vaddr));
 
     Addr shift = PageShift + LEVEL_BITS * 2;
     Addr idx = (vaddr >> shift) & LEVEL_MASK;
@@ -486,7 +486,7 @@ Walker::WalkerState::recvPacket(PacketPtr pkt)
              * well.
              */
             Addr vaddr = req->getVaddr();
-            vaddr &= (static_cast<Addr>(1) << VADDR_BITS) - 1;
+            vaddr = Addr(sext<VADDR_BITS>(vaddr));
             Addr paddr = walker->tlb->translateWithTLB(vaddr, satp.asid, mode);
             req->setPaddr(paddr);
             walker->pma->check(req);

src/arch/riscv/tlb.cc

@@ -277,7 +277,7 @@ TLB::doTranslate(const RequestPtr &req, ThreadContext *tc,
 {
     delayed = false;
 
-    Addr vaddr = req->getVaddr() & ((static_cast<Addr>(1) << VADDR_BITS) - 1);
+    Addr vaddr = Addr(sext<VADDR_BITS>(req->getVaddr()));
     SATP satp = tc->readMiscReg(MISCREG_SATP);
 
     TlbEntry *e = lookup(vaddr, satp.asid, mode, false);