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gem5/src/arch/riscv
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Andreas Sandberg 7806eaad51 arch: Add instruction size and PC set methods (#357) 
Add the instruction size of a static instruction. x86 and arm decoders
add now the instruction size to the macro instruction. However, microops
are still handled by the fetch stage which is not nice.
Furthermore, we add a set method to the PC state. It allows setting a PC
state to acertain address.
Both methods are required for the decoupled front-end.

Change-Id: I311fe3f637e867c42dee7781f5373ea2e69e2072
2023-10-04 10:49:30 +01:00
..
bare_metal
arch-riscv: Insert symbol table of bootloader into debug symbol table
2023-04-13 00:10:47 +00:00
gdb-xml
arch-riscv: Support RV32 to remote gdb
2022-12-13 05:21:27 +00:00
insts
arch: Add instruction size and PC set methods
2023-10-02 20:10:57 +00:00
isa
arch-riscv: FS bits -> DIRTY for more floating point loads
2023-10-01 23:12:25 -07:00
linux
arch-riscv,sim-se: Support RV32 register ABI call
2023-02-02 04:50:04 +00:00
regs
arch-riscv: Change VTYPE to BitUnion64
2023-09-12 13:56:21 +08:00
decoder.cc
arch: Add instruction size and PC set methods
2023-10-02 20:10:57 +00:00
decoder.hh
arch-riscv: Make RISC-V decodeInst overridable
2023-09-22 11:38:22 +08:00
faults.cc
arch-riscv: Add vlenb, vtype and vl in PCState
2023-09-12 13:56:21 +08:00
faults.hh
arch-riscv: Add risc-v vector regs and configs
2023-08-02 14:46:35 +02:00
fp_inst.hh
arch-riscv: When an inst generates a fault, return it immediately.
2021-05-20 23:42:13 +00:00
idle_event.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
idle_event.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
interrupts.hh
arch-riscv: Correct interrupt order
2023-01-11 01:02:11 +00:00
isa.cc
arch-riscv: Get vl, vtype and vlenb from PCState
2023-09-12 13:56:21 +08:00
isa.hh
arch-riscv: Add vlenb, vtype and vl in PCState
2023-09-12 13:56:21 +08:00
mmu.hh
arch: Make the MMU ranged translateFunction pure virtual.
2021-10-22 21:43:02 +00:00
page_size.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable_walker.cc
arch-riscv: fix memory leak problem in page table walker
2022-02-19 11:49:44 +00:00
pagetable_walker.hh
mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner
2023-02-03 06:11:45 +00:00
pagetable.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pagetable.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pcstate.hh
arch-riscv: Add vlenb, vtype and vl in PCState
2023-09-12 13:56:21 +08:00
pma_checker.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
pma_checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
PMAChecker.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
pmp.cc
arch-riscv: Refactor the shouldCheckPMP function
2023-04-11 08:43:47 +00:00
pmp.hh
arch-riscv: Refactor the shouldCheckPMP function
2023-04-11 08:43:47 +00:00
PMP.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
pra_constants.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
process.cc
arch-riscv: Check RISCV process run in matched CPU
2023-01-11 01:00:32 +00:00
process.hh
base: Remove the Loader namespace
2023-01-17 09:16:20 +00:00
reg_abi.cc
arch-riscv,sim-se: Support RV32 register ABI call
2023-02-02 04:50:04 +00:00
reg_abi.hh
arch-riscv,sim-se: Support RV32 register ABI call
2023-02-02 04:50:04 +00:00
remote_gdb.cc
arch,base,dev,sim: Convert objects to use the HostSocket param type.
2023-04-12 02:18:22 +00:00
remote_gdb.hh
arch,base,dev,sim: Convert objects to use the HostSocket param type.
2023-04-12 02:18:22 +00:00
RiscvCPU.py
arch-riscv: Allow Minor and O3 CPU execute RVV
2023-09-12 13:56:22 +08:00
RiscvDecoder.py
arch-riscv: Add fatal if RVV used with o3 or minor
2023-08-02 14:46:36 +02:00
RiscvFsWorkload.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
RiscvInterrupts.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
RiscvISA.py
arch-riscv: Add fatal if RVV used with o3 or minor
2023-08-02 14:46:36 +02:00
RiscvMMU.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
RiscvSeWorkload.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
RiscvTLB.py
python: Apply Black formatter to Python files
2022-08-03 09:10:41 +00:00
rvk.hh
arch-riscv: Add RV32 only Zk instruction extensions
2023-05-03 00:42:37 +00:00
SConscript
arch-riscv: Add basic features toward rv32 support
2022-12-02 23:53:45 +00:00
SConsopts
misc: Replace TARGET_ISA with USE_${ISA} variables.
2022-09-02 10:20:51 +00:00
se_workload.hh
arch-riscv,sim-se: Support RV32 register ABI call
2023-02-02 04:50:04 +00:00
stacktrace.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
tlb.cc
misc: Move Mode and Translation from BaseTLB to BaseMMU
2021-07-07 08:44:13 +00:00
tlb.hh
arch-riscv: Remove unused stats
2021-09-09 15:01:38 +00:00
types.hh
arch-riscv: refactor bitfields of insts
2023-04-26 00:41:06 +00:00
utility.hh
arch-riscv: Add risc-v vector ext v1.0 arith insts support
2023-08-02 14:46:36 +02:00