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arch-riscv: Refactor the shouldCheckPMP function

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The shouldCheckPMP can be simply with pmode != PRV_M since the
privilege mode of memory is modified by TLB and Walker. The
numRules check can done in shouldPMPCheck

Change-Id: I842687674fed7bc4d88a9ba6b4c4d52c3459068f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69497
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
This commit is contained in:
Roger Chang
2023-04-07 16:47:52 +08:00
parent e37b1d1d92
commit e4a46cb09d
2 changed files with 11 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
src/arch/riscv/pmp.cc
View File

@@ -59,7 +59,7 @@ PMP::pmpCheck(const RequestPtr &req, BaseMMU::Mode mode,
Addr vaddr)
{
// First determine if pmp table should be consulted
if (!shouldCheckPMP(pmode, mode, tc))
if (!shouldCheckPMP(pmode, tc))
return NoFault;
if (req->hasVaddr()) {
@@ -71,9 +71,6 @@ PMP::pmpCheck(const RequestPtr &req, BaseMMU::Mode mode,
req->getPaddr());
}
if (numRules == 0)
return NoFault;
// match_index will be used to identify the pmp entry
// which matched for the given address
int match_index = -1;
@@ -273,26 +270,14 @@ PMP::pmpUpdateAddr(uint32_t pmp_index, Addr this_addr)
}
bool
PMP::shouldCheckPMP(RiscvISA::PrivilegeMode pmode,
BaseMMU::Mode mode, ThreadContext *tc)
PMP::shouldCheckPMP(RiscvISA::PrivilegeMode pmode, ThreadContext *tc)
{
// instruction fetch in S and U mode
bool cond1 = (mode == BaseMMU::Execute &&
(pmode != RiscvISA::PrivilegeMode::PRV_M));
// data access in S and U mode when MPRV in mstatus is clear
RiscvISA::STATUS status =
tc->readMiscRegNoEffect(RiscvISA::MISCREG_STATUS);
bool cond2 = (mode != BaseMMU::Execute &&
(pmode != RiscvISA::PrivilegeMode::PRV_M)
&& (!status.mprv));
// data access in any mode when MPRV bit in mstatus is set
// and the MPP field in mstatus is S or U
bool cond3 = (mode != BaseMMU::Execute && (status.mprv)
&& (status.mpp != RiscvISA::PrivilegeMode::PRV_M));
return (cond1 || cond2 || cond3 || hasLockEntry);
// The privilege mode of memory read and write
// is modified by TLB. It can just simply check if
// the numRule is not zero, then return true if
// privilege mode is not M or has any lock entry
return numRules != 0 && (
pmode != RiscvISA::PrivilegeMode::PRV_M || hasLockEntry);
}
AddrRange

8
src/arch/riscv/pmp.hh
View File

@@ -118,7 +118,7 @@ class PMP : public SimObject
* is allowed based on the pmp rules.
* @param req memory request.
* @param mode mode of request (read, write, execute).
* @param pmode current privilege mode of execution (U, S, M).
* @param pmode current privilege mode of memory (U, S, M).
* @param tc thread context.
* @param vaddr optional parameter to pass vaddr of original
* request for which a page table walk is consulted by pmp unit
@@ -159,13 +159,11 @@ class PMP : public SimObject
* This function is called during a memory
* access to determine if the pmp table
* should be consulted for this access.
* @param pmode current privilege mode of execution (U, S, M).
* @param mode mode of request (read, write, execute).
* @param pmode current privilege mode of memory (U, S, M).
* @param tc thread context.
* @return true or false.
*/
bool shouldCheckPMP(RiscvISA::PrivilegeMode pmode,
BaseMMU::Mode mode, ThreadContext *tc);
bool shouldCheckPMP(RiscvISA::PrivilegeMode pmode, ThreadContext *tc);
/**
* createAddrfault creates an address fault