arch-riscv: Add fatal if RVV used with o3 or minor

Since the O3 and Minor CPU models do not support RVV right now as the
implementation stalls the decode until vsetvl instructions are exectued,
this change calls `fatal` if RVV is not explicitly enabled.

It is possible to override this if you explicitly enable RVV in the
config file.

Change-Id: Ia801911141bb2fb2bedcff3e139bf41ba8936085
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>

src/arch/riscv/RiscvCPU.py

@@ -41,6 +41,17 @@ class RiscvCPU:
     ArchISA = RiscvISA
 
 
+class RiscvISANoRVV(RiscvISA):
+    enable_rvv = False
+
+
+class RiscvCPUNoRVV:
+    ArchDecoder = RiscvDecoder
+    ArchMMU = RiscvMMU
+    ArchInterrupts = RiscvInterrupts
+    ArchISA = RiscvISANoRVV
+
+
 class RiscvAtomicSimpleCPU(BaseAtomicSimpleCPU, RiscvCPU):
     mmu = RiscvMMU()
 
@@ -53,9 +64,9 @@ class RiscvTimingSimpleCPU(BaseTimingSimpleCPU, RiscvCPU):
     mmu = RiscvMMU()
 
 
-class RiscvO3CPU(BaseO3CPU, RiscvCPU):
+class RiscvO3CPU(BaseO3CPU, RiscvCPUNoRVV):
     mmu = RiscvMMU()
 
 
-class RiscvMinorCPU(BaseMinorCPU, RiscvCPU):
+class RiscvMinorCPU(BaseMinorCPU, RiscvCPUNoRVV):
     mmu = RiscvMMU()

src/arch/riscv/RiscvDecoder.py

@@ -24,6 +24,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.objects.InstDecoder import InstDecoder
+from m5.params import *
 
 
 class RiscvDecoder(InstDecoder):

src/arch/riscv/RiscvISA.py

@@ -56,3 +56,5 @@ class RiscvISA(BaseISA):
         True, "whether to check memory access alignment"
     )
     riscv_type = Param.RiscvType("RV64", "RV32 or RV64")
+
+    enable_rvv = Param.Bool(True, "Enable vector extension")

src/arch/riscv/decoder.cc

@@ -28,6 +28,7 @@
  */
 
 #include "arch/riscv/decoder.hh"
+#include "arch/riscv/isa.hh"
 #include "arch/riscv/types.hh"
 #include "base/bitfield.hh"
 #include "debug/Decode.hh"
@@ -38,6 +39,13 @@ namespace gem5
 namespace RiscvISA
 {
 
+Decoder::Decoder(const RiscvDecoderParams &p) : InstDecoder(p, &machInst)
+{
+    ISA *isa = dynamic_cast<ISA*>(p.isa);
+    enableRvv = isa->getEnableRvv();
+    reset();
+}
+
 void Decoder::reset()
 {
     aligned = true;
@@ -53,6 +61,10 @@ Decoder::moreBytes(const PCStateBase &pc, Addr fetchPC)
     // TODO: Current vsetvl instructions stall decode. Future fixes should
     // enable speculation, and this code will be removed.
     if (GEM5_UNLIKELY(!this->vConfigDone)) {
+        fatal_if(!enableRvv,
+            "Vector extension is not enabled for this CPU type\n"
+            "You can manually enable vector extensions by setting rvv_enabled "
+            "to true for each ISA object after `createThreads()`\n");
         DPRINTF(Decode, "Waiting for vset*vl* to be executed\n");
         instDone = false;
         outOfBytes = false;

src/arch/riscv/decoder.hh

@@ -61,6 +61,7 @@ class Decoder : public InstDecoder
     ExtMachInst emi;
     uint32_t machInst;
 
+    bool enableRvv = false;
     VTYPE machVtype;
     uint32_t machVl;
 
@@ -72,10 +73,7 @@ class Decoder : public InstDecoder
     StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
 
   public:
-    Decoder(const RiscvDecoderParams &p) : InstDecoder(p, &machInst)
-    {
-        reset();
-    }
+    Decoder(const RiscvDecoderParams &p);
 
     void reset() override;
 

src/arch/riscv/isa.cc

@@ -253,7 +253,8 @@ RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
 } // anonymous namespace
 
 ISA::ISA(const Params &p) :
-    BaseISA(p), rv_type(p.riscv_type), checkAlignment(p.check_alignment)
+    BaseISA(p), rv_type(p.riscv_type), checkAlignment(p.check_alignment),
+    enableRvv(p.enable_rvv)
 {
     _regClasses.push_back(&intRegClass);
     _regClasses.push_back(&floatRegClass);
@@ -324,8 +325,10 @@ void ISA::clear()
         case RV64:
           misa.rv64_mxl = 2;
           status.uxl = status.sxl = 2;
-          status.vs = VPUStatus::INITIAL;
-          misa.rvv = 1;
+          if (getEnableRvv()) {
+              status.vs = VPUStatus::INITIAL;
+              misa.rvv = 1;
+          }
           break;
         default:
           panic("%s: Unknown rv_type: %d", name(), (int)rv_type);

src/arch/riscv/isa.hh

@@ -75,6 +75,7 @@ class ISA : public BaseISA
     RiscvType rv_type;
     std::vector<RegVal> miscRegFile;
     bool checkAlignment;
+    bool enableRvv;
 
     bool hpmCounterEnabled(int counter) const;
 
@@ -138,6 +139,8 @@ class ISA : public BaseISA
 
     RiscvType rvType() const { return rv_type; }
 
+    bool getEnableRvv() const { return enableRvv; }
+
     void
     clearLoadReservation(ContextID cid)
     {