arch-riscv: Change VTYPE to BitUnion64

Change-Id: I7620ad1ef3ee0cc045bcd02b3c9a2d83f93bf3fe
2023-09-05 10:39:02 +08:00
parent dfc725838e
commit 3f0475321a
1 changed files with 2 additions and 2 deletions
--- a/src/arch/riscv/regs/vector.hh
+++ b/src/arch/riscv/regs/vector.hh
@@ -75,8 +75,8 @@ inline constexpr RegClass vecRegClass =
        ops(vecRegClassOps).
        regType<VecRegContainer>();

-BitUnion32(VTYPE)
-    Bitfield<31> vill;
+BitUnion64(VTYPE)
+    Bitfield<63> vill;
    Bitfield<7, 0> vtype8;
    Bitfield<7> vma;
    Bitfield<6> vta;