diff --git a/src/arch/riscv/regs/vector.hh b/src/arch/riscv/regs/vector.hh
index d722c2d03a..388e1cb78d 100644
--- a/src/arch/riscv/regs/vector.hh
+++ b/src/arch/riscv/regs/vector.hh
@@ -75,8 +75,8 @@ inline constexpr RegClass vecRegClass =
         ops(vecRegClassOps).
         regType<VecRegContainer>();
 
-BitUnion32(VTYPE)
-    Bitfield<31> vill;
+BitUnion64(VTYPE)
+    Bitfield<63> vill;
     Bitfield<7, 0> vtype8;
     Bitfield<7> vma;
     Bitfield<6> vta;