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arch-riscv: Refactor PCState class

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Change-Id: I1d25350ba2a3c7c366f42340c20b4488c33cde6f
This commit is contained in:
Roger Chang
2023-08-31 13:27:41 +08:00
parent a217c218e0
commit dfc725838e
1 changed files with 29 additions and 8 deletions
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37
src/arch/riscv/pcstate.hh
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@@ -56,15 +56,22 @@ constexpr enums::RiscvType RV64 = enums::RV64;
class PCState : public GenericISA::UPCState<4>
{
private:
protected:
typedef GenericISA::UPCState<4> Base;
bool _compressed = false;
RiscvType _rvType = RV64;
public:
PCState(const PCState &other) : Base(other), _rvType(other._rvType)
{}
PCState &operator=(const PCState &other) = default;
PCState() = default;
PCState(const PCState &other) = default;
PCState(Addr addr, RiscvType rvType) : UPCState(addr), _rvType(rvType)
explicit PCState(Addr addr) { set(addr); }
explicit PCState(Addr addr, RiscvType rvType)
{
set(addr);
_rvType = rvType;
}
PCStateBase *clone() const override { return new PCState(*this); }
@@ -84,14 +91,28 @@ class PCState : public GenericISA::UPCState<4>
void rvType(RiscvType rvType) { _rvType = rvType; }
RiscvType rvType() const { return _rvType; }
uint64_t size() const { return _compressed ? 2 : 4; }
bool
branching() const override
{
if (_compressed) {
return npc() != pc() + 2 || nupc() != upc() + 1;
} else {
return npc() != pc() + 4 || nupc() != upc() + 1;
}
return npc() != pc() + size() || nupc() != upc() + 1;
}
void
serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(_rvType);
SERIALIZE_SCALAR(_compressed);
}
void
unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(_rvType);
UNSERIALIZE_SCALAR(_compressed);
}
};