From 3f0475321a071b016ba92dc4401183032d1c08f0 Mon Sep 17 00:00:00 2001
From: Roger Chang <rogerycchang@google.com>
Date: Tue, 5 Sep 2023 10:39:02 +0800
Subject: [PATCH] arch-riscv: Change VTYPE to BitUnion64

Change-Id: I7620ad1ef3ee0cc045bcd02b3c9a2d83f93bf3fe
---
 src/arch/riscv/regs/vector.hh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/arch/riscv/regs/vector.hh b/src/arch/riscv/regs/vector.hh
index d722c2d03a..388e1cb78d 100644
--- a/src/arch/riscv/regs/vector.hh
+++ b/src/arch/riscv/regs/vector.hh
@@ -75,8 +75,8 @@ inline constexpr RegClass vecRegClass =
         ops(vecRegClassOps).
         regType<VecRegContainer>();
 
-BitUnion32(VTYPE)
-    Bitfield<31> vill;
+BitUnion64(VTYPE)
+    Bitfield<63> vill;
     Bitfield<7, 0> vtype8;
     Bitfield<7> vma;
     Bitfield<6> vta;