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2c457d2a9fdaf373ea9343b2c5a644abaa31b746
gem5/src/cpu/o3
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Samuel Stark 2c457d2a9f cpu: Fix TME for dyn_o3_cpu 
Commit c417b76 changed the behaviour of addRequest(),
but did not update documentation or the HTM-related logic that used it.

Updates documentation for addRequest() in light of c417b76,
refactors request class to be idiomatic and use assigned byteEnable,
made HTM cmds pass in a correct byteEnable.

Change-Id: I7aa8c127df896e81caf915fbfea93e7b4bcc53b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50147
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-09-10 08:13:59 +00:00
..
probe
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
checker.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
checker.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
comm.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
commit.cc
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
commit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cpu.cc
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
cpu.hh
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
decode.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
decode.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dep_graph.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dyn_inst_ptr.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
dyn_inst.cc
cpu: Fix TME for dyn_o3_cpu
2021-09-10 08:13:59 +00:00
dyn_inst.hh
cpu: Simplify or eliminate set${type}Result methods for o3 and checker.
2021-08-11 20:24:54 +00:00
fetch.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
fetch.hh
cpu: Add a branch_prediction namespace
2021-07-07 23:18:59 +00:00
free_list.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
free_list.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
fu_pool.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
fu_pool.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
FuncUnitConfig.py
cpu: Delete authors lists from the cpu directory.
2020-02-17 21:51:23 +00:00
FUPool.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
iew.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
iew.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inst_queue.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
inst_queue.hh
mem: Adopt a memory namespace for memories
2021-07-09 11:24:10 +00:00
limits.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
lsq_unit.cc
misc: Revert "arch,cpu,mem,sim: Fold arch/locked_mem.hh..."
2021-09-04 04:37:49 +00:00
lsq_unit.hh
cpu: Remove unnecessary includes of arch/locked_mem.hh.
2021-07-23 10:41:21 +00:00
lsq.cc
cpu: Fix TME for dyn_o3_cpu
2021-09-10 08:13:59 +00:00
lsq.hh
cpu: Fix TME for dyn_o3_cpu
2021-09-10 08:13:59 +00:00
mem_dep_unit.cc
misc: Replace the GEM5_VAR_USED macro with [[maybe_unused]].
2021-07-29 10:17:51 +00:00
mem_dep_unit.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
O3Checker.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
O3CPU.py
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
regfile.cc
cpu: Rename RegClassInfo to RegClass.
2021-08-09 20:04:51 +00:00
regfile.hh
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
rename_map.cc
cpu: Rename RegClassInfo to RegClass.
2021-08-09 20:04:51 +00:00
rename_map.hh
cpu-o3: Fix minor style issue in rename_map.hh.
2021-08-12 22:01:30 +00:00
rename.cc
misc: Rename Debug namespace as debug
2021-07-07 23:18:59 +00:00
rename.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
rob.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
rob.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
SConscript
cpu: De-templatize the O3ThreadState.
2021-05-21 01:19:37 +00:00
SConsopts
scons: Turn the ISA and GPU ISA lists into construction variables.
2021-08-07 03:12:56 +00:00
scoreboard.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
scoreboard.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
store_set.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
store_set.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
thread_context.cc
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
thread_context.hh
cpu: Use RegVal for VecElems instead of TheISA::VecElem.
2021-08-11 04:48:02 +00:00
thread_state.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
thread_state.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00