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cpu: De-templatize the O3ThreadState.

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Change-Id: Ifa6342abe396e131ae8edcb8111453852cdbefd7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42118
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@huawei.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-03-03 05:06:35 -08:00
parent fda2e46a9e
commit f7902540e0
9 changed files with 93 additions and 67 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/o3/SConscript
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@@ -54,6 +54,7 @@ if 'O3CPU' in env['CPU_MODELS']:
Source('scoreboard.cc')
Source('store_set.cc')
Source('thread_context.cc')
Source('thread_state.cc')
DebugFlag('CommitRate')
DebugFlag('IEW')

2
src/cpu/o3/commit.cc
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@@ -243,7 +243,7 @@ DefaultCommit::CommitStats::CommitStats(FullO3CPU *cpu, DefaultCommit *commit)
}
void
DefaultCommit::setThreads(std::vector<Thread *> &threads)
DefaultCommit::setThreads(std::vector<O3ThreadState *> &threads)
{
thread = threads;
}

9
src/cpu/o3/commit.hh
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@@ -58,8 +58,7 @@
struct DerivO3CPUParams;
template <class>
struct O3ThreadState;
class O3ThreadState;
/**
* DefaultCommit handles single threaded and SMT commit. Its width is
@@ -86,8 +85,6 @@ struct O3ThreadState;
class DefaultCommit
{
public:
typedef O3ThreadState<O3CPUImpl> Thread;
/** Overall commit status. Used to determine if the CPU can deschedule
* itself due to a lack of activity.
*/
@@ -138,7 +135,7 @@ class DefaultCommit
void regProbePoints();
/** Sets the list of threads. */
void setThreads(std::vector<Thread *> &threads);
void setThreads(std::vector<O3ThreadState *> &threads);
/** Sets the main time buffer pointer, used for backwards communication. */
void setTimeBuffer(TimeBuffer<O3Comm::TimeStruct> *tb_ptr);
@@ -353,7 +350,7 @@ class DefaultCommit
FullO3CPU *cpu;
/** Vector of all of the threads. */
std::vector<Thread *> thread;
std::vector<O3ThreadState *> thread;
/** Records that commit has written to the time buffer this cycle. Used for
* the CPU to determine if it can deschedule itself if there is no activity.

11
src/cpu/o3/cpu.cc
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@@ -303,24 +303,19 @@ FullO3CPU::FullO3CPU(const DerivO3CPUParams &params)
if (FullSystem) {
// SMT is not supported in FS mode yet.
assert(numThreads == 1);
thread[tid] = new O3ThreadState<O3CPUImpl>(this, 0, NULL);
thread[tid] = new O3ThreadState(this, 0, NULL);
} else {
if (tid < params.workload.size()) {
DPRINTF(O3CPU, "Workload[%i] process is %#x", tid,
thread[tid]);
thread[tid] = new O3ThreadState<O3CPUImpl>(this, tid,
thread[tid] = new O3ThreadState(this, tid,
params.workload[tid]);
//usedTids[tid] = true;
//threadMap[tid] = tid;
} else {
//Allocate Empty thread so M5 can use later
//when scheduling threads to CPU
Process* dummy_proc = NULL;
thread[tid] = new O3ThreadState<O3CPUImpl>(this, tid,
dummy_proc);
//usedTids[tid] = false;
thread[tid] = new O3ThreadState(this, tid, dummy_proc);
}
}

2
src/cpu/o3/cpu.hh
View File

@@ -599,7 +599,7 @@ class FullO3CPU : public BaseCPU
System *system;
/** Pointers to all of the threads in the CPU. */
std::vector<O3ThreadState<O3CPUImpl> *> thread;
std::vector<O3ThreadState *> thread;
/** Threads Scheduled to Enter CPU */
std::list<int> cpuWaitList;

8
src/cpu/o3/dyn_inst.hh
View File

@@ -106,7 +106,7 @@ class BaseO3DynInst : public ExecContext, public RefCounted
BaseCPU *getCpuPtr() { return cpu; }
/** Pointer to the thread state. */
O3ThreadState<O3CPUImpl> *thread = nullptr;
O3ThreadState *thread = nullptr;
/** The kind of fault this instruction has generated. */
Fault fault = NoFault;
@@ -1014,11 +1014,7 @@ class BaseO3DynInst : public ExecContext, public RefCounted
void setTid(ThreadID tid) { threadNumber = tid; }
/** Sets the pointer to the thread state. */
void
setThreadState(O3ThreadState<O3CPUImpl> *state)
{
thread = state;
}
void setThreadState(O3ThreadState *state) { thread = state; }
/** Returns the thread context. */
ThreadContext *tcBase() const override { return thread->getTC(); }

2
src/cpu/o3/thread_context.hh
View File

@@ -94,7 +94,7 @@ class O3ThreadContext : public ThreadContext
}
/** Pointer to the thread state that this TC corrseponds to. */
O3ThreadState<O3CPUImpl> *thread;
O3ThreadState *thread;
/** Returns a pointer to the MMU. */
BaseMMU *getMMUPtr() override { return cpu->mmu; }

71
src/cpu/o3/thread_state.cc Normal file
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@@ -0,0 +1,71 @@
/*
* Copyright (c) 2012, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/o3/thread_state.hh"
#include "cpu/o3/cpu.hh"
O3ThreadState::O3ThreadState(FullO3CPU *_cpu, int _thread_num,
Process *_process) : ThreadState(_cpu, _thread_num, _process),
comInstEventQueue("instruction-based event queue")
{}
void
O3ThreadState::serialize(CheckpointOut &cp) const
{
ThreadState::serialize(cp);
// Use the ThreadContext serialization helper to serialize the
// TC.
::serialize(*tc, cp);
}
void
O3ThreadState::unserialize(CheckpointIn &cp)
{
// Prevent squashing - we don't have any instructions in
// flight that we need to squash since we just instantiated a
// clean system.
noSquashFromTC = true;
ThreadState::unserialize(cp);
// Use the ThreadContext serialization helper to unserialize
// the TC.
::unserialize(*tc, cp);
noSquashFromTC = false;
}

54
src/cpu/o3/thread_state.hh
View File

@@ -41,17 +41,13 @@
#ifndef __CPU_O3_THREAD_STATE_HH__
#define __CPU_O3_THREAD_STATE_HH__
#include "base/callback.hh"
#include "base/compiler.hh"
#include "base/output.hh"
#include <memory>
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#include "sim/full_system.hh"
#include "sim/sim_exit.hh"
class Event;
class FunctionalMemory;
class Process;
class FullO3CPU;
/**
* Class that has various thread state, such as the status, the
@@ -60,15 +56,8 @@ class Process;
* pointer, etc. It also handles anything related to a specific
* thread's process, such as syscalls and checking valid addresses.
*/
template <class Impl>
struct O3ThreadState : public ThreadState
class O3ThreadState : public ThreadState
{
typedef ThreadContext::Status Status;
private:
/** Pointer to the CPU. */
FullO3CPU *cpu;
public:
PCEventQueue pcEventQueue;
/**
@@ -85,46 +74,23 @@ struct O3ThreadState : public ThreadState
* lead to successive restarts and forward progress couldn't be made. This
* variable controls if the squashing will occur.
*/
bool noSquashFromTC;
bool noSquashFromTC = false;
/** Whether or not the thread is currently waiting on a trap, and
* thus able to be externally updated without squashing.
*/
bool trapPending;
bool trapPending = false;
/** Pointer to the hardware transactional memory checkpoint. */
std::unique_ptr<BaseHTMCheckpoint> htmCheckpoint;
O3ThreadState(FullO3CPU *_cpu, int _thread_num, Process *_process)
: ThreadState((BaseCPU *)_cpu, _thread_num, _process), cpu(_cpu),
comInstEventQueue("instruction-based event queue"),
noSquashFromTC(false), trapPending(false), tc(nullptr)
{
}
O3ThreadState(FullO3CPU *_cpu, int _thread_num, Process *_process);
void serialize(CheckpointOut &cp) const override
{
ThreadState::serialize(cp);
// Use the ThreadContext serialization helper to serialize the
// TC.
::serialize(*tc, cp);
}
void unserialize(CheckpointIn &cp) override
{
// Prevent squashing - we don't have any instructions in
// flight that we need to squash since we just instantiated a
// clean system.
noSquashFromTC = true;
ThreadState::unserialize(cp);
// Use the ThreadContext serialization helper to unserialize
// the TC.
::unserialize(*tc, cp);
noSquashFromTC = false;
}
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
/** Pointer to the ThreadContext of this thread. */
ThreadContext *tc;
ThreadContext *tc = nullptr;
/** Returns a pointer to the TC of this thread. */
ThreadContext *getTC() { return tc; }