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cpu: Fix TME for dyn_o3_cpu

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Commit c417b76 changed the behaviour of addRequest(),
but did not update documentation or the HTM-related logic that used it.

Updates documentation for addRequest() in light of c417b76,
refactors request class to be idiomatic and use assigned byteEnable,
made HTM cmds pass in a correct byteEnable.

Change-Id: I7aa8c127df896e81caf915fbfea93e7b4bcc53b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50147
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Samuel Stark
2021-08-23 15:57:00 +01:00
committed by Giacomo Travaglini
parent f4d8200178
commit 2c457d2a9f
3 changed files with 27 additions and 26 deletions
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6
src/cpu/o3/dyn_inst.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2011 ARM Limited
* Copyright (c) 2010-2011, 2021 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -301,9 +301,11 @@ DynInst::initiateMemRead(Addr addr, unsigned size, Request::Flags flags,
Fault
DynInst::initiateHtmCmd(Request::Flags flags)
{
const unsigned int size = 8;
return cpu->pushRequest(
dynamic_cast<DynInstPtr::PtrType>(this),
/* ld */ true, nullptr, 8, 0x0ul, flags, nullptr, nullptr);
/* ld */ true, nullptr, size, 0x0ul, flags, nullptr, nullptr,
std::vector<bool>(size, true));
}
Fault

41
src/cpu/o3/lsq.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2012, 2014, 2017-2019 ARM Limited
* Copyright (c) 2011-2012, 2014, 2017-2019, 2021 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -1374,6 +1374,16 @@ LSQ::HtmCmdRequest::HtmCmdRequest(LSQUnit* port, const DynInstPtr& inst,
SingleDataRequest(port, inst, true, 0x0lu, 8, flags_,
nullptr, nullptr, nullptr)
{
}
void
LSQ::HtmCmdRequest::initiateTranslation()
{
// Special commands are implemented as loads to avoid significant
// changes to the cpu and memory interfaces
// The virtual and physical address uses a dummy value of 0x00
// Address translation does not really occur thus the code below
assert(_requests.size() == 0);
addRequest(_addr, _size, _byteEnable);
@@ -1390,34 +1400,23 @@ LSQ::HtmCmdRequest::HtmCmdRequest(LSQUnit* port, const DynInstPtr& inst,
_inst->memReqFlags = _requests.back()->getFlags();
_inst->savedReq = this;
setState(State::Translation);
flags.set(Flag::TranslationStarted);
flags.set(Flag::TranslationFinished);
_inst->translationStarted(true);
_inst->translationCompleted(true);
setState(State::Request);
} else {
panic("unexpected behaviour");
panic("unexpected behaviour in initiateTranslation()");
}
}
void
LSQ::HtmCmdRequest::initiateTranslation()
{
// Transaction commands are implemented as loads to avoid significant
// changes to the cpu and memory interfaces
// The virtual and physical address uses a dummy value of 0x00
// Address translation does not really occur thus the code below
flags.set(Flag::TranslationStarted);
flags.set(Flag::TranslationFinished);
_inst->translationStarted(true);
_inst->translationCompleted(true);
setState(State::Request);
}
void
LSQ::HtmCmdRequest::finish(const Fault &fault, const RequestPtr &req,
gem5::ThreadContext* tc, BaseMMU::Mode mode)
{
panic("unexpected behaviour");
panic("unexpected behaviour - finish()");
}
Fault

6
src/cpu/o3/lsq.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2012, 2014, 2018-2019 ARM Limited
* Copyright (c) 2011-2012, 2014, 2018-2019, 2021 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -362,8 +362,8 @@ class LSQ
/** Helper function used to add a (sub)request, given its address
* `addr`, size `size` and byte-enable mask `byteEnable`.
*
* The request is only added if the mask is empty or if there is at
* least an active element in it.
* The request is only added if there is at least one active
* element in the mask.
*/
void addRequest(Addr addr, unsigned size,
const std::vector<bool>& byte_enable);