Commit Graph

17031 Commits

Author SHA1 Message Date
Srikant Bharadwaj
ef96d4cc5c mem-garnet: Change flitbuffer structure to deque
Flitbuffers act as FIFOs for internal links and output queues
in routers. This change replaces the use of vectors with deque
for performance improvements. The older implementation of using
a vector combined with a heap sort was both incorrect and
inefficient.

Incorrect because flit buffers should act strictly
as FIFO, sorting them based on time changes the order which affects
functionality in the case of DVFS enabled NoCs.

Change-Id: Ieba40f85628b7c7255e86792d40b8ce3d7ac34b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44286
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 18:04:42 +00:00
Srikant Bharadwaj
40c69e8f64 mem-garnet: Reduce complexity of data structures within SwitchAllocator
The switch allocator implements a two step separable allocator and
utilizes port winner and vc winner data structures for functionality.
This improves the data structures used and their operations to improve
overall performance of the simulation. We start with an invalid output
port(-1) and an invalid vc(-1) and then allocate the outports
and vcs to inport.

Change-Id: I38b70ebdc1a54b8f748c2a5d510814bf139b9eaa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44285
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 18:04:42 +00:00
Jui-min Lee
c4aad44a62 systemc: Fix tlm phase ordering in Gem5ToTlmBridge
Previously we only rely on timestamp to schedule all phase change events
of tlm transactions in Gem5ToTlmBridge. However, it is valid to have
END_REQ and BEGIN_RESP of a transaction to be scheduled at the same
timestamp and the gem5 scheduler will not necessary order them in a
correct way.

This unfortunately breaks the code as sending a response before
accepting a request doesn't make sense at all and will trigger an
assertion failure.

In this CL we slightly increase the priority of END_REQ event so we can
always process phase change events in a correct order.

Change-Id: Ic33a92162c8c53af3887c7b04090115a38f96866
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44305
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 16:46:59 +00:00
Giacomo Travaglini
d1e090eec4 arch-arm: Make TLB misses from a sw prefetch visible
While a TLB hit caused by a prefetching operation is visible in terms
of TLB stats update, this is not the case for a TLB miss, which is
invisible to the stats as it is now.

This patch is realigning the behaviour to be more consistent: we will
always update the stats regardless of whether the access caused a
TLB hit/miss

Change-Id: I161e04fc09a0dbba7468a52848aa7710d1476e19
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37955
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 15:50:22 +00:00
Daniel R. Carvalho
e7e03df9a9 cpu-o3: Fix missing overrides
Fix missing overrides in SimpleTrace.

Change-Id: I82ed2a10c98ea67dde7b99db13c0ad5d9ed96f0f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44405
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-14 00:09:06 +00:00
Hoa Nguyen
f8d8547575 util: Add missing parameter for print_insts
JIRA: https://gem5.atlassian.net/browse/GEM5-949

Change-Id: I74fe7adc06124d193f17d682882766484ac18528
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44448
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 08:40:10 +00:00
Hoa Nguyen
004692487f util: Make o3-pipeview Python3 compatible
JIRA: https://gem5.atlassian.net/browse/GEM5-955

Change-Id: I48cb0bfb784eafe2057eb1095e6aad7abf9a1bc9
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44447
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 08:40:03 +00:00
Giacomo Travaglini
12fa117ed2 tests: Define a MatchFileRegex verifier
Using it as a base class for MatchRegex.
While the latter is using a regex to scan the stdout and stderr files,
MatchFileRegex is more generically allowing you to specify which file to
scan at __init__ time.

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I2a64dab9c88a632b0a6b400ba02aafe473b3e62d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44445
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 08:01:17 +00:00
Yu-hsin Wang
7f91f4726a systemc: Eliminate ClockTick duplicated name warning
In systemc, a module name is consist of hierarchy names with dot
separated. The basename is the last part of the module name. Because
lack of hierarchy information, it's a chance that the basename is
duplicated. Although, ClockTick is using sc_gen_unique_name to solve
this, the warning from sc_gen_unique_name is annoying. To solve this
completely, we should use the full module name to construct the name of
ClockTick.

Change-Id: Ie664fe4757a05f72860be49c3a9d1172f824eb2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44425
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 07:39:35 +00:00
Yu-hsin Wang
2cbf4170c9 systemc: Fix verify.py and make it python 3 compatible
1. The logger behavior change breaks verify.py.
commit 8deb205ea1
Author: Daniel Carvalho <odanrc@yahoo.com.br>
Date:   Wed Mar 3 16:49:05 2021 -0300

    base: Add LOC to Loggers

    Printing the line and the file that triggered a log
    is useful for debugging.

    Change-Id: I74e0637b2943049134bd3e9a4bc6cab3766591a9
    Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
    Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42141
    Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
    Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
    Tested-by: kokoro <noreply+kokoro@google.com>

2. Use bytes diff in LogChecker.
In Python3, string is required to be in a certain encoding, while in Python2,
it is not. In the testcase, misc/cae_test/general/bitwise/or/datatypes,
it contains some invalid codepoint of utf-8, we need diff the log with
bytes in Pyhton3.

3. Python3 compatible.
* dict.iteritems -> dict.items
* remove object base class
* use `except as` when catching exceptions
* handle map and filter behavior change

Test with

src/systemc/tests/verify.py --update-json build/ARM -j `nproc` \
  --filter-file src/systemc/tests/working.filt

src/systemc/tests/verify.py --update-json build/ARM -j `nproc` \
  --filter-file src/systemc/tests/working.filt --phase verify --result-file

Change-Id: Ibf5b99d08a948387cf6162c476c294c49a7dac0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44465
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 07:39:35 +00:00
Gabe Black
c2f71c71d2 scons,systemc: In clang <= 6, -Wno-self-assign-overloaded doesn't exist.
In those versions of clang, use -Wno-self-assign.

Change-Id: Ic4f2fba6881f65fd40d0a4f3d3fb76574614b29a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44385
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-04-13 01:05:03 +00:00
Gabe Black
960b9246c5 scons: Convert gem5_scons.Configure to a context manager.
This has two purposes. First, SCons assumes that once you call
Configure, you won't set up the environment the Configure is based on
until after you get the environment back from it again with
conf.Finish(). We get away with this when the cache mode for config
tests is not "force", since Configure just reuses the environment we
pass in, and any changes we make are immediately communicated between
the two.

If the cache mode *is* "force" though, SCons modifies the decider so
that everything the conf environment goes to build looks like it's out
of date. It does that by cloning the original environment, and then
using that clone to do its tests. That causes a problem because we have
a long lived "conf" object and make further changes to main, and since
the two environments are now separate the one in conf doesn't see those
updates.

Second, and more subtly, we export our "main" and "env" environments so
that other SConsopts and SConscript files can use them and define things
in them. The way Configure is designed, if the config caching mode is
"force", then it will create a new environment, and then that
environment will replace what the, for instance, "main" variable points
to when "main = conf.Finish()" is executed.

Unfortunately, if we've already Export()-ed main, we've exported what
the "main" variable pointed to at that time. Our view of "main" will
track with the value that conf.Finish() returned, but since that
construction environment is mearly derived from the main we Exported and
not actually the same thing, they have diverged at that point and will
behave independently.

To solve both of these problems, this change modifies the
gem5_scons.Configure() method so that it's a context manager instead of
a regular function. As before, it will call Configure for us and create
a configuration context, which it will yield as the "with" value. When
the context exits, all the variables in the context Finish() returns
will be shoved back into the original context with Replace(). This isn't
perfect since variables which were deleted in the environment (probably
very rare in practice) will not exist and so will not overwrite the
still existent variable in the original dict.

This has several advantages. The environment never splits into two
copies which continue on independently. It makes the lifetime of a
configuration context short, which is good because behavior during that
time is tricky and unintuitive. It also makes the scope of the context
very clear, so that you won't miss the fact that you're in a special
setting and need to pay attention to what environment you're modifying.

Also, this keeps the conceptual overhead of configuration localized to
where the configuration is happening. In parts of the SConscripts which
are not doing anything with conf, etc, they don't have to modify their
behavior since no configuration context is active.

This change is based on this change from Hanhwi Jang who identified this
problem and proposed an initial solution:

https://gem5-review.googlesource.com/c/public/gem5/+/44265

Change-Id: Iae0a292d6b375c5da98619f31392ca1de6216fcd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44389
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Hanhwi Jang <jang.hanhwi@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-13 01:04:54 +00:00
Giacomo Travaglini
7c2140f576 tests: Add realview-kvm-dual regression
This is to test multiple KVM vCPUs

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ied4f578bcf8d30f9c1738aa1c4265220e78589e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44326
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-12 13:13:17 +00:00
Giacomo Travaglini
0b8564f5b2 tests: Allow multi-KvmCPU regressions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I3207074e794385528b680e54eaa9a536aef9eb43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44325
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-12 13:13:17 +00:00
Gabe Black
1f41f50c9a fastmodel: Call the base class initFromIrisInstance in the R52.
In the CortexR52 model in the initFromIrisInstance method, call into
the base classes version of that function to ensure some basic, common
setup is performed.

Change-Id: I43198578ce1057d63d8e72d66b5370bf4d1ccd4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43545
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-12 12:27:19 +00:00
Daniel R. Carvalho
0a80511aea dev: Fix compilation errors
'backing' was initialized after being used.
'buffer' was initialized after its data() was used
by the constructor.

Change-Id: I0f8d0f6efb5d4b7abc5fc6c2c3ecca2c9b0a2eaf
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44366
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-12 12:23:34 +00:00
Eduardo José Gómez Hernández
a6fc2797e8 arch-x86: Fixed locked cmpxchg8b allows reordering
Locked versions of cmpxcgh8b (and cmpxcgh16b) should
be guarded by mfences to prevent reordering from
surrounding memory instructions.

Change-Id: I4a04bb871b4f9a38efd78df194b43f785d5d2236
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44166
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-12 08:01:50 +00:00
Gabe Black
ae09f19fc8 arch-arm: Add a message to a static_assert in isa.hh.
static_asserts without a message are a c++17 feature.

Change-Id: I9d8b5f5a0d7f9b83784f0480afab0f534a466ee5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44386
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2021-04-11 22:17:31 +00:00
Gabe Black
0abef82db8 python: Don't try setting the parent of null SimObject pointers.
The line of code which would have added the null SimObject as a child
was already guarded by an if, but the line before it which would set the
parent of the null SimObject itself was not. This change moves it into
the if as well.

Change-Id: Icfbc0e87e0ab55917735f720de4e94c19185df46
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44387
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-11 22:16:52 +00:00
Gabe Black
6334ef4701 python: If a SimObject already has a parent, don't add it as a child.
The SimObject will have already been added to the other object's list
of children, and if it's given a new parent, it will be added as a
child to the new parent as well. The object will then be the child of
two other SimObjects which will cause a delightful variety of hard to
debug problems.

Another slightly better way to handle this situation would be to both
move to the new parent and also remove the SimObject from the original
parent's list of children. Unfortunately there isn't a simple way to
figure out what the parent called the child, and so we would have to
look through its children one by one until we found the right one.

Change-Id: I8f43dfab7adf58a43f806390a0c7c35a2efde11a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43905
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-11 22:16:40 +00:00
Daniel R. Carvalho
1525ee8cdd util: Fix cpt_upgrader
This had multiple issues related to the upgrade
to Python 3.

Change-Id: Iebac5618a05d7c3ad08b34652bf2ba08a82b5948
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44105
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-04-11 14:09:24 +00:00
Daniel R. Carvalho
667cad35db arch-riscv: Fix braces around scalar initializer
clang complains that this scalar should not be
surrounded by braces.

Change-Id: Id399d7fbe06f3edaa1e1d569f968cd1674b2ac1d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44365
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-10 23:28:16 +00:00
Gabe Black
bdb941b6d7 arch: Remove unnecessary "typename"s from VecPredRegT.
Change-Id: If38e71ac79105b111d68df1e572f9a8e32a131ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41998
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-10 07:55:09 +00:00
Gabe Black
0dade68dae arch,cpu,gpu-compute: Further simplify VecRegContainer.
Get rid of VecRegT, and a few redundant or unused methods.

Change-Id: I6c88c40653e1939fe74b8ffb847ef50ab8064670
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41995
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-10 07:31:23 +00:00
Gabe Black
0e455475c8 arch-power: Pull non-public information out of registers.hh.
Also create a regs/ directory for register related headers.

Change-Id: Id376597b7b6254b26c05aa94e0141abacd807c79
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41740
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-04-10 01:11:21 +00:00
Gabe Black
a580e08426 arch-arm: Pull everything not purely public out of registers.hh.
There are currently only two types of values exported from registers.hh,
vector register definitions, and the zero reg index. The ZeroReg
constant is still defined in registers.hh. The vector register
information has been moved into a new file called arch/arm/regs/vec.hh
since it's used internally by the ISA itself, and then included in
registers.hh so it can be consumed externally too.

Change-Id: I31d8dd5bcb21818efa32ccc42f26b0e598a2c88e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41738
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-04-10 01:10:57 +00:00
Giacomo Travaglini
6cb9c3e87f sim: Fix Temperature class
* Adding __str__ method: To fix its printing on config.ini
(Replacing <m5.params.Temperature> with the Temperature value)

* Replacing "fromKelvin" with from_kelvin
(that's how pybind exports it)

* Fixing config_value to allow JSON serialization
(JIRA: https://gem5.atlassian.net/browse/GEM5-951)

Change-Id: I1aaea9c9df6466a5cbed0a29c5937243796948d2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44167
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-09 23:12:00 +00:00
Bobby R. Bruce
291bc67ef1 misc,mem-ruby: Fixing unused variable error for fast builds
This fixes the broken compiler tests for .fast builds:
https://www.mail-archive.com/gem5-dev@gem5.org/msg38412.html

Change-Id: Ibc377a57ce6455ca709003f326b0ca8d4c01377b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44086
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-07 16:55:22 +00:00
Giacomo Travaglini
b3af12ccd5 dev-arm: Align gem5 to FVP Base PCI
The VExpress_GEM5_Foundation platform was reserving
a region of the memory map (@ 0x4 0000 0000) for PCI.

The Armv8-A FVP Foundation platform is not PCI capable at
the moment, so any PCI logic is really gem5 specific.
With this patch we are aligning gem5 to the FVP Base Platform,
which supports PCI and it is reserving 256GiB of memory
starting at 0x40 0000 0000 (256GiB).

Fast Models - Reference Manual - Version 11.8

At the moment we are still supporting a single DRAM range,
starting at 2GiB. So DRAM could overlap with the PCI memory
region though it is unlikely to happen in near future as
it would require a DRAM size > 254 GiB.

JIRA: https://gem5.atlassian.net/browse/GEM5-898

Change-Id: I506fd6696cdddc39d057602581cb16b30db3f7c7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44165
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2021-04-07 09:09:49 +00:00
Giacomo Travaglini
e30378e2d2 configs: Add --kvm-userspace-gic to fs_bigLITTLE.py
This will allow a user to select gem5 simulation of the GIC via
command line; Necessary option when the simulated GIC != than the
host GIC

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I30e151b774ddfa7f4e91054a375254e15007af3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44006
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-07 08:21:28 +00:00
Daniel R. Carvalho
d67f28473a util: Revamp opening brace verifier
1 - Rename the verifier from ClassBraces to
StructureBraces.

2 - Add support for anonymous structures. This
includes anonymous classes, anonymous structs,
anonymous enums and anonymous unions. e.g.:

  struct {

3 - Make the verifier not trigger error for
structures that do not currently abide to gem5's
coding style and use non-uppercase characters as
their first character. e.g.:

  struct test {

4 - Improve handling of nested structures. e.g.:

  struct { enum { VAR, VAR2

becomes

  struct
  {
      enum {
          VAR, VAR2

But the verifier will fail for declarations like:

  struct { int a; }; struct {

which becomes

  struct
  {
      int a; struct {

However, this later issue is not a desired coding
style, so it should be handled by another kind of
verifier if desired.

Change-Id: I8f0536dcc2c164e2d3d2a2e5b7a35d5ee351a814
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43365
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-04-07 01:37:12 +00:00
Daniel R. Carvalho
5c8983fc18 misc: Fix remaining opening braces
These were not caught by the previous patches because
the grep used ignored:
- anonymous structures
  (e.g., "struct {")
- opening braces without leading spaces
  (e.g., "struct Name{"),
- weird chars in auto-generation files
  (e.g., "struct $name {").
- extra characters after the opening brace.
  (e.g., "struct Name { // Comment")
- typedefs (note that this is not caught by the verifier)
  (e.g., "typedef struct Name {")

Most of this has been fixed be grepping structures
with the following regex:
  grep -nrE --exclude-dir=systemc \
    "^ *(typedef)* *(struct|class|enum|union) [^{]*{$" src/

The following makes sure that "struct{" is captured:
  grep -nrE --exclude-dir=systemc \
    "^ *(struct|class|enum|union){" src/

To find cases that contain a comment after the
opening brace:
  grep -nrE --exclude-dir=systemc \
    "^ *(struct|class|enum|union)[^{]*{\s*//" src/

Change-Id: I9f822bed628d13b1a09ccd6059373aff63a8d7bd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43505
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-07 01:29:31 +00:00
Giacomo Travaglini
5e24869079 configs: Do not assume single mem range in RealView
The SimpleSystem was assuming a single memory range for RealView
platforms by selecting the first element of the list only:

mem_range = self.realview._mem_regions[0]

This patch is fixing this by evaluating the entire list of platform
ranges.

Change-Id: I453fff7857966076c1419b95ddb9177e51d9f8d5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39636
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-06 08:48:50 +00:00
Ayaz Akram
95fdb9f3c4 arch-riscv: Add riscv pmp support
This change adds the pmp (physical memory protection)
feature of riscv previliged isa.

Change-Id: Ica701223cfc1be91a0bf953e6a3df6d72d6d3130
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43945
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Peter Yuen <petery.hin@huawei.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-05 04:18:12 +00:00
Gabe Black
0877e5125c base: Report actual thread numbers to remote GDB.
This is more accurate, and will help when the GDB stub is able to manage
multiple threads through the same connection.

Change-Id: Ica04a8e2b5e93ca254fb2c2e1b44075634a69b9c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44029
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-03 14:03:20 +00:00
Gabe Black
ea631194d9 scons: Eliminate the useless USE_SSE2 flag.
This option would set the -msse2 compiler flag to avoid using x87
floating point, but every 64 bit x86 CPU supports sse2, and so sse2 is
enabled by default on compilers targeting it. 32 bit x86 CPUs are
obscure enough that it's not worth preserving this marginally meaningful
option which would only matter for them.

Change-Id: Ib425c261b27f1f74300e714619787d04970065ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40879
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-03 14:03:10 +00:00
Gabe Black
ab19f3c560 Revert "arch-arm: Use src/base/fenv.hh instead of raw fenv.h."
This reverts commit 8ff1dd9c9b.

Reason for revert: gerrit allowed rebasing this out of the original order, but it doesn't build without another uncommitted change going in first.

Change-Id: I678a22154b539691a962b4a686333cacf98731de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44065
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-03 14:03:04 +00:00
Gabe Black
0d569c559b scons: Streamline the LTO option setting code and add options for clang.
Clang also supports an -flto option, although not with a thread count.

Change-Id: Ifc783ac3ab2e0ea93fad0402b288605a20725aa0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40962
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-03 05:53:31 +00:00
Gabe Black
59e0ce27a3 scons: Include libthr on freebsd no matter what compiler you're using.
The compiler won't change where the thread library is implemented.

Change-Id: Ic6fbaae2ff9c4a91ce86b06d62049b9d9a0e3132
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40960
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: B.A. Zeeb <baz21@cam.ac.uk>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-03 05:53:17 +00:00
Gabe Black
dd0d54d749 scons: Narrow the scope of the -Wno-parentheses flag.
This was added to avoid warnings from code generated as part of Ruby's
AST. Instead of applying this to all of gem5, apply it only to files
generated by Ruby.

Change-Id: I2b11d2df3cb631debdc594059d9d480a0e695c59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40958
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-03 05:53:01 +00:00
Gabe Black
b464d16444 ext: Fix an operator precedence bug in the nomali library.
An expression in that library intended to create a bitmask by checking
if a bit should be set, and then using ?: to select between a bitmask
with that bit, or 0. Unfortunately | is higher precedence than ?:, and
so 0 would be |-ed with the condition of the next ?: instead. This CL
fixes the bug by adding some parenthesis.

Change-Id: Ib7e06f261e07a6ad00b9a96939d07b64c3a50409
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40954
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-03 05:52:43 +00:00
Gabe Black
c017caad88 scons: More narrowly target -Wno-self-assign.
This flag was necessary because of self assignments in the ISA parser
where self assignments are often hints to the parser itself, and in one
case because a pybind-ism used to attach the -= operator looked like a
self assignment.

This change narrows the scope of the flag that disables this warning to
only files generated by the ISA parser, and the single file in the
systemc code which uses that operator overload.

Change-Id: Ib64fc72e46f894cba9064afcdbdcc5859c30e745
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40952
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-03 05:52:24 +00:00
Gabe Black
64d71220d1 scons: Delete unnecessary imports from SConstruct.
Also get rid of the joinpath and splitpath aliases for os.path.join and
os.path.split. The aliases are only slightly shorter, and obscure these
extremely common python methods.

Change-Id: I0784e2d8dbaacb0690a59e9fa8c8258c1df0e6c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40874
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-03 05:51:35 +00:00
Kyle Roarty
c734ab7602 dev-hsa,gpu-compute: Fix override for updateHsaSignal
Change 965ad12 removed a parameter from the updateHsaSignal
function. Change 25e8a14 added the parameter back, but only for the
derived class, breaking the override. This patch adds that parameter
back to the base class, fixing the override.

Change-Id: Id1e96e29ca4be7f3ce244bac83a112e3250812d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44046
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Alex Dutu <alexandru.dutu@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
2021-04-03 02:39:27 +00:00
Gabe Black
8ff1dd9c9b arch-arm: Use src/base/fenv.hh instead of raw fenv.h.
This provides a layer of indirection where the rounding mode
setting/getting code will do nothing if fenv.h isn't available. At build
time, if fenv.h can't be found, a warning is printed.

Also, the include for fenv.h was guarded in the includes in the ISA
header, but the functions from it weren't guarded in the actual code.

Finally, the code was setting the rounding mode, but not setting it
back. That would mean running these instructions would set the rounding
mode in gem5 as a whole, affecting its other behaviors and any other
instructions that might expect the default rounding mode.

Change-Id: Ic5cc32773652f423e66d78f31b80c6604f2c4a49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41214
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2021-04-03 01:34:21 +00:00
Gabe Black
1791b8732c scons: Pull domain specific build setup out of SConstruct.
Use SConsopts files local to individual domains to pull
non-foundational build code out of SConstruct. This greatly simplifies
SConstruct, and also makes it easier to find build configuration having
to do with particular pieces of gem5.

This change also converts some python level variables, all_protocols,
protocol_dirs, and slicc_includes, into the environment where the timing
of their initialization is more flexible.

Change-Id: Ie61ceb75ae9e5557cc400603c972a9582e99c1ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40872
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
2021-04-03 01:18:17 +00:00
Jason Lowe-Power
91f4ea6683 python: Improve type annotations in pystats
This fixes some errors and warning when running mypy.

`gem5/src/python/m5/ext> mypy pystats`

There is one error that is ignored, which is a bug in mypy. See
https://github.com/python/mypy/issues/6040

Change-Id: I18b648c059da12bd30d612f0e265930b976f22b4
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42644
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-02 20:47:35 +00:00
Ayaz Akram
2dfa2ddc6f arch-riscv,util: update riscv crosstool-ng config and m5 README entry
Change-Id: I751a6c97a0ac97f7b3fce360577d0ee16f29fda4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44032
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-02 20:45:12 +00:00
Kyle Roarty
df5ddabc03 gpu-compute: Fix scalar register ready check
Replaces some curly braces that were accidentally removed
causing the function to return false even when it shouldn't

Change-Id: I15fb4167468c8e3dd1107f1ca3dc98c48df4611b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44045
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Alex Dutu <alexandru.dutu@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-02 20:12:29 +00:00
Hoa Nguyen
e6b62c0252 configs: Make MemConfig.py compatible with Python3
Change-Id: I0c180fca18a19412348cbb90837825e7b6b544c6
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44047
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-02 19:06:25 +00:00