Commit Graph

73 Commits

Author SHA1 Message Date
Hoa Nguyen
cf087d4d11 arch-riscv: Add PCEvent for RISCV FS Workload kernel panic/oops
Inspired by a similar feature in ARM's full system workload, this change adds
an option to halt gem5 simulation if the guest system encounter kernel panic
or kernel oops.

On RiscvISA::BootloaderKernelWorkload, by default, the simulation
will exit upon kernel panic, while kernel oops will not induce simulation halt.
This is because the system will essentially do nop after a kernel panic, while the
system might be still functional after a kernel oops.

Dumping kernel's dmesg is useful for diagonizing the cause of kernel panic, so
ideally, we want to dump the guest's dmesg to the host. However, due to a bug
described in [1], kernel v5.18+ dmesg might not be dumped properly. Hence, the
dmesg will not be dumped to the host.

On RiscvISA::FsLinux, this feature is turned off by default as the symbols from the
official RISC-V kernel resource are stripped from the binary. However, if this feature
is enable, the dmesg will be dumped to the host system.

[1] https://github.com/gem5/gem5/issues/550

Change-Id: I8f52257727a3a789ebf99fdd4dffe5b3d89f1ebf
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
Co-authored-by: Jason Lowe-Power <jason@lowepower.com>
2023-12-04 14:59:26 -08:00
Bobby R. Bruce
21919addca Fix for gem5 Issue #550 (#636)
This Pull-Request addresses gem5 Issue #550. The code that dumps the
Dmesg buffer is now templated on the two variants of the `Metadata`
structure, and the correct one is chosen based on the detected Kernel
version.

To support this functionality, the pull request also adds Symbol Size
data to the loader Symbol Table, and adds a method to query the Kernel
Version from the image in guest memory. The new attributes in the Symbol
class are de-serialized speculatively, so no checkpoint upgrader is
required to support this change.
2023-12-01 18:06:20 -08:00
Richard Cooper
2fbbdad618 base: Add encapsulation to the loader::Symbol class
This commit converts `gem5::loader::Symbol` to a full class with
private members, enforcing encapsulation. Until now client code has
been able to (and does) access members directly.

This change will enable class invariants to be enforced via accessor
methods.

Change-Id: Ia0b5b080d4f656637a211808e13dce1ddca74541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2023-12-01 22:00:26 +00:00
Hoa Nguyen
bbe5216d88 arch-riscv: Rename BootloaderKernelWorkload parameters
The gem5 standard library hardcoded some parameters of the workload.
E.g., the kernel filename must be `object_file`.

Change-Id: I5eeb7359be399138693eaba0738eaf524c59408f
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-12-01 07:28:30 +00:00
Hoa Nguyen
4fdfb96cad arch-riscv: Load function symbols for BootloaderKernelWorkload
Change-Id: Iade91b2cdf6701ed3fe6f5583127c8c3d669d695
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-10-30 21:36:34 +00:00
Hoa Nguyen
0218103162 arch-riscv: Correct BootloaderKernelWorkload symbol table (#511)
Currently, the kernel's symbols are shifted by `kernel_paddr_offset`,
which is where the kernel is located in the physcial address space.
However, the symbols are mapped to virtual addresses, which stay the
same even though the physical address space is shifted.

This patch removes the offset for the kernel's symbols virtual
addresses.

Change-Id: I7c35f925777220f56bd8c69bba14c267d2048ade

Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-10-30 09:56:10 -07:00
Hoa Nguyen
3fc6b67974 arch-riscv: Add several inform() to RiscvISA::BootloaderKernelWorkload
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-10-06 00:45:21 -07:00
Hoa Nguyen
46a9d85215 arch-riscv: Add bootloader+kernel workload
Aims to boot OpenSBI + Linux kernel.

Change-Id: I9ee93cc367e8c06bdd0c7ddf43335d32965be14d
Signed-off-by: Hoa Nguyen <hn@hnpl.org>
2023-10-06 00:33:05 -07:00
Roger Chang
f2562152e8 arch-riscv,sim-se: Support RV32 register ABI call
1. Add RegABI32, SyscallABI32
2. Support parse function arguments to host and save result to registers
3. Add write to ThreadPointerReg in archClone
4. Support RV32 M5Op syscall

Change-Id: Ie327b517f41b5d633d2741b6abb5be955281c838
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65532
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2023-02-02 04:50:04 +00:00
Earl Ou
5bf88bf7a1 sim: allow specifying remote gdb port for each workload
In a platform with multiple systems, we may want to specify the
remote gdb port for each system. This change makes it
possible to specify the port number at each Workload instance.

Change-Id: I755b3960ee920ae5289819aa05d98902614a5615
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65151
Maintainer: Earl Ou <shunhsingou@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-11-03 05:34:09 +00:00
Jason Yu
e501078787 sim-se,arch-riscv: Fixes file-related flags for riscv64 target
Previous file-related flags for the riscv64-unknown-linux-gnu target
do not match the actual
values, leading to incorrect behaviours in certain emulated syscalls.
This commit fixes the problem.

Change-Id: I38ff624c00e46e37672510af5a10f527b5f0842a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64472
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
2022-10-14 17:18:06 +00:00
Gabe Black
0fa9bc0780 arch-riscv: Revamp int regs.
Change-Id: Ie4773178843757acede4fe9e77ca327f7b024270
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49772
Reviewed-by: Boris Shingarov <shingarov@labware.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2022-06-20 04:03:52 +00:00
Hoa Nguyen
96870d4713 arch-riscv: Fix compilation error due to getdents* syscalls
In src/sim/syscall_emul.*, getdents and getdents64 are guarded
by #ifdefs. Similar #ifdefs should be in se_workload.cc for each
arch.

Change-Id: Ie636a739235711c3e6d8256fd7929b7d8b4ec953
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60189
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-06-01 18:31:14 +00:00
Luming Wang
b3f1e5f9d7 sim-se: add getrandom() syscall support
getrandom() was introduced in version 3.17 of the Linux kernel.
This commit implements getrandom() for Gem5 SE mode.

Change-Id: I86bfeee52048184dbf72330284933b70daab5850
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57809
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2022-03-22 02:05:32 +00:00
Luming Wang
8cd70b7da1 arch-riscv,sim-se: correct the spelling of sendto
The system call "sendto" is incorrectly written as "sendo".
This patch fixes this spelling error and adds support for `sendto`.

Change-Id: I21851fe7679509161b09d335a5df9640c8334430
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56689
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2022-02-11 03:33:02 +00:00
Luming Wang
1f155ffd90 arch-riscv,sim-se: Complements the system calls on RISC-V
There are many SE mode system calls that are implemented
in src/sim/syscall_emul.cc or src/sim/syscall_emul.hh.
And they work well under X86 and ARM platforms. However,
they are not supported in se_workload.cc under the RISC-V
platform. This patch adds support for all the system calls
already implemented in syscall_emul.hh/cc to the RISC-V
platform (in arch/riscv/linux/se_workload.cc).

Change-Id: Ia47c3c113767b50412b1c8ade3c1047c894376cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54803
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
2022-01-05 03:25:58 +00:00
Gabe Black
5e3226bed5 arch,sim: Add a byteOrder accessor to the Workload class.
The workload would have a better idea of what it's endianness is than
the system object that holds it. This is the first step towards getting
rid of the getByteOrder method on the system object, which currently
checks TARGET_ISA to determine what the default endianness should be.

If it makes sense for a Workload, it could determine the endianness
dynamically by, for instance, reading it out of a binary image before
putting it into memory.

This does assume that the workload has a consistent endianness
throughout which may not be true, but this is not a new assumption.

Also, mark the SEWorkload SimObject class as "abstract", since it isn't
useful until they get subclassed by some arch specific version.

Change-Id: I8d4ba8382f22236a81f9738cc3506cdb97bdbfb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52104
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-11-18 07:09:00 +00:00
Giacomo Travaglini
851e543b2f misc: Using OS::off_t in syscall signature
Change-Id: Iefa1e207a3e825959b0fe8df30e6be182d73a0f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51490
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 07:44:00 +00:00
Giacomo Travaglini
37495f8823 misc: Using OS::size_t in syscall signature
Using the host size_t is confusing the guest ABI engine every time
the host and the guest adopt a different data model (ILP32 vs LP64)

For example when a LP64 machine is running an ILP32 application in SE
mode, "size_t" will wrongly inform the guest ABI engine to retrieve the
argument by loading a 64 bit (instead of 32) value from the stack

JIRA: https://gem5.atlassian.net/browse/GEM5-1074

Change-Id: Id7d7740ac429f534a4089331bedf21dc3951bbad
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51489
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-10-13 07:44:00 +00:00
Gabe Black
1a1ba692c3 sim: Move the MemPools object out of System and into SEWorkload.
This removes the need for all the FullSystem checks in the System class,
and simplifies that class in general.

Change-Id: Ie8a3bc67db9195027d2111009b15ca59221bdeb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50348
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-09-30 00:30:49 +00:00
Gabe Black
1c7c825757 arch,kern: Use CRTP to build open flags tables, not macros.
Change-Id: I433c064c66254c6e082fd6e37b4364576c2fbc3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45903
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-07 18:05:51 +00:00
Gabe Black
d58b4f004e misc: Remove typedef (struct|enum) Foo in cpp files.
In C, to refer to a type without a struct or enum tag on the type, you
need to typedef it like this:

typedef struct
{
} Foo;

Foo foo;

In C++, this is unnecessary:

struct Foo
{
};

Foo foo;

Remove all of the first form in C++ files and replace them with the
second form.

Change-Id: I37cc0d63b2777466dc6cc51eb5a3201de2e2cf43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46199
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-07 08:35:12 +00:00
Daniel R. Carvalho
974a47dfb9 misc: Adopt the gem5 namespace
Apply the gem5 namespace to the codebase.

Some anonymous namespaces could theoretically be removed,
but since this change's main goal was to keep conflicts
at a minimum, it was decided not to modify much the
general shape of the files.

A few missing comments of the form "// namespace X" that
occurred before the newly added "} // namespace gem5"
have been added for consistency.

std out should not be included in the gem5 namespace, so
they weren't.

ProtoMessage has not been included in the gem5 namespace,
since I'm not familiar with how proto works.

Regarding the SystemC files, although they belong to gem5,
they actually perform integration between gem5 and SystemC;
therefore, it deserved its own separate namespace.

Files that are automatically generated have been included
in the gem5 namespace.

The .isa files currently are limited to a single namespace.
This limitation should be later removed to make it easier
to accomodate a better API.

Regarding the files in util, gem5:: was prepended where
suitable. Notice that this patch was tested as much as
possible given that most of these were already not
previously compiling.

Change-Id: Ia53d404ec79c46edaa98f654e23bc3b0e179fe2d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/46323
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-07-01 19:08:24 +00:00
Daniel R. Carvalho
9f55bb8478 base: Rename Loader namespace as loader
As part of recent decisions regarding namespace
naming conventions, all namespaces will be changed
to snake case.

::Loader became ::loader.

Change-Id: Ifddf11ab4d5d7358032fbc523bc923c0a9feedbd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45424
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-29 11:13:49 +00:00
Gabe Black
9f547559d8 arch,base,sim: Move GDB stub creation into the arch Workloads.
These classes know what flavor of GDB stub they want, so there's no need
for TheISA:: to multiplex.

Change-Id: Ia428fe391719a3320d865421fc59352a17875bcf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44619
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-28 07:56:19 +00:00
Gabe Black
7186fc4c2d arch,kern,sim: Use a map to map syscall flags.
Use a std::map to map target syscall flag bits to host flag bits. This
avoids having to track the number of elements in the map separately.

Change-Id: I43bd54f5286f11b9635d46240a55742ddfdb0901
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45899
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-05-28 00:46:56 +00:00
Daniel R. Carvalho
10c0fb84ad arch: Rename some linux loader variables as linuxLoader
Pave the way for a loader namespace.

Change-Id: Ie7c811e74424063ff773569e7ad9df9dde166d4f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45422
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
2021-05-21 23:10:39 +00:00
Daniel R. Carvalho
5c8983fc18 misc: Fix remaining opening braces
These were not caught by the previous patches because
the grep used ignored:
- anonymous structures
  (e.g., "struct {")
- opening braces without leading spaces
  (e.g., "struct Name{"),
- weird chars in auto-generation files
  (e.g., "struct $name {").
- extra characters after the opening brace.
  (e.g., "struct Name { // Comment")
- typedefs (note that this is not caught by the verifier)
  (e.g., "typedef struct Name {")

Most of this has been fixed be grepping structures
with the following regex:
  grep -nrE --exclude-dir=systemc \
    "^ *(typedef)* *(struct|class|enum|union) [^{]*{$" src/

The following makes sure that "struct{" is captured:
  grep -nrE --exclude-dir=systemc \
    "^ *(struct|class|enum|union){" src/

To find cases that contain a comment after the
opening brace:
  grep -nrE --exclude-dir=systemc \
    "^ *(struct|class|enum|union)[^{]*{\s*//" src/

Change-Id: I9f822bed628d13b1a09ccd6059373aff63a8d7bd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43505
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-04-07 01:29:31 +00:00
Bobby R. Bruce
502ad193ae misc: Merge branch v21.0.0.0 into develop
This incorporates the last of the v21.0 staging branch changes into the
develop branch.

Change-Id: I89349ac5c52fd454eb87d6199ea5ccde0d50dda3
2021-03-25 14:42:27 -07:00
Peter Yuen
39108150ab arch-riscv: Added DTB Generation Functionality to RISC-V FS
Changes:
1. RiscvBareMetal
The RiscvBareMetal class and API are preserved for backwards
compatibility, but the base class RiscvFSWorkload is removed
as it inherits from the Workload class. However, most needed
functionalities are already implemented in the KernelWorkload
class

2. RiscvLinux
The RiscvLinux class is added. A dtb filename can be specified
to be loaded to the corresponding memory address.

3. HiFive, Clint, Plic, Uart8250, VirtIOMMIO
Devicetree node generation function is added.

4. tlb, faults
Unnecessary includes of arch/riscv/fs_workload are removed.

Change-Id: Ia239b5614bd93d8e794330ead266f6121a4d13cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42053
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2021-03-24 02:47:30 +00:00
Gabe Black
5ffd619d38 arch,cpu: Move TheISA::copyRegs to TheISA::ISA::copyRegsFrom.
This eliminates the last externally used function in arch/utility.hh.

Change-Id: I7f402b0303e2758762e19d69f3bed37262cc9289
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39336
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2021-03-22 21:01:33 +00:00
Daniel R. Carvalho
2922f763e1 misc: Fix coding style for struct's opening braces
The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, 2 and 3 levels of indentation (and a single
occurrence of 2 and 3 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *struct [A-Za-z].* {$" src/

Then the following commands were run to replace:

<indent level>struct X ... {

by:

<indent level>struct X ...
<indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc
        "^struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^struct ([A-Za-z].*) \{$/struct \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    struct [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    struct ([A-Za-z].*) \{$/    struct \1\n    \{/g'

and so on.

Change-Id: I362ef58c86912dabdd272c7debb8d25d587cd455
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39017
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-03-19 20:57:24 +00:00
Giacomo Travaglini
41928dac80 misc: Remove unused params() definitions
Lots of times the params() helper has been defined but not used

Change-Id: Id71829aca71341d46964d8f071099342b946b62f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41613
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-19 23:27:34 +00:00
Alexander Klimov
92ba3ba843 misc: Use PARAMS
The patch is using the newly defined PARAMS macro to replace
custom params() getters in derived class.

The patch is also removing redundant _params:
Instead of creating yet another _params field, SimObject descendants
should use params() to expose the real type of SimObject::_params they
already have.

Change-Id: I43394cebb9661fe747bdbb332236f0f0181b3dba
Signed-off-by: Alexander Klimov <Alexander.Klimov@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39900
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-02-19 23:27:34 +00:00
Gabe Black
d05a0a4ea1 misc: Delete the now unnecessary create methods.
Most create() methods are no longer necessary. This change deletes them,
and occasionally moves some code from them into the constructors they
call.

Change-Id: Icbab29ba280144b892f9b12fac9e29a0839477e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36536
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-30 04:00:20 +00:00
Gabe Black
a78abf07b7 riscv: Implement an SE workload for Linux.
Change-Id: Ieb7058007e56ce0c8d153c1853e4b92237e98ab8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34156
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-29 01:34:41 +00:00
Gabe Black
91d83cc8a1 misc: Standardize the way create() constructs SimObjects.
The create() method on Params structs usually instantiate SimObjects
using a constructor which takes the Params struct as a parameter
somehow. There has been a lot of needless variation in how that was
done, making it annoying to pass Params down to base classes. Some of
the different forms were:

const Params &
Params &
Params *
const Params *
Params const*

This change goes through and fixes up every constructor and every
create() method to use the const Params & form. We use a reference
because the Params struct should never be null. We use const because
neither the create method nor the consuming object should modify the
record of the parameters as they came in from the config. That would
make consuming them not idempotent, and make it impossible to tell what
the actual simulation configuration was since it would change from any
user visible form (config script, config.ini, dot pdf output).

Change-Id: I77453cba52fdcfd5f4eec92dfb0bddb5a9945f31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35938
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-10-14 12:06:44 +00:00
Andreas Sandberg
51992fa80a base, sim: Make ByteOrder into a ScopedEnum accessible to Python
There is currently no good way of passing a byte order as a Param
since the ByteOrder type is defined in C++. Make this into a generated
ScopedEnum that can be used in Params.

Change-Id: I990f402340c17c4e0799de57df19516ae61794d4
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
2020-09-08 16:24:00 +00:00
Gabe Black
21fdd4290b misc: Remove the "fault" parameter from syscall functions.
This parameter was never set or used, just plumbed everywhere,
occasionally with a dummy value. This change removes all of that
plumbing.

Change-Id: I9bc31ffd1fbc4952c5d3096f7f21eab30102300b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33277
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2020-09-02 03:30:20 +00:00
Gabe Black
93a01dba47 arch: Use VPtr for uname.
Change-Id: Ia4b6c9135f16e6c68bbcf3a9c15ba7433a0a6682
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29403
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
2020-08-05 23:52:25 +00:00
Gabe Black
9884641603 base,arch,sim,cpu: Move object file loader components into a namespace.
The components in base/loader were moved into a namespace called
Loader. This will make it easier to add loader components with fairly
short natural names which don't invite name collisions.

gem5 should use namespaces more in general for that reason and to make
it easier to write independent components without having to worry about
name collisions being added in the future.

Unfortunately this namespace has the same name as a class used to load
an object file into a process object. These names can be disambiguated
because the Process loader is inside the Process scope and the Loader
namespace is at global scope, but it's still confusing to read.

Fortunately, this shouldn't last for very long since the responsibility
for loading Processes is going to move to a fake OS object which will
expect to load a particular type of Process, for instance, fake 64 bit
x86 linux will load either 32 or 64 bit x86 processes.

That means that the capability to feed any binary that matches the
current build into gem5 and have gem5 figure out what to do with it
will likely be going away in the future. That's likely for the best,
since it will force users to be more explicit about what they're trying
to do, ie what OS they want to try to load a given binary, and also
will prevent loading two or more Processes which are for different OSes
to the same system, something that's possible today as far as I know
since there are no consistency checks.

Change-Id: Iea0012e98f39f5e20a7c351b78cdff9401f5e326
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24783
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-04-22 06:08:54 +00:00
Gabe Black
cd69bb5041 arch,sim: Merge Process::syscall and Process::getDesc.
When handling a system call, external code would call Process::syscall
which would extract the syscall number, that would call the base
class' doSyscall method, that would call into the subclass' getDesc
to get the appropriate descriptor, and then doSyscall would check
that a syscall was found and call into it.

Instead, we can just make the SyscallDescTable optionally check for
missing syscalls (in case we want to check multiple tables), and
make syscall look up the appropriate descriptor and call it. The base
implementation of syscall would then do the only bit of doSyscall that
is no longer being handled, incrementing the numSyscalls stat.

Change-Id: If102c156830ed2997d177dc6937cc85dddadf3f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24119
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2020-03-20 10:04:18 +00:00
Gabe Black
a63b853320 arch,sim: Drop the syscall number from the syscall func signature.
This value is almost never used, and is now part of the SyscallDesc.

Change-Id: Ia4ffc19774bb2eac8f29134e3765c06a264407b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24118
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-20 10:04:18 +00:00
Gabe Black
ab8d484c27 arch,sim: Create a common structure to hold syscall tables.
Also add the syscall number into the SyscallDesc class.

The common table structure is basically just a map that extracts its
key value from the SyscallDesc class using a new num() accessor. By
using a map instead of an array (like RISCV was already doing), it's
easy to support gaps of arbitrary size and non-zero offsets of groups
of system calls without lots of filler or additional logic. This
simplified the ARM system call tables in particular which had a lot
of filler entries.

Also, both the 32 and 64 bit ARM syscall tables had entries for a
syscall at 123456 which was the "Angel SWI system call". This value
is actually the immediate constant passed to the SWI system call
instruction and is not interpreted as the system call number in linux.
This constant can be intercepted by hardware or a simulator to, for
instance, implement ARM semihosting.

Also, that constant in combination with the SWI instruction is only
used for semihosting in 32 bit ARM mode, not in 64 bit mode or in
thumb.

Since checking for that system call number was very likely a mistake
from misinterpreting how the semihosting calls work, this change
drops those checks.

Change-Id: I9b2a902d7326791449cf0e1b98e932dcadba54f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24117
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
2020-03-20 10:04:18 +00:00
Gabe Black
7b0cd2d59e riscv: Use a riscv specific GuestABI for riscv system calls.
Change-Id: Ia6ac34dfb38b71eff7b573b3c9ce477fef0ef5f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23453
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-12 01:35:34 +00:00
Gabe Black
33593d77f9 riscv: Convert RISCV specific syscalls to Guest ABI.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I1a7041ba890f5f69d5506583c658ae6a777b5daf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23202
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-12 00:43:28 +00:00
Gabe Black
ca867678a6 arch,sim: Convert clone to GuestABI and define a cloneBackwardsFunc.
cloneBackwardsFunc takes its arguments in the order specified for
ARM and RISCV. Because of the new GuestABI mechanism, it can be a
simple wrapper around the normal clone implementation without the need
for #ifdefs.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Iff1ffd6774b9162185a124585e9507a5bdbc46f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23198
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-03-12 00:43:28 +00:00
Gabe Black
5d5f53378b riscv: Delete authors lists from riscv files.
Change-Id: I94135c8f0e1baee741d6470cb80b4da5e5f8e673
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25451
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-18 03:36:09 +00:00
Gabe Black
4aa277a865 arch: Add a bunch of missing override specifiers.
Missing override on methods which are overriding virtual methods causes
warnings/errors on certain compilers.

Change-Id: I16f565fa07bfcb399a0209cd87f1f9729cd89b2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25223
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-10 22:31:12 +00:00
Gabe Black
97a0ad7f63 arch,sim: Replace setuidFunc with ignoreFunc.
The setuidFunc just ignores the call and warns about it, and that's
what ignoreFunc already does.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I7655863ed6fe200ff3ac087be3218d49c3c43061
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23194
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-08 13:05:45 +00:00