derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
14,196 Commits 2 Branches 0 Tags
b16e525e4073b27f70bf6cf960313ea76cf6ed54
Commit Graph

14196 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Gabe Black
b16e525e40 cpu: Move the instruction port into o3's fetch stage. 
That's where it's used, and that avoids having to pass it around using
the top level getInstPort accessor.

Change-Id: I489a3f3239b3116292f3dcd78a3945fb468c6311
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20239
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
 2019-08-28 02:14:53 +00:00
Gabe Black
b4e3e2f4a4 cpu: Move O3's data port into the LSQ. 
That's where it's used, and putting it there avoids having to pass
around the port using the top level getDataPort function.

Change-Id: I0dea25d0c5f4bb3f58a6574a8f2b2d242784caf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20238
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
 2019-08-28 02:14:29 +00:00
Gabe Black
c387a212d9 mem: Eliminate the Base(Slave|Master)Port classes. 
The Port class has assumed all the duties of the less generic
Base*Port classes, making them unnecessary. Since they don't add
anything but make the code more complex, this change eliminates them.

Change-Id: Ibb9c56def04465f353362595c1f1c5ac5083e5e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20236
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
 2019-08-28 02:14:21 +00:00
Gabe Black
4d503eeffe cpu, dev, mem: Use the new Port methods. 
Use getPeer, takeOverFrom, and << to simplify the use of ports in some
areas.

Change-Id: Idfbda27411b5d6b742f5e4927894302ea6d6a53d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20235
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-08-27 22:18:28 +00:00
Gabe Black
f4f31b261c sim: Add a << overload for the Port class which prints its name. 
This makes it easier/less verbose to print the name of a port, it's
most important and identifying feature, in a DPRINTF or other stream
based output.

Change-Id: I050d102844612577f9a83d550e619736507a6781
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20234
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-08-27 22:18:10 +00:00
Gabe Black
51d46ef4c6 sim: Add a takeOverFrom method to the base Port class. 
This makes it easier, safer, and less verbose to swap out ports when
a CPU takes over for another CPU, for instance.

Change-Id: Ice08e4dcb4b04dc66b1841331092a78b4f6f5a96
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20233
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
 2019-08-27 22:17:57 +00:00
Gabe Black
2a566b4fa7 mem, sim, systemc: Reorganize Port and co.s bind, unbind slightly. 
The base Port class can keep track of its peer, and also whether it's
connected. This is partially delegated away from the port subclasses
which still keep track of a cast version of their peer pointer for
their own conveneince, so that it can be used by generic code. Even
with the Port mechanism's new flexibility, each port still has
exactly one peer and is either connected or not based on whether there
is a peer currently.

Change-Id: Id3228617dd1604d196814254a1aadeac5ade7cde
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20232
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
 2019-08-27 22:17:45 +00:00
Giacomo Travaglini
3126e84db7 dev-arm: Fix GICv3 ITS indexing error 
Table walks were not considering the entry size when evaluating
the address.

Change-Id: Ica6bf6d88632985ee8ed120448b32e0f7e918a8a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20329
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-26 09:29:53 +00:00
Giacomo Travaglini
b90fcd7357 dev-arm: Fix GITS_BASER initialization/access 
The patch is fixing/improving GITS_BASER registers initialization.

* Not using reserved table types anymore (GITS_BASER.TYPE)
* Using write mask for handling WI bits

Change-Id: Ibe24667fdf22b42b86496167c19fc00bbb0ba191
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20328
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-26 09:29:53 +00:00
Alec Roelke
579c2cd54b arch-riscv: fix GDB register cache 
Fixes the definition of the RISC-V GDB register cache.  The latest
version, of RISC-V gdb, commit c3eb4078520dad8234ffd7fbf893ac0da23ad3c8,
appears to only accept the 32 integer registers + the PC in the 'g'
packet.

This functions with the Linux toolchain (riscv64-unknown-linux-gnu-*),
but works best with the Newlib toolchain (riscv64-unknown-elf-*).

Change-Id: Ie35ea89a45870fb634e6c68236261bde27c86e41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20028
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-23 23:13:40 +00:00
Gabe Black
41f38a559b mem: Put gem5 protocols in their own directory. 
This reduces clutter in the src/mem directory, and makes it clear that
those protocols are for the classic gem5 memory system, not ruby, TLM,
etc.

Change-Id: I6cf6b21134d82f4f01991e4fe92dbea8c7e82081
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20231
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-08-23 21:13:33 +00:00
Gabe Black
c08351f4d3 mem: Move ruby protocols into a directory called ruby_protocol. 
Now that the gem5 protocols are split out, it would be nice to put them
in their own protocol directory. It's also confusing to have files
called *_protocol which are not in the protocol directory.

Change-Id: I7475ee111630050a2421816dfd290921baab9f71
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-23 21:13:07 +00:00
Gabe Black
d97e4e1dd0 mem: Split the various protocols out of the gem5 master/slave ports. 
This makes the protocols easier to see in their entirity, and makes it
easier to add a new type of port which only supports the functional
protocol.

Change-Id: If5d639bef45062f0a23af2ac46f50933e6a8f144
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20228
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-08-23 09:04:13 +00:00
Ciro Santilli
34b22c298c mem-ruby: fix build with PROTOCOL=MOESI_hammer 
Was failing with:

Error: Unrecognized variable: l1i_victim_addr

since: I2c43f22aba5af3a57e54b1c435e5d3fbba86d1d5

Change-Id: I7df666acb724ee541804dd7557753a9ba4005516
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20261
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-22 10:37:41 +00:00
Giacomo Travaglini
f8fbeae6fc dev-arm: Start using GITS_CTLR.quiescent bit 
The GITS_CTLR.quiescent bit is used by priviledged sw to check when the
ITS has finished draining its state (all pending translations/table
walks have ended) once it has been disabled (by setting the
GITS_CTLR.enable bit to 0).
This patch is modelling this behaviour by

* Changing the reset state to enable=0, quiescent=1
* Making the GITS_CTLR.quiescent bit RO
* Updating the bit once a new translation/command is being processed
(quiescent=0) and when there are no pending translation/commands
(quiescent=1)

Change-Id: I7cfe94b25d603400364b1cdfc2d2397acf5dfad8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20257
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-22 08:49:00 +00:00
Giacomo Travaglini
bd8c9614da dev-arm: Allow 32 bit accesses to GITS_C(WRITER/READR/BASER) 
For those registers (GITS_CWRITER, GITS_READR and GITS_CBASER)
Bits [63:32] and bits [31:0] are accessible separately.

Change-Id: Ibf60b5e4fd20efb21a63570e6012862e37946877
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20256
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-22 08:49:00 +00:00
Adrian Herrera
8e73f1d497 dev-arm,system-arm: missing GICv3 ranges property 
This patch adds the device tree "ranges" property to GICv3 for
the VExpress_GEM5_V2 platform. It is also included in the GICv3 DTB
auto generation.
This allows the GICv3 ITS to be specified in the device tree.

Change-Id: I00e1bb0fd45521e34820c0a23ddf047afec7aa4c
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20255
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-22 08:49:00 +00:00
Adrian Herrera
441fa07f8c configs: root, platform options in fs bigLITTLE 
(1) Two new options are added to fs_bigLITTLE.py:
    - "root": disk/partition containing the rootfs (def. "/dev/vda1")
    - "machine-type": hardware platform class (def. "VExpress_GEM5_V1")
        + Accepts platform classes from PlatformConfig
(2) Default kernel is not available in public uploads, force the user
    to provide its own kernel instead of crashing.

Change-Id: I88283ae12cd7289e15b9277ea2cc382e9136f11c
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20148
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-21 17:54:23 +00:00
Yifei Liu
d3a87a87b4 arch-riscv: Update register file 
This patch adds mcounteren, scounteren according to Risc-V
Privileged Architectures V1.10.

Change-Id: I6e138a50710bc0a1e9d9c38a11fc7fcc09ed500e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20128
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-21 17:52:54 +00:00
Ciro Santilli
76358df574 arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0 
In src/cpu/reg_class.hh, numPinnedWrites was unset because the
constructors were not well factored out.

Change-Id: Ib2fc8d34a1adf5c48826d257a31dd24dfa64a08a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20048
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-21 12:17:17 +00:00
Ciro Santilli
acad54cf4e base: assert that stats bucket size is greater than 0 
Change-Id: I9a2264e9ee74acea1f09f01ea8f5004567ba1ea8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20049
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-21 12:16:48 +00:00
Chun-Chen TK Hsu
b192aed7e7 arch-arm: Fix implicit fallthrough build errors 
1942b21713 introduced implicit-fallthrough errors when compiled with
GCC 8.  This change adds M5_UNREACHABLE in the default case.

Change-Id: I220f2b3fe39b5c3a65c0dd390915bffeafb28962
Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20268
Reviewed-by: Jordi Vaquero <jordi.vaquero@metempsy.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-21 11:35:23 +00:00
Giacomo Travaglini
869053c8fa dev-arm: Add redistributor-stride property to GICv3 
This is needed since by default the model is assuming a GICv4
memory layout.

Change-Id: Ic64e6a488cc1a43a56ce28f6d11b8868df102aa0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20248
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-20 14:23:47 +00:00
Giacomo Travaglini
20990ad5e9 arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currEL 
Change-Id: I739a9be03ea5caa63540c62fd110eee86a058c4c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20252
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-20 14:23:19 +00:00
Giacomo Travaglini
e97a1fe390 arch-arm: Replace direct use cpsr.el with currEL helper 
The patch is replacing it in places where the current EL could be using
AArch32, hence leading to an incorrect ExceptionLevel.

Change-Id: I99b75af2668f2c38fd88bec62e985ab7dbea80dc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20251
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-20 14:23:19 +00:00
Giacomo Travaglini
4ccb1ea710 arch-arm: Overload currEL helper with CPSR argument 
Change-Id: I1edabc61637ecb9d30bca34b5dbcf1de12b35fe0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20250
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-20 14:23:19 +00:00
Giacomo Travaglini
befa49ffb7 arch-arm: Rewrite the currEL helper method to use opModeToEL 
Direct use of cpsr.el should be discouraged: it should be used when
in AArch64 only; when in AArch32 it won't return the matching EL.

Eg: when in Supervisor Mode (EL1), CPSR.M<3,0> (mode) is 0b0011,
and cpsr.el will return 0 (EL0)

Change-Id: I5504bd1f59980f79b2607cce435ea09245de12e5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20249
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-20 14:23:19 +00:00
Giacomo Travaglini
8ec72b4fba dev-arm: Add GITS_PIDR2 register to the ITS memory map 
The GITS Peripheral Identification Register #2 bits assignments are the
same as those for GICD_PIDR2.

Change-Id: I235008a383e08dd557d899cb3aa18202ef943f8b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20254
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-20 12:22:51 +00:00
Giacomo Travaglini
705fe5ef44 dev-arm: Add Gicv3Distributor members for GICv3 GICD_PIDRx 
There is no need of calculating the value every time the registers
are read.

Change-Id: I58b87abb585fb9928959992927f00d9c000a4c35
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20253
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-20 12:22:51 +00:00
Pablo Prieto
4bcb6023f1 mem-ruby, arch-hsail: Removed hit latency from VIPERCoalescer 
Removed the dcache hit latency from VIPERCoalescer so HSAIL_X86
compiles after commit 496d5ed3e1

Change-Id: I050a58d90f0f6356824c3c3bcb3f0b3c76d145e0
Signed-off-by: Pablo Prieto <pablo.prieto@unican.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19148
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-19 17:00:33 +00:00
Gabe Black
c7f18da6b0 x86: Stop CPUID from claiming we support xsave. 
xsave is a fairly complex feature which we don't support in gem5, but
we do report that we support it through CPUID. It looks like I confused
it with FXSAVE which is an instruction related to SSE. This change
turns that bit back off again.

Change-Id: I00fc79168c5f7095b5241e870a4c8782e4385425
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20169
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-16 01:05:01 +00:00
Gabe Black
023aca7755 x86: Make unsuccessful CPUID instructions zero the result. 
The previous implementation left the registers unmodified which is
technically correct since there is no defined behavior in that case or
a fault to raise. That would make what happened when the following code
consumed the result unpredictable because it would depend on what junk
values were left in the registers. This was originally not a problem
since the space of supported functions were tightly packed, but someone
added a new function with a gap without adjusting this behavior.

This change makes CPUID zero out RAX, RBX, RCX, and RDX when it fails.
That should be more predictable and cause less flakey failures.

Change-Id: If6ffb17c2969d34aff1600c0ffc32333d0b9be44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20168
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-15 02:53:04 +00:00
Gabe Black
5e83d70352 sim: Add a hook Clocked objects can implement for frequency changes. 
This hook will let them implement whatever additional behavior is
necessary for when the clock changes.

An alternative design for this might have made the "update" function
virtual, and required anyone overriding it to call into the base class.
I think that would be an inferior design for two reasons. First, the
subclass author might forget to call update. Second, while it might
*seem* like this would have some performance benefit since you wouldn't
call into the virtual function and then call update, incurring the
function call overhead twice, you're going to call into update once
regardless, and then you're either going to call the virtual funciton
which does nothing (the norm) or does something. In either case you
call the same functions the same number of times.

There may be a slight penalty in code size since the call to update
may be inlined in the call sights before the virtual function, and
there will almost certainly be more of those than there would be
implementations of the virtual function, but that should be negligable
when compared to gem5's size as a whole.

Change-Id: Id25a5359f2b1f7e42c6d1dcbc70a37d3ce092d38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20089
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-08-13 22:32:31 +00:00
Gabe Black
ea8c435b6c sim: Clean up some mild style bugs in clocked_object.hh. 
Clean up some formatting, and also remove redundant inline keywords.
A function defined in place in a class definition is already
automatically inline.

Change-Id: Iaad3a8dda6498c6a6068c2aabc9d6eb11f3d2eb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20088
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-13 02:21:52 +00:00
Pouya Fotouhi
444a49d110 mem-ruby: Use check_on_cache_probe on MI 
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MI.

Change-Id: I276822e987e52f7682ff30f55880f295b6af023d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19888
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
 2019-08-13 00:52:27 +00:00
Pouya Fotouhi
def0a4c6fd mem-ruby: Use check_on_cache_probe on MOESI hammer 
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MOESI hammer.

Change-Id: I2c43f22aba5af3a57e54b1c435e5d3fbba86d1d5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19891
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
 2019-08-13 00:52:16 +00:00
Pouya Fotouhi
8b4f2ca902 mem-ruby: Use check_on_cache_probe on MOESI CMP 
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MOESI CMP.

Change-Id: I3a8879e10ebd94ef68194836475e656761fed62c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19908
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
 2019-08-13 00:52:05 +00:00
Pouya Fotouhi
4651f36193 mem-ruby: Use check_on_cache_probe on MOESI 
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MOESI.

Change-Id: Ie650ccdc15bb41b4088e534975b662408aaccf24
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19890
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
 2019-08-13 00:51:54 +00:00
Jordi Vaquero
1942b21713 arch-arm: Added LD/ST<op> atomic instruction family and SWP instrs 
Adding LD/ST/SWP family of instructions, LD/ST include a set of
operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN
This commit includes:
+ Instruction decode
+ Instruction functional code
+ New set of skeletons for Ex/Com/Ini/Constructor and declaration.

Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19812
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2019-08-12 20:22:53 +00:00
Pouya Fotouhi
507a0cecc5 mem-ruby: Use check_on_cache_probe to protect locked lines from eviction 
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MESI Three Level.

Change-Id: Ib0de54aa067c7603db1f7321cc4825b123b641ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19868
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-12 18:21:28 +00:00
Pouya Fotouhi
e424be8281 mem-ruby: Use check_on_cache_probe to protect locked lines from eviction 
This change uses check_on_cache_probe statement to check if the cacheline
subject to eviction is locked in MESI Two Level. Other protocols should
be updated accordingly.

Signed-off-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Change-Id: Idcdbc8ee528eb5e4e2f8d56a268a3a92eadd95b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16809
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-12 18:17:56 +00:00
Giacomo Travaglini
fd95c68485 dev-arm: Enable DTB autogeneration in GICv3 
Change-Id: I539ae5ae74bc6f42f291441594a0d14c98e687f4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20053
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-12 18:17:45 +00:00
Giacomo Travaglini
377860544f dev-arm: Fix PCI node's interrupt-map property 
The PCI host has an interrupt-map property which only works for a fixed
setup of parent/child interrupt/address cells, which currently overlaps
with GICv2.
We want to make this flexible, so that the interrupt-map doesn't break
if we change the interrupt/address-cells value, and the patch is aiming
in that direction.  This is also needed for GICv3 DTB autogeneration,
since it is using different values than GICv2.

Change-Id: If1c661ddcbc0c277c9d6b0e44a0fd3fe2427618c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20052
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-12 18:17:45 +00:00
Giacomo Travaglini
5e3b9693c8 dev-arm: Use FdtState to generate GIC properites 
Rather than hardcoding property values, we use a FdtState variable, so
that it is possible to retrieve them from an external object.

Change-Id: Ifd90814b03c68a7f55ef3be6123dcfee5e1de568
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20051
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-12 18:17:45 +00:00
Giacomo Travaglini
91419e3682 python: FdtState using interrupt-cells 
Change-Id: I37813748f518b442d2b53c2bc4f381edb2e26146
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20050
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-12 18:17:45 +00:00
Jordi Vaquero
00b3d2c5bc arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func 
CAS/CASP atomic instruction implementation
This change includes:
+ Instructions decode
+ new amo64.isa file where CAS/CASP main functional code is implemented
+ mem64.isa include Execute/complete/initiatie skeletons,
contructor and declarator
+ Added TypedAtomic function for pair register CASP instruction

Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19811
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
 2019-08-12 17:21:36 +00:00
Brandon Potter
f4d21fa24a sim-se: rename Process::setpgid member 
The getter methods to access these types of members do not
have a 'get' string in the method names. To make the interface
a bit more consistent, remove the 'set' part of the member name.

Change-Id: I04c56bd9d9feb1cf68ff50a1152083ea57ea7c62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20008
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-12 16:49:54 +00:00
Andreas Sandberg
dbf18ac111 misc: Update MAINTAINERS with a system tag 
The code in system/ currently doesn't have a well-defined tag. Arm
components have traditionally used 'system-arm' and in some cases just
'arm'. This change introduces a separate tag for system software and
related files components.

Change-Id: I5c0ecd057bd65ab9d88c25f7ec7572d6941e41b5
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19931
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2019-08-12 10:26:36 +00:00
Gabe Black
cc3d89b6c1 cpu: Pull more arch specialization to the top of BaseCPU.py. 
This simplifies the logic of the CPU python class, and brings us ever
so slightly closer to factoring hardcoded ISA behavior out of non-ISA
specific components.

Change-Id: I7e4511dd4e6076f5c214be5af2a0e33af0142563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19889
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-08-10 07:12:37 +00:00
Chun-Chen TK Hsu
f320cba1df system-arm: Refactor makefile to create targets with functions 
This change simplifies writing targets which has same prefix but
differrent number of CPUs.

Change-Id: I3b7d67a554f5d27714ace6b88c9784ddaa3b34d5
Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19989
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
 2019-08-10 05:20:31 +00:00